1 /*
2 * Generic intermediate code generation.
3 *
4 * Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu>
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
9
10 #ifndef EXEC__TRANSLATOR_H
11 #define EXEC__TRANSLATOR_H
12
13 /*
14 * Include this header from a target-specific file, and add a
15 *
16 * DisasContextBase base;
17 *
18 * member in your target-specific DisasContext.
19 */
20
21 #include "qemu/bswap.h"
22 #include "exec/vaddr.h"
23
24 /**
25 * gen_intermediate_code
26 * @cpu: cpu context
27 * @tb: translation block
28 * @max_insns: max number of instructions to translate
29 * @pc: guest virtual program counter address
30 * @host_pc: host physical program counter address
31 *
32 * This function must be provided by the target, which should create
33 * the target-specific DisasContext, and then invoke translator_loop.
34 */
35 void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
36 vaddr pc, void *host_pc);
37
38 /**
39 * DisasJumpType:
40 * @DISAS_NEXT: Next instruction in program order.
41 * @DISAS_TOO_MANY: Too many instructions translated.
42 * @DISAS_NORETURN: Following code is dead.
43 * @DISAS_TARGET_*: Start of target-specific conditions.
44 *
45 * What instruction to disassemble next.
46 */
47 typedef enum DisasJumpType {
48 DISAS_NEXT,
49 DISAS_TOO_MANY,
50 DISAS_NORETURN,
51 DISAS_TARGET_0,
52 DISAS_TARGET_1,
53 DISAS_TARGET_2,
54 DISAS_TARGET_3,
55 DISAS_TARGET_4,
56 DISAS_TARGET_5,
57 DISAS_TARGET_6,
58 DISAS_TARGET_7,
59 DISAS_TARGET_8,
60 DISAS_TARGET_9,
61 DISAS_TARGET_10,
62 DISAS_TARGET_11,
63 } DisasJumpType;
64
65 /**
66 * DisasContextBase:
67 * @tb: Translation block for this disassembly.
68 * @pc_first: Address of first guest instruction in this TB.
69 * @pc_next: Address of next guest instruction in this TB (current during
70 * disassembly).
71 * @is_jmp: What instruction to disassemble next.
72 * @num_insns: Number of translated instructions (including current).
73 * @max_insns: Maximum number of instructions to be translated in this TB.
74 * @singlestep_enabled: "Hardware" single stepping enabled.
75 * @plugin_enabled: TCG plugin enabled in this TB.
76 * @fake_insn: True if translator_fake_ldb used.
77 * @insn_start: The last op emitted by the insn_start hook,
78 * which is expected to be INDEX_op_insn_start.
79 *
80 * Architecture-agnostic disassembly context.
81 */
82 struct DisasContextBase {
83 TranslationBlock *tb;
84 vaddr pc_first;
85 vaddr pc_next;
86 DisasJumpType is_jmp;
87 int num_insns;
88 int max_insns;
89 bool singlestep_enabled;
90 bool plugin_enabled;
91 bool fake_insn;
92 struct TCGOp *insn_start;
93 void *host_addr[2];
94
95 /*
96 * Record insn data that we cannot read directly from host memory.
97 * There are only two reasons we cannot use host memory:
98 * (1) We are executing from I/O,
99 * (2) We are executing a synthetic instruction (s390x EX).
100 * In both cases we need record exactly one instruction,
101 * and thus the maximum amount of data we record is limited.
102 */
103 int record_start;
104 int record_len;
105 uint8_t record[32];
106 };
107
108 /**
109 * TranslatorOps:
110 * @init_disas_context:
111 * Initialize the target-specific portions of DisasContext struct.
112 * The generic DisasContextBase has already been initialized.
113 *
114 * @tb_start:
115 * Emit any code required before the start of the main loop,
116 * after the generic gen_tb_start().
117 *
118 * @insn_start:
119 * Emit the tcg_gen_insn_start opcode.
120 *
121 * @translate_insn:
122 * Disassemble one instruction and set db->pc_next for the start
123 * of the following instruction. Set db->is_jmp as necessary to
124 * terminate the main loop.
125 *
126 * @tb_stop:
127 * Emit any opcodes required to exit the TB, based on db->is_jmp.
128 *
129 * @disas_log:
130 * Print instruction disassembly to log.
131 */
132 typedef struct TranslatorOps {
133 void (*init_disas_context)(DisasContextBase *db, CPUState *cpu);
134 void (*tb_start)(DisasContextBase *db, CPUState *cpu);
135 void (*insn_start)(DisasContextBase *db, CPUState *cpu);
136 void (*translate_insn)(DisasContextBase *db, CPUState *cpu);
137 void (*tb_stop)(DisasContextBase *db, CPUState *cpu);
138 bool (*disas_log)(const DisasContextBase *db, CPUState *cpu, FILE *f);
139 } TranslatorOps;
140
141 /**
142 * translator_loop:
143 * @cpu: Target vCPU.
144 * @tb: Translation block.
145 * @max_insns: Maximum number of insns to translate.
146 * @pc: guest virtual program counter address
147 * @host_pc: host physical program counter address
148 * @ops: Target-specific operations.
149 * @db: Disassembly context.
150 *
151 * Generic translator loop.
152 *
153 * Translation will stop in the following cases (in order):
154 * - When is_jmp set by #TranslatorOps::breakpoint_check.
155 * - set to DISAS_TOO_MANY exits after translating one more insn
156 * - set to any other value than DISAS_NEXT exits immediately.
157 * - When is_jmp set by #TranslatorOps::translate_insn.
158 * - set to any value other than DISAS_NEXT exits immediately.
159 * - When the TCG operation buffer is full.
160 * - When single-stepping is enabled (system-wide or on the current vCPU).
161 * - When too many instructions have been translated.
162 */
163 void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
164 vaddr pc, void *host_pc, const TranslatorOps *ops,
165 DisasContextBase *db);
166
167 /**
168 * translator_use_goto_tb
169 * @db: Disassembly context
170 * @dest: target pc of the goto
171 *
172 * Return true if goto_tb is allowed between the current TB
173 * and the destination PC.
174 */
175 bool translator_use_goto_tb(DisasContextBase *db, vaddr dest);
176
177 /**
178 * translator_io_start
179 * @db: Disassembly context
180 *
181 * If icount is enabled, set cpu->can_do_io, adjust db->is_jmp to
182 * DISAS_TOO_MANY if it is still DISAS_NEXT, and return true.
183 * Otherwise return false.
184 */
185 bool translator_io_start(DisasContextBase *db);
186
187 /*
188 * Translator Load Functions
189 *
190 * These are intended to replace the direct usage of the cpu_ld*_code
191 * functions and are mandatory for front-ends that have been migrated
192 * to the common translator_loop. These functions are only intended
193 * to be called from the translation stage and should not be called
194 * from helper functions. Those functions should be converted to encode
195 * the relevant information at translation time.
196 */
197
198 uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, vaddr pc);
199 uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, vaddr pc);
200 uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, vaddr pc);
201 uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, vaddr pc);
202
203 static inline uint16_t
translator_lduw_swap(CPUArchState * env,DisasContextBase * db,vaddr pc,bool do_swap)204 translator_lduw_swap(CPUArchState *env, DisasContextBase *db,
205 vaddr pc, bool do_swap)
206 {
207 uint16_t ret = translator_lduw(env, db, pc);
208 if (do_swap) {
209 ret = bswap16(ret);
210 }
211 return ret;
212 }
213
214 static inline uint32_t
translator_ldl_swap(CPUArchState * env,DisasContextBase * db,vaddr pc,bool do_swap)215 translator_ldl_swap(CPUArchState *env, DisasContextBase *db,
216 vaddr pc, bool do_swap)
217 {
218 uint32_t ret = translator_ldl(env, db, pc);
219 if (do_swap) {
220 ret = bswap32(ret);
221 }
222 return ret;
223 }
224
225 static inline uint64_t
translator_ldq_swap(CPUArchState * env,DisasContextBase * db,vaddr pc,bool do_swap)226 translator_ldq_swap(CPUArchState *env, DisasContextBase *db,
227 vaddr pc, bool do_swap)
228 {
229 uint64_t ret = translator_ldq(env, db, pc);
230 if (do_swap) {
231 ret = bswap64(ret);
232 }
233 return ret;
234 }
235
236 /**
237 * translator_fake_ld - fake instruction load
238 * @db: Disassembly context
239 * @data: bytes of instruction
240 * @len: number of bytes
241 *
242 * This is a special case helper used where the instruction we are
243 * about to translate comes from somewhere else (e.g. being
244 * re-synthesised for s390x "ex"). It ensures we update other areas of
245 * the translator with details of the executed instruction.
246 */
247 void translator_fake_ld(DisasContextBase *db, const void *data, size_t len);
248
249 /**
250 * translator_st
251 * @db: disassembly context
252 * @dest: address to copy into
253 * @addr: virtual address within TB
254 * @len: length
255 *
256 * Copy @len bytes from @addr into @dest.
257 * All bytes must have been read during translation.
258 * Return true on success or false on failure.
259 */
260 bool translator_st(const DisasContextBase *db, void *dest,
261 vaddr addr, size_t len);
262
263 /**
264 * translator_st_len
265 * @db: disassembly context
266 *
267 * Return the number of bytes available to copy from the
268 * current translation block with translator_st.
269 */
270 size_t translator_st_len(const DisasContextBase *db);
271
272 #ifdef COMPILING_PER_TARGET
273 /*
274 * Return whether addr is on the same page as where disassembly started.
275 * Translators can use this to enforce the rule that only single-insn
276 * translation blocks are allowed to cross page boundaries.
277 */
is_same_page(const DisasContextBase * db,vaddr addr)278 static inline bool is_same_page(const DisasContextBase *db, vaddr addr)
279 {
280 return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) == 0;
281 }
282 #endif
283
284 #endif /* EXEC__TRANSLATOR_H */
285