1// -*- verilog -*- 2// 3// USRP - Universal Software Radio Peripheral 4// 5// Copyright (C) 2003 Matt Ettus 6// 7// This program is free software; you can redistribute it and/or modify 8// it under the terms of the GNU General Public License as published by 9// the Free Software Foundation; either version 2 of the License, or 10// (at your option) any later version. 11// 12// This program is distributed in the hope that it will be useful, 13// but WITHOUT ANY WARRANTY; without even the implied warranty of 14// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15// GNU General Public License for more details. 16// 17// You should have received a copy of the GNU General Public License 18// along with this program; if not, write to the Free Software 19// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA 20// 21 22 23 24module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr); 25 parameter depth = 4; 26 parameter width = 16; 27 parameter size = 16; 28 29 input wclk; 30 input [width-1:0] wdata; 31 input [depth-1:0] waddr; 32 input wen; 33 34 input rclk; 35 output reg [width-1:0] rdata; 36 input [depth-1:0] raddr; 37 38 reg [width-1:0] ram [0:size-1]; 39 40 always @(posedge wclk) 41 if(wen) 42 ram[waddr] <= #1 wdata; 43 44 always @(posedge rclk) 45 rdata <= #1 ram[raddr]; 46 47endmodule // dpram 48