1// -*- verilog -*- 2// 3// USRP - Universal Software Radio Peripheral 4// 5// Copyright (C) 2003 Matt Ettus 6// 7// This program is free software; you can redistribute it and/or modify 8// it under the terms of the GNU General Public License as published by 9// the Free Software Foundation; either version 2 of the License, or 10// (at your option) any later version. 11// 12// This program is distributed in the hope that it will be useful, 13// but WITHOUT ANY WARRANTY; without even the implied warranty of 14// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15// GNU General Public License for more details. 16// 17// You should have received a copy of the GNU General Public License 18// along with this program; if not, write to the Free Software 19// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA 20// 21 22module gen_sync 23 ( input clock, 24 input reset, 25 input enable, 26 input [7:0] rate, 27 output wire sync ); 28 29// parameter width = 8; 30 31 reg [7:0] counter; 32 assign sync = |(((rate+1)>>1)& counter); 33 34 always @(posedge clock) 35 if(reset || ~enable) 36 counter <= #1 0; 37 else if(counter == rate) 38 counter <= #1 0; 39 else 40 counter <= #1 counter + 8'd1; 41 42endmodule // gen_sync 43 44