1// -*- verilog -*- 2// 3// USRP - Universal Software Radio Peripheral 4// 5// Copyright (C) 2003 Matt Ettus 6// 7// This program is free software; you can redistribute it and/or modify 8// it under the terms of the GNU General Public License as published by 9// the Free Software Foundation; either version 2 of the License, or 10// (at your option) any later version. 11// 12// This program is distributed in the hope that it will be useful, 13// but WITHOUT ANY WARRANTY; without even the implied warranty of 14// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15// GNU General Public License for more details. 16// 17// You should have received a copy of the GNU General Public License 18// along with this program; if not, write to the Free Software 19// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA 20// 21 22module tx_chain 23 (input clock, 24 input reset, 25 input enable, 26 input wire [7:0] interp_rate, 27 input sample_strobe, 28 input interpolator_strobe, 29 input wire [31:0] freq, 30 input wire [15:0] i_in, 31 input wire [15:0] q_in, 32 output wire [15:0] i_out, 33 output wire [15:0] q_out 34 ); 35 36 wire [15:0] bb_i, bb_q; 37 38 cic_interp cic_interp_i 39 ( .clock(clock),.reset(reset),.enable(enable), 40 .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe), 41 .signal_in(i_in),.signal_out(bb_i) ); 42 43 cic_interp cic_interp_q 44 ( .clock(clock),.reset(reset),.enable(enable), 45 .rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe), 46 .signal_in(q_in),.signal_out(bb_q) ); 47 48`define NOCORDIC_TX 49`ifdef NOCORDIC_TX 50 assign i_out = bb_i; 51 assign q_out = bb_q; 52`else 53 wire [31:0] phase; 54 55 phase_acc phase_acc_tx 56 (.clk(clock),.reset(reset),.enable(enable), 57 .strobe(sample_strobe),.freq(freq),.phase(phase) ); 58 59 cordic tx_cordic_0 60 ( .clock(clock),.reset(reset),.enable(sample_strobe), 61 .xi(bb_i),.yi(bb_q),.zi(phase[31:16]), 62 .xo(i_out),.yo(q_out),.zo() ); 63`endif 64 65endmodule // tx_chain 66