1// -*- verilog -*- 2// 3// USRP - Universal Software Radio Peripheral 4// 5// Copyright (C) 2003,2004,2005,2006 Matt Ettus 6// Copyright (C) 2006 Martin Dudok van Heel 7// 8// This program is free software; you can redistribute it and/or modify 9// it under the terms of the GNU General Public License as published by 10// the Free Software Foundation; either version 2 of the License, or 11// (at your option) any later version. 12// 13// This program is distributed in the hope that it will be useful, 14// but WITHOUT ANY WARRANTY; without even the implied warranty of 15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16// GNU General Public License for more details. 17// 18// You should have received a copy of the GNU General Public License 19// along with this program; if not, write to the Free Software 20// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA 21// 22 23// Top level module for a full setup with DUCs and DDCs 24 25// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins 26// for debugging info. NB, This can kill the m'board and/or d'board if you 27// have anything except basic d'boards installed. 28 29// Uncomment the following to include optional circuitry 30 31`include "config.vh" 32`include "../../common/fpga_regs_common.v" 33`include "../../common/fpga_regs_standard.v" 34 35module usrp_multi 36(output MYSTERY_SIGNAL, 37 input master_clk, 38 input SCLK, 39 input SDI, 40 inout SDO, 41 input SEN_FPGA, 42 43 input FX2_1, 44 output FX2_2, 45 output FX2_3, 46 47 input wire [11:0] rx_a_a, 48 input wire [11:0] rx_b_a, 49 input wire [11:0] rx_a_b, 50 input wire [11:0] rx_b_b, 51 52 output wire [13:0] tx_a, 53 output wire [13:0] tx_b, 54 55 output wire TXSYNC_A, 56 output wire TXSYNC_B, 57 58 // USB interface 59 input usbclk, 60 input wire [2:0] usbctl, 61 output wire [1:0] usbrdy, 62 inout [15:0] usbdata, // NB Careful, inout 63 64 // These are the general purpose i/o's that go to the daughterboard slots 65 inout wire [15:0] io_tx_a, 66 inout wire [15:0] io_tx_b, 67 inout wire [15:0] io_rx_a, 68 inout wire [15:0] io_rx_b 69 ); 70 wire [15:0] debugdata,debugctrl; 71 assign MYSTERY_SIGNAL = 1'b0; 72 73 wire clk64,clk128; 74 75 wire WR = usbctl[0]; 76 wire RD = usbctl[1]; 77 wire OE = usbctl[2]; 78 79 wire have_space, have_pkt_rdy; 80 assign usbrdy[0] = have_space; 81 assign usbrdy[1] = have_pkt_rdy; 82 83 wire tx_underrun, rx_overrun; 84 wire clear_status = FX2_1; 85 assign FX2_2 = rx_overrun; 86 assign FX2_3 = tx_underrun; 87 88 wire [15:0] usbdata_out; 89 90 wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; 91 92 wire tx_realsignals; 93 wire [3:0] rx_numchan; 94 wire [2:0] tx_numchan; 95 96 wire [7:0] interp_rate, decim_rate; 97 wire [15:0] tx_debugbus, rx_debugbus; 98 99 wire enable_tx, enable_rx; 100 wire reset_data; 101`ifdef MULTI_ON 102 wire sync_rx; 103 assign reset_data = sync_rx; 104`else 105 assign reset_data = 1'b0; 106`endif // `ifdef MULTI_ON 107 108 wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; 109 wire [7:0] settings; 110 111 // Tri-state bus macro 112 bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); 113 114 assign clk64 = master_clk; 115 116 wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx; 117 wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; 118 119 // TX 120 wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1; 121 wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3; 122 123 wire strobe_interp, tx_sample_strobe; 124 wire tx_empty; 125 126 wire serial_strobe; 127 wire [6:0] serial_addr; 128 wire [31:0] serial_data; 129 130 reg [15:0] debug_counter; 131`ifdef COUNTER_32BIT_ON 132 reg [31:0] sample_counter_32bit; 133`endif // `ifdef COUNTER_32BIT_ON 134 reg [15:0] loopback_i_0,loopback_q_0; 135 136 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 137 // Transmit Side 138`ifdef TX_ON 139 assign bb_tx_i0 = ch0tx; 140 assign bb_tx_q0 = ch1tx; 141 assign bb_tx_i1 = ch2tx; 142 assign bb_tx_q1 = ch3tx; 143 144 tx_buffer tx_buffer 145 ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset), 146 .usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun), 147 .channels({tx_numchan,1'b0}), 148 .tx_i_0(ch0tx),.tx_q_0(ch1tx), 149 .tx_i_1(ch2tx),.tx_q_1(ch3tx), 150 .tx_i_2(),.tx_q_2(), 151 .tx_i_3(),.tx_q_3(), 152 .txclk(clk64),.txstrobe(strobe_interp), 153 .clear_status(clear_status), 154 .tx_empty(tx_empty), 155 .debugbus(tx_debugbus) ); 156 157 tx_chain tx_chain_0 158 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), 159 .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), 160 .interpolator_strobe(strobe_interp),.freq(), 161 .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) ); 162 163 tx_chain tx_chain_1 164 ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx), 165 .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe), 166 .interpolator_strobe(strobe_interp),.freq(), 167 .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) ); 168 169 setting_reg #(`FR_TX_MUX) 170 sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), 171 .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); 172 173 wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0; 174 wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0; 175 wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0; 176 wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0; 177 178 wire txsync = tx_sample_strobe; 179 assign TXSYNC_A = txsync; 180 assign TXSYNC_B = txsync; 181 182 assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2]; 183 assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2]; 184`endif // `ifdef TX_ON 185 186 ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 187 // Receive Side 188`ifdef RX_ON 189 wire rx_sample_strobe,strobe_decim,hb_strobe; 190 wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1, 191 bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3; 192 193 wire loopback = settings[0]; 194 wire counter = settings[1]; 195`ifdef COUNTER_32BIT_ON 196 wire counter_32bit = settings[2]; 197 198 always @(posedge clk64) 199 if(rx_dsp_reset) 200 sample_counter_32bit <= #1 32'd0; 201 else if(~enable_rx | reset_data) 202 sample_counter_32bit <=#1 32'd0; 203 else if(hb_strobe) 204 sample_counter_32bit <=#1 sample_counter_32bit + 32'd1; 205`endif // `ifdef COUNTER_32BIT_ON 206 207 always @(posedge clk64) 208 if(rx_dsp_reset) 209 debug_counter <= #1 16'd0; 210 else if(~enable_rx) 211 debug_counter <= #1 16'd0; 212 else if(hb_strobe) 213 debug_counter <=#1 debug_counter + 16'd2; 214 215 always @(posedge clk64) 216 if(strobe_interp) 217 begin 218 loopback_i_0 <= #1 ch0tx; 219 loopback_q_0 <= #1 ch1tx; 220 end 221 222`ifdef COUNTER_32BIT_ON 223 assign ch0rx = counter_32bit?sample_counter_32bit[31:16]:counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; 224 assign ch1rx = counter_32bit?sample_counter_32bit[15:0]:counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; 225 assign ch2rx = bb_rx_i1; 226 assign ch3rx = bb_rx_q1; 227 assign ch4rx = counter_32bit?bb_rx_i0:bb_rx_i2; 228 assign ch5rx = counter_32bit?bb_rx_q0:bb_rx_q2;// If using counter replicate channels here to be able to get rx_i0 when using counter 229 //This means if you use 4 channels that channel 3 will be replaced by channel 0 230 // and channel 0 will output the 32 bit counter. 231 assign ch6rx = bb_rx_i3; 232 assign ch7rx = bb_rx_q3; 233`else 234 assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0; 235 assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0; 236 assign ch2rx = bb_rx_i1; 237 assign ch3rx = bb_rx_q1; 238 assign ch4rx = bb_rx_i2; 239 assign ch5rx = bb_rx_q2; 240 assign ch6rx = bb_rx_i3; 241 assign ch7rx = bb_rx_q3; 242`endif // `ifdef COUNTER_32BIT_ON 243 244 245 wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q; 246 adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1), 247 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 248 .rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b), 249 .ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q), 250 .ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q), 251 .ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q), 252 .ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) ); 253 254 rx_buffer rx_buffer 255 ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset | reset_data), 256 .reset_regs(rx_dsp_reset), 257 .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), 258 .channels(rx_numchan), 259 .ch_0(ch0rx),.ch_1(ch1rx), 260 .ch_2(ch2rx),.ch_3(ch3rx), 261 .ch_4(ch4rx),.ch_5(ch5rx), 262 .ch_6(ch6rx),.ch_7(ch7rx), 263 .rxclk(clk64),.rxstrobe(hb_strobe), 264 .clear_status(clear_status), 265 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 266 .debugbus(rx_debugbus) ); 267 268 `ifdef RX_EN_0 269 rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0 270 ( .clock(clk64),.reset(reset_data),.enable(enable_rx), 271 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe), 272 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 273 .i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl)); 274 `else 275 assign bb_rx_i0=16'd0; 276 assign bb_rx_q0=16'd0; 277 `endif 278 279 `ifdef RX_EN_1 280 rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1 281 ( .clock(clk64),.reset(reset_data),.enable(enable_rx), 282 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), 283 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 284 .i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1)); 285 `else 286 assign bb_rx_i1=16'd0; 287 assign bb_rx_q1=16'd0; 288 `endif 289 290 `ifdef RX_EN_2 291 rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2 292 ( .clock(clk64),.reset(reset_data),.enable(enable_rx), 293 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), 294 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 295 .i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2)); 296 `else 297 assign bb_rx_i2=16'd0; 298 assign bb_rx_q2=16'd0; 299 `endif 300 301 `ifdef RX_EN_3 302 rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3 303 ( .clock(clk64),.reset(reset_data),.enable(enable_rx), 304 .decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(), 305 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 306 .i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3)); 307 assign bb_rx_i3=16'd0; 308 assign bb_rx_q3=16'd0; 309 `endif 310 311`endif // `ifdef RX_ON 312 313 /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 314 // Control Functions 315 316 wire [31:0] capabilities; 317 assign capabilities[7] = `TX_CAP_HB; 318 assign capabilities[6:4] = `TX_CAP_NCHAN; 319 assign capabilities[3] = `RX_CAP_HB; 320 assign capabilities[2:0] = `RX_CAP_NCHAN; 321 322 323 serial_io serial_io 324 ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), 325 .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), 326 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 327 .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a) ); 328 329 wire [15:0] reg_0,reg_1,reg_2,reg_3; 330 331`ifdef MULTI_ON 332 333 master_control_multi master_control 334 ( .master_clk(clk64),.usbclk(usbclk), 335 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 336 .rx_slave_sync(io_rx_a[`bitnoFR_RX_SYNC_INPUT_IOPIN]), 337 .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), 338 .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), 339 .enable_tx(enable_tx),.enable_rx(enable_rx), 340 .sync_rx(sync_rx), 341 .interp_rate(interp_rate),.decim_rate(decim_rate), 342 .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), 343 .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), 344 .tx_empty(tx_empty), 345 //.debug_0(rx_a_a),.debug_1(ddc0_in_i), 346 .debug_0(rx_debugbus),.debug_1(ddc0_in_i), 347 .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), 348 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); 349 350`else //`ifdef MULTI_ON 351 352 master_control master_control 353 ( .master_clk(clk64),.usbclk(usbclk), 354 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), 355 .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), 356 .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), 357 .enable_tx(enable_tx),.enable_rx(enable_rx), 358 .interp_rate(interp_rate),.decim_rate(decim_rate), 359 .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), 360 .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), 361 .tx_empty(tx_empty), 362 //.debug_0(rx_a_a),.debug_1(ddc0_in_i), 363 .debug_0(rx_debugbus),.debug_1(ddc0_in_i), 364 .debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}), 365 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); 366 367`endif //`ifdef MULTI_ON 368 369 io_pins io_pins 370 (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), 371 .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), 372 .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), 373 .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); 374 375 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// 376 // Misc Settings 377 setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings)); 378 379endmodule // usrp_multi 380