1// 2// Copyright 2011 Ettus Research LLC 3// 4// This program is free software: you can redistribute it and/or modify 5// it under the terms of the GNU General Public License as published by 6// the Free Software Foundation, either version 3 of the License, or 7// (at your option) any later version. 8// 9// This program is distributed in the hope that it will be useful, 10// but WITHOUT ANY WARRANTY; without even the implied warranty of 11// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12// GNU General Public License for more details. 13// 14// You should have received a copy of the GNU General Public License 15// along with this program. If not, see <http://www.gnu.org/licenses/>. 16// 17 18module fifo_to_wb_tb(); 19 20 reg clk = 0; 21 reg rst = 1; 22 reg clear = 0; 23 initial #1000 rst = 0; 24 always #50 clk = ~clk; 25 26 reg trigger = 0; 27 initial #10000 trigger = 1; 28 29 wire wb_cyc, wb_stb, wb_we, wb_ack; 30 wire [15:0] wb_adr; 31 wire [15:0] wb_dat_miso, wb_dat_mosi; 32 33 reg cmd_src_rdy; 34 wire cmd_dst_rdy, resp_src_rdy, resp_dst_rdy; 35 reg [17:0] cmd; 36 wire [17:0] resp; 37 38 wire [17:0] resp_int; 39 wire resp_src_rdy_int, resp_dst_rdy_int; 40 41 fifo_to_wb fifo_to_wb 42 (.clk(clk), .reset(rst), .clear(clear), 43 .data_i(cmd), .src_rdy_i(cmd_src_rdy), .dst_rdy_o(cmd_dst_rdy), 44 .data_o(resp_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int), 45 46 .wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), 47 .wb_sel_o(), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb), 48 .wb_we_o(wb_we), .wb_ack_i(wb_ack), 49 .triggers()); 50 51 assign wb_dat_miso = {wb_adr[7:0],8'hBF}; 52 53 fifo19_pad #(.LENGTH(16)) fifo19_pad 54 (.clk(clk), .reset(rst), .clear(clear), 55 .data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), 56 .data_o(resp), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy)); 57 58 59 // Set up monitors 60 always @(posedge clk) 61 if(wb_cyc & wb_stb & wb_ack) 62 if(wb_we) 63 $display("WB-WRITE ADDR:%h DATA:%h",wb_adr, wb_dat_mosi); 64 else 65 $display("WB-READ ADDR:%h DATA:%h",wb_adr, wb_dat_miso); 66 67 always @(posedge clk) 68 if(cmd_src_rdy & cmd_dst_rdy) 69 $display("CMD-WRITE SOF:%b EOF:%b DATA:%h",cmd[16],cmd[17],cmd[15:0]); 70 71 always @(posedge clk) 72 if(resp_src_rdy & resp_dst_rdy) 73 $display("RESP-READ SOF:%b EOF:%b DATA:%h",resp[16],resp[17],resp[15:0]); 74 75 assign wb_ack = wb_stb; 76 assign resp_dst_rdy = 1; 77 78 task InsertRW; 79 input [15:0] data_start; 80 input [5:0] triggers; 81 input [7:0] seqno; 82 input [15:0] len; 83 input [15:0] addr; 84 reg [15:0] data_val; 85 86 begin 87 data_val <= data_start; 88 @(posedge clk); 89 cmd <= {2'b01,2'b11,triggers,seqno}; 90 cmd_src_rdy <= 1; 91 @(posedge clk); 92 cmd <= {2'b00,len}; 93 @(posedge clk); 94 cmd <= {2'b00,addr}; 95 @(posedge clk); 96 cmd <= {2'b00,16'd0}; 97 @(posedge clk); 98 repeat (len) 99 begin 100 cmd <= {2'b00,data_val}; 101 data_val <= data_val + 1; 102 @(posedge clk); 103 end 104 repeat (12-len-1) 105 begin 106 cmd <= {2'b00,16'hBEEF}; 107 @(posedge clk); 108 end 109 cmd <= {2'b10, 16'hDEAD}; 110 @(posedge clk); 111 cmd_src_rdy <= 0; 112 end 113 endtask // InsertRead 114 115 initial $dumpfile("fifo_to_wb_tb.vcd"); 116 initial $dumpvars(0,fifo_to_wb_tb); 117 118 initial 119 begin 120 @(negedge rst); 121 //#10000; 122 @(posedge clk); 123 @(posedge clk); 124 @(posedge clk); 125 @(posedge clk); 126 InsertRW(16'hF00D, 6'd0, 8'hB5, 16'd7, 16'h1234); 127 #20000; 128 InsertRW(16'h9876, 6'd0, 8'h43, 16'd8, 16'hBEEF); 129 #20000; 130 InsertRW(16'h1000, 6'd0, 8'h96, 16'd4, 16'hF00D); 131 #20000; 132 InsertRW(16'h3000, 6'd0, 8'h12, 16'd10,16'hDEAD); 133 #20000 $finish; 134 end 135 136endmodule // fifo_to_wb_tb 137