1// 2// Copyright 2011 Ettus Research LLC 3// 4// This program is free software: you can redistribute it and/or modify 5// it under the terms of the GNU General Public License as published by 6// the Free Software Foundation, either version 3 of the License, or 7// (at your option) any later version. 8// 9// This program is distributed in the hope that it will be useful, 10// but WITHOUT ANY WARRANTY; without even the implied warranty of 11// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12// GNU General Public License for more details. 13// 14// You should have received a copy of the GNU General Public License 15// along with this program. If not, see <http://www.gnu.org/licenses/>. 16// 17 18 19module gpif_rd 20 (input gpif_clk, input gpif_rst, 21 output [15:0] gpif_data, input gpif_rd, input gpif_ep, 22 output reg gpif_empty_d, output reg gpif_empty_c, 23 output reg gpif_flush, 24 25 input sys_clk, input sys_rst, 26 input [18:0] data_i, input src_rdy_i, output dst_rdy_o, 27 input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, 28 output [31:0] debug 29 ); 30 31 wire [18:0] data_o; // occ bit indicates flush 32 wire [17:0] resp_o; // no occ bit 33 wire final_rdy_data, final_rdy_resp; 34 35 // 33/257 Bug Fix 36 reg [8:0] read_count; 37 always @(negedge gpif_clk) 38 if(gpif_rst) 39 read_count <= 0; 40 else if(gpif_rd) 41 read_count <= read_count + 1; 42 else 43 read_count <= 0; 44 45 // Data Path 46 wire [18:0] data_int; 47 wire src_rdy_int, dst_rdy_int; 48 fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk 49 (.wclk(sys_clk), .datain(data_i[18:0]), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), 50 .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), 51 .arst(sys_rst)); 52 53 reg [7:0] packet_count; 54 wire consume_data_line = gpif_rd & ~gpif_ep & ~read_count[8]; 55 wire produce_eop = src_rdy_int & dst_rdy_int & data_int[17]; 56 wire consume_sop = consume_data_line & final_rdy_data & data_o[16]; 57 wire consume_eop = consume_data_line & final_rdy_data & data_o[17]; 58 59 fifo_cascade #(.WIDTH(19), .SIZE(10)) rd_fifo 60 (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), 61 .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), 62 .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(consume_data_line), .occupied()); 63 64 always @(negedge gpif_clk) 65 if(gpif_rst) 66 packet_count <= 0; 67 else 68 if(produce_eop & ~consume_sop) 69 packet_count <= packet_count + 1; 70 else if(consume_sop & ~produce_eop) 71 packet_count <= packet_count - 1; 72 73 always @(negedge gpif_clk) 74 if(gpif_rst) 75 gpif_empty_d <= 1; 76 else 77 gpif_empty_d <= ~|packet_count; 78 79 // Use occ bit to signal a gpif flush 80 always @(negedge gpif_clk) 81 if(gpif_rst) 82 gpif_flush <= 0; 83 else if(consume_eop & data_o[18]) 84 gpif_flush <= ~gpif_flush; 85 86 // Response Path 87 wire [15:0] resp_fifolevel; 88 wire consume_resp_line = gpif_rd & gpif_ep & ~read_count[4]; 89 90 fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk 91 (.wclk(sys_clk), .datain(resp_i[17:0]), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(), 92 .rclk(~gpif_clk), .dataout(resp_o), 93 .src_rdy_o(final_rdy_resp), .dst_rdy_i(consume_resp_line), .occupied(resp_fifolevel), 94 .arst(sys_rst)); 95 96 // FIXME -- handle short packets 97 98 always @(negedge gpif_clk) 99 if(gpif_rst) 100 gpif_empty_c <= 1; 101 else 102 gpif_empty_c <= resp_fifolevel < 16; 103 104 // Output Mux 105 assign gpif_data = gpif_ep ? resp_o[15:0] : data_o[15:0]; 106 107 assign debug = { { 16'd0 }, 108 { data_int[17:16], data_o[17:16], packet_count[3:0] }, 109 { consume_sop, consume_eop, final_rdy_data, data_o[18], consume_data_line, consume_resp_line, src_rdy_int, dst_rdy_int} }; 110 111endmodule // gpif_rd 112