xref: /linux/drivers/comedi/drivers/gsc_hpdi.c (revision df0e68c1)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * gsc_hpdi.c
4  * Comedi driver the General Standards Corporation
5  * High Speed Parallel Digital Interface rs485 boards.
6  *
7  * Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
8  * Copyright (C) 2003 Coherent Imaging Systems
9  *
10  * COMEDI - Linux Control and Measurement Device Interface
11  * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
12  */
13 
14 /*
15  * Driver: gsc_hpdi
16  * Description: General Standards Corporation High
17  *    Speed Parallel Digital Interface rs485 boards
18  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
19  * Status: only receive mode works, transmit not supported
20  * Updated: Thu, 01 Nov 2012 16:17:38 +0000
21  * Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
22  *   PMC-HPDI32
23  *
24  * Configuration options:
25  *    None.
26  *
27  * Manual configuration of supported devices is not supported; they are
28  * configured automatically.
29  *
30  * There are some additional hpdi models available from GSC for which
31  * support could be added to this driver.
32  */
33 
34 #include <linux/module.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/comedi/comedi_pci.h>
38 
39 #include "plx9080.h"
40 
41 /*
42  * PCI BAR2 Register map (dev->mmio)
43  */
44 #define FIRMWARE_REV_REG			0x00
45 #define FEATURES_REG_PRESENT_BIT		BIT(15)
46 #define BOARD_CONTROL_REG			0x04
47 #define BOARD_RESET_BIT				BIT(0)
48 #define TX_FIFO_RESET_BIT			BIT(1)
49 #define RX_FIFO_RESET_BIT			BIT(2)
50 #define TX_ENABLE_BIT				BIT(4)
51 #define RX_ENABLE_BIT				BIT(5)
52 #define DEMAND_DMA_DIRECTION_TX_BIT		BIT(6)  /* ch 0 only */
53 #define LINE_VALID_ON_STATUS_VALID_BIT		BIT(7)
54 #define START_TX_BIT				BIT(8)
55 #define CABLE_THROTTLE_ENABLE_BIT		BIT(9)
56 #define TEST_MODE_ENABLE_BIT			BIT(31)
57 #define BOARD_STATUS_REG			0x08
58 #define COMMAND_LINE_STATUS_MASK		(0x7f << 0)
59 #define TX_IN_PROGRESS_BIT			BIT(7)
60 #define TX_NOT_EMPTY_BIT			BIT(8)
61 #define TX_NOT_ALMOST_EMPTY_BIT			BIT(9)
62 #define TX_NOT_ALMOST_FULL_BIT			BIT(10)
63 #define TX_NOT_FULL_BIT				BIT(11)
64 #define RX_NOT_EMPTY_BIT			BIT(12)
65 #define RX_NOT_ALMOST_EMPTY_BIT			BIT(13)
66 #define RX_NOT_ALMOST_FULL_BIT			BIT(14)
67 #define RX_NOT_FULL_BIT				BIT(15)
68 #define BOARD_JUMPER0_INSTALLED_BIT		BIT(16)
69 #define BOARD_JUMPER1_INSTALLED_BIT		BIT(17)
70 #define TX_OVERRUN_BIT				BIT(21)
71 #define RX_UNDERRUN_BIT				BIT(22)
72 #define RX_OVERRUN_BIT				BIT(23)
73 #define TX_PROG_ALMOST_REG			0x0c
74 #define RX_PROG_ALMOST_REG			0x10
75 #define ALMOST_EMPTY_BITS(x)			(((x) & 0xffff) << 0)
76 #define ALMOST_FULL_BITS(x)			(((x) & 0xff) << 16)
77 #define FEATURES_REG				0x14
78 #define FIFO_SIZE_PRESENT_BIT			BIT(0)
79 #define FIFO_WORDS_PRESENT_BIT			BIT(1)
80 #define LEVEL_EDGE_INTERRUPTS_PRESENT_BIT	BIT(2)
81 #define GPIO_SUPPORTED_BIT			BIT(3)
82 #define PLX_DMA_CH1_SUPPORTED_BIT		BIT(4)
83 #define OVERRUN_UNDERRUN_SUPPORTED_BIT		BIT(5)
84 #define FIFO_REG				0x18
85 #define TX_STATUS_COUNT_REG			0x1c
86 #define TX_LINE_VALID_COUNT_REG			0x20,
87 #define TX_LINE_INVALID_COUNT_REG		0x24
88 #define RX_STATUS_COUNT_REG			0x28
89 #define RX_LINE_COUNT_REG			0x2c
90 #define INTERRUPT_CONTROL_REG			0x30
91 #define FRAME_VALID_START_INTR			BIT(0)
92 #define FRAME_VALID_END_INTR			BIT(1)
93 #define TX_FIFO_EMPTY_INTR			BIT(8)
94 #define TX_FIFO_ALMOST_EMPTY_INTR		BIT(9)
95 #define TX_FIFO_ALMOST_FULL_INTR		BIT(10)
96 #define TX_FIFO_FULL_INTR			BIT(11)
97 #define RX_EMPTY_INTR				BIT(12)
98 #define RX_ALMOST_EMPTY_INTR			BIT(13)
99 #define RX_ALMOST_FULL_INTR			BIT(14)
100 #define RX_FULL_INTR				BIT(15)
101 #define INTERRUPT_STATUS_REG			0x34
102 #define TX_CLOCK_DIVIDER_REG			0x38
103 #define TX_FIFO_SIZE_REG			0x40
104 #define RX_FIFO_SIZE_REG			0x44
105 #define FIFO_SIZE_MASK				(0xfffff << 0)
106 #define TX_FIFO_WORDS_REG			0x48
107 #define RX_FIFO_WORDS_REG			0x4c
108 #define INTERRUPT_EDGE_LEVEL_REG		0x50
109 #define INTERRUPT_POLARITY_REG			0x54
110 
111 #define TIMER_BASE				50	/* 20MHz master clock */
112 #define DMA_BUFFER_SIZE				0x10000
113 #define NUM_DMA_BUFFERS				4
114 #define NUM_DMA_DESCRIPTORS			256
115 
116 struct hpdi_private {
117 	void __iomem *plx9080_mmio;
118 	u32 *dio_buffer[NUM_DMA_BUFFERS];	/* dma buffers */
119 	/* physical addresses of dma buffers */
120 	dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
121 	/*
122 	 * array of dma descriptors read by plx9080, allocated to get proper
123 	 * alignment
124 	 */
125 	struct plx_dma_desc *dma_desc;
126 	/* physical address of dma descriptor array */
127 	dma_addr_t dma_desc_phys_addr;
128 	unsigned int num_dma_descriptors;
129 	/* pointer to start of buffers indexed by descriptor */
130 	u32 *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
131 	/* index of the dma descriptor that is currently being used */
132 	unsigned int dma_desc_index;
133 	unsigned int tx_fifo_size;
134 	unsigned int rx_fifo_size;
135 	unsigned long dio_count;
136 	/* number of bytes at which to generate COMEDI_CB_BLOCK events */
137 	unsigned int block_size;
138 };
139 
gsc_hpdi_drain_dma(struct comedi_device * dev,unsigned int channel)140 static void gsc_hpdi_drain_dma(struct comedi_device *dev, unsigned int channel)
141 {
142 	struct hpdi_private *devpriv = dev->private;
143 	struct comedi_subdevice *s = dev->read_subdev;
144 	struct comedi_cmd *cmd = &s->async->cmd;
145 	unsigned int idx;
146 	unsigned int start;
147 	unsigned int desc;
148 	unsigned int size;
149 	unsigned int next;
150 
151 	next = readl(devpriv->plx9080_mmio + PLX_REG_DMAPADR(channel));
152 
153 	idx = devpriv->dma_desc_index;
154 	start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
155 	/* loop until we have read all the full buffers */
156 	for (desc = 0; (next < start || next >= start + devpriv->block_size) &&
157 	     desc < devpriv->num_dma_descriptors; desc++) {
158 		/* transfer data from dma buffer to comedi buffer */
159 		size = devpriv->block_size / sizeof(u32);
160 		if (cmd->stop_src == TRIG_COUNT) {
161 			if (size > devpriv->dio_count)
162 				size = devpriv->dio_count;
163 			devpriv->dio_count -= size;
164 		}
165 		comedi_buf_write_samples(s, devpriv->desc_dio_buffer[idx],
166 					 size);
167 		idx++;
168 		idx %= devpriv->num_dma_descriptors;
169 		start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
170 
171 		devpriv->dma_desc_index = idx;
172 	}
173 	/* XXX check for buffer overrun somehow */
174 }
175 
gsc_hpdi_interrupt(int irq,void * d)176 static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
177 {
178 	struct comedi_device *dev = d;
179 	struct hpdi_private *devpriv = dev->private;
180 	struct comedi_subdevice *s = dev->read_subdev;
181 	struct comedi_async *async = s->async;
182 	u32 hpdi_intr_status, hpdi_board_status;
183 	u32 plx_status;
184 	u32 plx_bits;
185 	u8 dma0_status, dma1_status;
186 	unsigned long flags;
187 
188 	if (!dev->attached)
189 		return IRQ_NONE;
190 
191 	plx_status = readl(devpriv->plx9080_mmio + PLX_REG_INTCSR);
192 	if ((plx_status &
193 	     (PLX_INTCSR_DMA0IA | PLX_INTCSR_DMA1IA | PLX_INTCSR_PLIA)) == 0)
194 		return IRQ_NONE;
195 
196 	hpdi_intr_status = readl(dev->mmio + INTERRUPT_STATUS_REG);
197 	hpdi_board_status = readl(dev->mmio + BOARD_STATUS_REG);
198 
199 	if (hpdi_intr_status)
200 		writel(hpdi_intr_status, dev->mmio + INTERRUPT_STATUS_REG);
201 
202 	/* spin lock makes sure no one else changes plx dma control reg */
203 	spin_lock_irqsave(&dev->spinlock, flags);
204 	dma0_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR0);
205 	if (plx_status & PLX_INTCSR_DMA0IA) {
206 		/* dma chan 0 interrupt */
207 		writeb((dma0_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
208 		       devpriv->plx9080_mmio + PLX_REG_DMACSR0);
209 
210 		if (dma0_status & PLX_DMACSR_ENABLE)
211 			gsc_hpdi_drain_dma(dev, 0);
212 	}
213 	spin_unlock_irqrestore(&dev->spinlock, flags);
214 
215 	/* spin lock makes sure no one else changes plx dma control reg */
216 	spin_lock_irqsave(&dev->spinlock, flags);
217 	dma1_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR1);
218 	if (plx_status & PLX_INTCSR_DMA1IA) {
219 		/* XXX */ /* dma chan 1 interrupt */
220 		writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
221 		       devpriv->plx9080_mmio + PLX_REG_DMACSR1);
222 	}
223 	spin_unlock_irqrestore(&dev->spinlock, flags);
224 
225 	/* clear possible plx9080 interrupt sources */
226 	if (plx_status & PLX_INTCSR_LDBIA) {
227 		/* clear local doorbell interrupt */
228 		plx_bits = readl(devpriv->plx9080_mmio + PLX_REG_L2PDBELL);
229 		writel(plx_bits, devpriv->plx9080_mmio + PLX_REG_L2PDBELL);
230 	}
231 
232 	if (hpdi_board_status & RX_OVERRUN_BIT) {
233 		dev_err(dev->class_dev, "rx fifo overrun\n");
234 		async->events |= COMEDI_CB_ERROR;
235 	}
236 
237 	if (hpdi_board_status & RX_UNDERRUN_BIT) {
238 		dev_err(dev->class_dev, "rx fifo underrun\n");
239 		async->events |= COMEDI_CB_ERROR;
240 	}
241 
242 	if (devpriv->dio_count == 0)
243 		async->events |= COMEDI_CB_EOA;
244 
245 	comedi_handle_events(dev, s);
246 
247 	return IRQ_HANDLED;
248 }
249 
gsc_hpdi_abort_dma(struct comedi_device * dev,unsigned int channel)250 static void gsc_hpdi_abort_dma(struct comedi_device *dev, unsigned int channel)
251 {
252 	struct hpdi_private *devpriv = dev->private;
253 	unsigned long flags;
254 
255 	/* spinlock for plx dma control/status reg */
256 	spin_lock_irqsave(&dev->spinlock, flags);
257 
258 	plx9080_abort_dma(devpriv->plx9080_mmio, channel);
259 
260 	spin_unlock_irqrestore(&dev->spinlock, flags);
261 }
262 
gsc_hpdi_cancel(struct comedi_device * dev,struct comedi_subdevice * s)263 static int gsc_hpdi_cancel(struct comedi_device *dev,
264 			   struct comedi_subdevice *s)
265 {
266 	writel(0, dev->mmio + BOARD_CONTROL_REG);
267 	writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
268 
269 	gsc_hpdi_abort_dma(dev, 0);
270 
271 	return 0;
272 }
273 
gsc_hpdi_cmd(struct comedi_device * dev,struct comedi_subdevice * s)274 static int gsc_hpdi_cmd(struct comedi_device *dev,
275 			struct comedi_subdevice *s)
276 {
277 	struct hpdi_private *devpriv = dev->private;
278 	struct comedi_async *async = s->async;
279 	struct comedi_cmd *cmd = &async->cmd;
280 	unsigned long flags;
281 	u32 bits;
282 
283 	if (s->io_bits)
284 		return -EINVAL;
285 
286 	writel(RX_FIFO_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
287 
288 	gsc_hpdi_abort_dma(dev, 0);
289 
290 	devpriv->dma_desc_index = 0;
291 
292 	/*
293 	 * These register are supposedly unused during chained dma,
294 	 * but I have found that left over values from last operation
295 	 * occasionally cause problems with transfer of first dma
296 	 * block.  Initializing them to zero seems to fix the problem.
297 	 */
298 	writel(0, devpriv->plx9080_mmio + PLX_REG_DMASIZ0);
299 	writel(0, devpriv->plx9080_mmio + PLX_REG_DMAPADR0);
300 	writel(0, devpriv->plx9080_mmio + PLX_REG_DMALADR0);
301 
302 	/* give location of first dma descriptor */
303 	bits = devpriv->dma_desc_phys_addr | PLX_DMADPR_DESCPCI |
304 	       PLX_DMADPR_TCINTR | PLX_DMADPR_XFERL2P;
305 	writel(bits, devpriv->plx9080_mmio + PLX_REG_DMADPR0);
306 
307 	/* enable dma transfer */
308 	spin_lock_irqsave(&dev->spinlock, flags);
309 	writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR,
310 	       devpriv->plx9080_mmio + PLX_REG_DMACSR0);
311 	spin_unlock_irqrestore(&dev->spinlock, flags);
312 
313 	if (cmd->stop_src == TRIG_COUNT)
314 		devpriv->dio_count = cmd->stop_arg;
315 	else
316 		devpriv->dio_count = 1;
317 
318 	/* clear over/under run status flags */
319 	writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, dev->mmio + BOARD_STATUS_REG);
320 
321 	/* enable interrupts */
322 	writel(RX_FULL_INTR, dev->mmio + INTERRUPT_CONTROL_REG);
323 
324 	writel(RX_ENABLE_BIT, dev->mmio + BOARD_CONTROL_REG);
325 
326 	return 0;
327 }
328 
gsc_hpdi_check_chanlist(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)329 static int gsc_hpdi_check_chanlist(struct comedi_device *dev,
330 				   struct comedi_subdevice *s,
331 				   struct comedi_cmd *cmd)
332 {
333 	int i;
334 
335 	for (i = 0; i < cmd->chanlist_len; i++) {
336 		unsigned int chan = CR_CHAN(cmd->chanlist[i]);
337 
338 		if (chan != i) {
339 			dev_dbg(dev->class_dev,
340 				"chanlist must be ch 0 to 31 in order\n");
341 			return -EINVAL;
342 		}
343 	}
344 
345 	return 0;
346 }
347 
gsc_hpdi_cmd_test(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)348 static int gsc_hpdi_cmd_test(struct comedi_device *dev,
349 			     struct comedi_subdevice *s,
350 			     struct comedi_cmd *cmd)
351 {
352 	int err = 0;
353 
354 	if (s->io_bits)
355 		return -EINVAL;
356 
357 	/* Step 1 : check if triggers are trivially valid */
358 
359 	err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
360 	err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
361 	err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
362 	err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
363 	err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
364 
365 	if (err)
366 		return 1;
367 
368 	/* Step 2a : make sure trigger sources are unique */
369 
370 	err |= comedi_check_trigger_is_unique(cmd->stop_src);
371 
372 	/* Step 2b : and mutually compatible */
373 
374 	if (err)
375 		return 2;
376 
377 	/* Step 3: check if arguments are trivially valid */
378 
379 	err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
380 
381 	if (!cmd->chanlist_len || !cmd->chanlist) {
382 		cmd->chanlist_len = 32;
383 		err |= -EINVAL;
384 	}
385 	err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
386 					   cmd->chanlist_len);
387 
388 	if (cmd->stop_src == TRIG_COUNT)
389 		err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
390 	else	/* TRIG_NONE */
391 		err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
392 
393 	if (err)
394 		return 3;
395 
396 	/* Step 4: fix up any arguments */
397 
398 	/* Step 5: check channel list if it exists */
399 
400 	if (cmd->chanlist && cmd->chanlist_len > 0)
401 		err |= gsc_hpdi_check_chanlist(dev, s, cmd);
402 
403 	if (err)
404 		return 5;
405 
406 	return 0;
407 }
408 
409 /* setup dma descriptors so a link completes every 'len' bytes */
gsc_hpdi_setup_dma_descriptors(struct comedi_device * dev,unsigned int len)410 static int gsc_hpdi_setup_dma_descriptors(struct comedi_device *dev,
411 					  unsigned int len)
412 {
413 	struct hpdi_private *devpriv = dev->private;
414 	dma_addr_t phys_addr = devpriv->dma_desc_phys_addr;
415 	u32 next_bits = PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR |
416 			PLX_DMADPR_XFERL2P;
417 	unsigned int offset = 0;
418 	unsigned int idx = 0;
419 	unsigned int i;
420 
421 	if (len > DMA_BUFFER_SIZE)
422 		len = DMA_BUFFER_SIZE;
423 	len -= len % sizeof(u32);
424 	if (len == 0)
425 		return -EINVAL;
426 
427 	for (i = 0; i < NUM_DMA_DESCRIPTORS && idx < NUM_DMA_BUFFERS; i++) {
428 		devpriv->dma_desc[i].pci_start_addr =
429 		    cpu_to_le32(devpriv->dio_buffer_phys_addr[idx] + offset);
430 		devpriv->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
431 		devpriv->dma_desc[i].transfer_size = cpu_to_le32(len);
432 		devpriv->dma_desc[i].next = cpu_to_le32((phys_addr +
433 			(i + 1) * sizeof(devpriv->dma_desc[0])) | next_bits);
434 
435 		devpriv->desc_dio_buffer[i] = devpriv->dio_buffer[idx] +
436 					      (offset / sizeof(u32));
437 
438 		offset += len;
439 		if (len + offset > DMA_BUFFER_SIZE) {
440 			offset = 0;
441 			idx++;
442 		}
443 	}
444 	devpriv->num_dma_descriptors = i;
445 	/* fix last descriptor to point back to first */
446 	devpriv->dma_desc[i - 1].next = cpu_to_le32(phys_addr | next_bits);
447 
448 	devpriv->block_size = len;
449 
450 	return len;
451 }
452 
gsc_hpdi_dio_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)453 static int gsc_hpdi_dio_insn_config(struct comedi_device *dev,
454 				    struct comedi_subdevice *s,
455 				    struct comedi_insn *insn,
456 				    unsigned int *data)
457 {
458 	int ret;
459 
460 	switch (data[0]) {
461 	case INSN_CONFIG_BLOCK_SIZE:
462 		ret = gsc_hpdi_setup_dma_descriptors(dev, data[1]);
463 		if (ret)
464 			return ret;
465 
466 		data[1] = ret;
467 		break;
468 	default:
469 		ret = comedi_dio_insn_config(dev, s, insn, data, 0xffffffff);
470 		if (ret)
471 			return ret;
472 		break;
473 	}
474 
475 	return insn->n;
476 }
477 
gsc_hpdi_free_dma(struct comedi_device * dev)478 static void gsc_hpdi_free_dma(struct comedi_device *dev)
479 {
480 	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
481 	struct hpdi_private *devpriv = dev->private;
482 	int i;
483 
484 	if (!devpriv)
485 		return;
486 
487 	/* free pci dma buffers */
488 	for (i = 0; i < NUM_DMA_BUFFERS; i++) {
489 		if (devpriv->dio_buffer[i])
490 			dma_free_coherent(&pcidev->dev,
491 					  DMA_BUFFER_SIZE,
492 					  devpriv->dio_buffer[i],
493 					  devpriv->dio_buffer_phys_addr[i]);
494 	}
495 	/* free dma descriptors */
496 	if (devpriv->dma_desc)
497 		dma_free_coherent(&pcidev->dev,
498 				  sizeof(struct plx_dma_desc) *
499 				  NUM_DMA_DESCRIPTORS,
500 				  devpriv->dma_desc,
501 				  devpriv->dma_desc_phys_addr);
502 }
503 
gsc_hpdi_init(struct comedi_device * dev)504 static int gsc_hpdi_init(struct comedi_device *dev)
505 {
506 	struct hpdi_private *devpriv = dev->private;
507 	u32 plx_intcsr_bits;
508 
509 	/* wait 10usec after reset before accessing fifos */
510 	writel(BOARD_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
511 	usleep_range(10, 1000);
512 
513 	writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
514 	       dev->mmio + RX_PROG_ALMOST_REG);
515 	writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
516 	       dev->mmio + TX_PROG_ALMOST_REG);
517 
518 	devpriv->tx_fifo_size = readl(dev->mmio + TX_FIFO_SIZE_REG) &
519 				FIFO_SIZE_MASK;
520 	devpriv->rx_fifo_size = readl(dev->mmio + RX_FIFO_SIZE_REG) &
521 				FIFO_SIZE_MASK;
522 
523 	writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
524 
525 	/* enable interrupts */
526 	plx_intcsr_bits =
527 	    PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN |
528 	    PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN |
529 	    PLX_INTCSR_DMA0IEN;
530 	writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_REG_INTCSR);
531 
532 	return 0;
533 }
534 
gsc_hpdi_init_plx9080(struct comedi_device * dev)535 static void gsc_hpdi_init_plx9080(struct comedi_device *dev)
536 {
537 	struct hpdi_private *devpriv = dev->private;
538 	u32 bits;
539 	void __iomem *plx_iobase = devpriv->plx9080_mmio;
540 
541 #ifdef __BIG_ENDIAN
542 	bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1;
543 #else
544 	bits = 0;
545 #endif
546 	writel(bits, devpriv->plx9080_mmio + PLX_REG_BIGEND);
547 
548 	writel(0, devpriv->plx9080_mmio + PLX_REG_INTCSR);
549 
550 	gsc_hpdi_abort_dma(dev, 0);
551 	gsc_hpdi_abort_dma(dev, 1);
552 
553 	/* configure dma0 mode */
554 	bits = 0;
555 	/* enable ready input */
556 	bits |= PLX_DMAMODE_READYIEN;
557 	/* enable dma chaining */
558 	bits |= PLX_DMAMODE_CHAINEN;
559 	/*
560 	 * enable interrupt on dma done
561 	 * (probably don't need this, since chain never finishes)
562 	 */
563 	bits |= PLX_DMAMODE_DONEIEN;
564 	/*
565 	 * don't increment local address during transfers
566 	 * (we are transferring from a fixed fifo register)
567 	 */
568 	bits |= PLX_DMAMODE_LACONST;
569 	/* route dma interrupt to pci bus */
570 	bits |= PLX_DMAMODE_INTRPCI;
571 	/* enable demand mode */
572 	bits |= PLX_DMAMODE_DEMAND;
573 	/* enable local burst mode */
574 	bits |= PLX_DMAMODE_BURSTEN;
575 	bits |= PLX_DMAMODE_WIDTH_32;
576 	writel(bits, plx_iobase + PLX_REG_DMAMODE0);
577 }
578 
gsc_hpdi_auto_attach(struct comedi_device * dev,unsigned long context_unused)579 static int gsc_hpdi_auto_attach(struct comedi_device *dev,
580 				unsigned long context_unused)
581 {
582 	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
583 	struct hpdi_private *devpriv;
584 	struct comedi_subdevice *s;
585 	int i;
586 	int retval;
587 
588 	dev->board_name = "pci-hpdi32";
589 
590 	devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
591 	if (!devpriv)
592 		return -ENOMEM;
593 
594 	retval = comedi_pci_enable(dev);
595 	if (retval)
596 		return retval;
597 	pci_set_master(pcidev);
598 
599 	devpriv->plx9080_mmio = pci_ioremap_bar(pcidev, 0);
600 	dev->mmio = pci_ioremap_bar(pcidev, 2);
601 	if (!devpriv->plx9080_mmio || !dev->mmio) {
602 		dev_warn(dev->class_dev, "failed to remap io memory\n");
603 		return -ENOMEM;
604 	}
605 
606 	gsc_hpdi_init_plx9080(dev);
607 
608 	/* get irq */
609 	if (request_irq(pcidev->irq, gsc_hpdi_interrupt, IRQF_SHARED,
610 			dev->board_name, dev)) {
611 		dev_warn(dev->class_dev,
612 			 "unable to allocate irq %u\n", pcidev->irq);
613 		return -EINVAL;
614 	}
615 	dev->irq = pcidev->irq;
616 
617 	dev_dbg(dev->class_dev, " irq %u\n", dev->irq);
618 
619 	/* allocate pci dma buffers */
620 	for (i = 0; i < NUM_DMA_BUFFERS; i++) {
621 		devpriv->dio_buffer[i] =
622 		    dma_alloc_coherent(&pcidev->dev, DMA_BUFFER_SIZE,
623 				       &devpriv->dio_buffer_phys_addr[i],
624 				       GFP_KERNEL);
625 		if (!devpriv->dio_buffer[i]) {
626 			dev_warn(dev->class_dev,
627 				 "failed to allocate DMA buffer\n");
628 			return -ENOMEM;
629 		}
630 	}
631 	/* allocate dma descriptors */
632 	devpriv->dma_desc = dma_alloc_coherent(&pcidev->dev,
633 					       sizeof(struct plx_dma_desc) *
634 					       NUM_DMA_DESCRIPTORS,
635 					       &devpriv->dma_desc_phys_addr,
636 					       GFP_KERNEL);
637 	if (!devpriv->dma_desc) {
638 		dev_warn(dev->class_dev,
639 			 "failed to allocate DMA descriptors\n");
640 		return -ENOMEM;
641 	}
642 	if (devpriv->dma_desc_phys_addr & 0xf) {
643 		dev_warn(dev->class_dev,
644 			 " dma descriptors not quad-word aligned (bug)\n");
645 		return -EIO;
646 	}
647 
648 	retval = gsc_hpdi_setup_dma_descriptors(dev, 0x1000);
649 	if (retval < 0)
650 		return retval;
651 
652 	retval = comedi_alloc_subdevices(dev, 1);
653 	if (retval)
654 		return retval;
655 
656 	/* Digital I/O subdevice */
657 	s = &dev->subdevices[0];
658 	dev->read_subdev = s;
659 	s->type		= COMEDI_SUBD_DIO;
660 	s->subdev_flags	= SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
661 			  SDF_CMD_READ;
662 	s->n_chan	= 32;
663 	s->len_chanlist	= 32;
664 	s->maxdata	= 1;
665 	s->range_table	= &range_digital;
666 	s->insn_config	= gsc_hpdi_dio_insn_config;
667 	s->do_cmd	= gsc_hpdi_cmd;
668 	s->do_cmdtest	= gsc_hpdi_cmd_test;
669 	s->cancel	= gsc_hpdi_cancel;
670 
671 	return gsc_hpdi_init(dev);
672 }
673 
gsc_hpdi_detach(struct comedi_device * dev)674 static void gsc_hpdi_detach(struct comedi_device *dev)
675 {
676 	struct hpdi_private *devpriv = dev->private;
677 
678 	if (dev->irq)
679 		free_irq(dev->irq, dev);
680 	if (devpriv) {
681 		if (devpriv->plx9080_mmio) {
682 			writel(0, devpriv->plx9080_mmio + PLX_REG_INTCSR);
683 			iounmap(devpriv->plx9080_mmio);
684 		}
685 		if (dev->mmio)
686 			iounmap(dev->mmio);
687 	}
688 	comedi_pci_disable(dev);
689 	gsc_hpdi_free_dma(dev);
690 }
691 
692 static struct comedi_driver gsc_hpdi_driver = {
693 	.driver_name	= "gsc_hpdi",
694 	.module		= THIS_MODULE,
695 	.auto_attach	= gsc_hpdi_auto_attach,
696 	.detach		= gsc_hpdi_detach,
697 };
698 
gsc_hpdi_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)699 static int gsc_hpdi_pci_probe(struct pci_dev *dev,
700 			      const struct pci_device_id *id)
701 {
702 	return comedi_pci_auto_config(dev, &gsc_hpdi_driver, id->driver_data);
703 }
704 
705 static const struct pci_device_id gsc_hpdi_pci_table[] = {
706 	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080,
707 			 PCI_VENDOR_ID_PLX, 0x2400) },
708 	{ 0 }
709 };
710 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
711 
712 static struct pci_driver gsc_hpdi_pci_driver = {
713 	.name		= "gsc_hpdi",
714 	.id_table	= gsc_hpdi_pci_table,
715 	.probe		= gsc_hpdi_pci_probe,
716 	.remove		= comedi_pci_auto_unconfig,
717 };
718 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
719 
720 MODULE_AUTHOR("Comedi https://www.comedi.org");
721 MODULE_DESCRIPTION("Comedi driver for General Standards PCI-HPDI32/PMC-HPDI32");
722 MODULE_LICENSE("GPL");
723