1 /*
2 * Copyright 2013-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "include/gpio_types.h"
28 #include "../hw_factory.h"
29
30
31 #include "../hw_gpio.h"
32 #include "../hw_ddc.h"
33 #include "../hw_hpd.h"
34
35 #include "hw_factory_dcn10.h"
36
37 #include "dcn/dcn_1_0_offset.h"
38 #include "dcn/dcn_1_0_sh_mask.h"
39 #include "soc15_hw_ip.h"
40 #include "vega10_ip_offset.h"
41
42 #define block HPD
43 #define reg_num 0
44
45 /* set field name */
46 #define SF_HPD(reg_name, field_name, post_fix)\
47 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
48
49 #define BASE_INNER(seg) \
50 DCE_BASE__INST0_SEG ## seg
51
52 /* compile time expand base address. */
53 #define BASE(seg) \
54 BASE_INNER(seg)
55
56 #define REG(reg_name)\
57 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
58
59 #define REGI(reg_name, block, id)\
60 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
61 mm ## block ## id ## _ ## reg_name
62
63 #include "reg_helper.h"
64 #include "../hpd_regs.h"
65
66 #define hpd_regs(id) \
67 {\
68 HPD_REG_LIST(id)\
69 }
70
71 static const struct hpd_registers hpd_regs[] = {
72 hpd_regs(0),
73 hpd_regs(1),
74 hpd_regs(2),
75 hpd_regs(3),
76 hpd_regs(4),
77 hpd_regs(5)
78 };
79
80 static const struct hpd_sh_mask hpd_shift = {
81 HPD_MASK_SH_LIST(__SHIFT)
82 };
83
84 static const struct hpd_sh_mask hpd_mask = {
85 HPD_MASK_SH_LIST(_MASK)
86 };
87
88 #include "../ddc_regs.h"
89
90 /* set field name */
91 #define SF_DDC(reg_name, field_name, post_fix)\
92 .field_name = reg_name ## __ ## field_name ## post_fix
93
94 static const struct ddc_registers ddc_data_regs[] = {
95 ddc_data_regs(1),
96 ddc_data_regs(2),
97 ddc_data_regs(3),
98 ddc_data_regs(4),
99 ddc_data_regs(5),
100 ddc_data_regs(6),
101 ddc_vga_data_regs,
102 ddc_i2c_data_regs
103 };
104
105 static const struct ddc_registers ddc_clk_regs[] = {
106 ddc_clk_regs(1),
107 ddc_clk_regs(2),
108 ddc_clk_regs(3),
109 ddc_clk_regs(4),
110 ddc_clk_regs(5),
111 ddc_clk_regs(6),
112 ddc_vga_clk_regs,
113 ddc_i2c_clk_regs
114 };
115
116 static const struct ddc_sh_mask ddc_shift = {
117 DDC_MASK_SH_LIST(__SHIFT)
118 };
119
120 static const struct ddc_sh_mask ddc_mask = {
121 DDC_MASK_SH_LIST(_MASK)
122 };
123
define_ddc_registers(struct hw_gpio_pin * pin,uint32_t en)124 static void define_ddc_registers(
125 struct hw_gpio_pin *pin,
126 uint32_t en)
127 {
128 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
129
130 switch (pin->id) {
131 case GPIO_ID_DDC_DATA:
132 ddc->regs = &ddc_data_regs[en];
133 ddc->base.regs = &ddc_data_regs[en].gpio;
134 break;
135 case GPIO_ID_DDC_CLOCK:
136 ddc->regs = &ddc_clk_regs[en];
137 ddc->base.regs = &ddc_clk_regs[en].gpio;
138 break;
139 default:
140 ASSERT_CRITICAL(false);
141 return;
142 }
143
144 ddc->shifts = &ddc_shift;
145 ddc->masks = &ddc_mask;
146
147 }
148
define_hpd_registers(struct hw_gpio_pin * pin,uint32_t en)149 static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
150 {
151 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
152
153 hpd->regs = &hpd_regs[en];
154 hpd->shifts = &hpd_shift;
155 hpd->masks = &hpd_mask;
156 hpd->base.regs = &hpd_regs[en].gpio;
157 }
158
159
160 /* fucntion table */
161 static const struct hw_factory_funcs funcs = {
162 .create_ddc_data = dal_hw_ddc_create,
163 .create_ddc_clock = dal_hw_ddc_create,
164 .create_generic = NULL,
165 .create_hpd = dal_hw_hpd_create,
166 .create_sync = NULL,
167 .create_gsl = NULL,
168 .define_hpd_registers = define_hpd_registers,
169 .define_ddc_registers = define_ddc_registers
170 };
171 /*
172 * dal_hw_factory_dcn10_init
173 *
174 * @brief
175 * Initialize HW factory function pointers and pin info
176 *
177 * @param
178 * struct hw_factory *factory - [out] struct of function pointers
179 */
dal_hw_factory_dcn10_init(struct hw_factory * factory)180 void dal_hw_factory_dcn10_init(struct hw_factory *factory)
181 {
182 /*TODO check ASIC CAPs*/
183 factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
184 factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
185 factory->number_of_pins[GPIO_ID_GENERIC] = 7;
186 factory->number_of_pins[GPIO_ID_HPD] = 6;
187 factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
188 factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
189 factory->number_of_pins[GPIO_ID_SYNC] = 2;
190 factory->number_of_pins[GPIO_ID_GSL] = 4;
191
192 factory->funcs = &funcs;
193 }
194