xref: /dragonfly/sys/dev/netif/txp/if_txpreg.h (revision 86d7f5d3)
1 /*	$OpenBSD: if_txpreg.h,v 1.30 2001/06/23 04:18:02 jason Exp $ */
2 /*	$FreeBSD: src/sys/dev/txp/if_txpreg.h,v 1.2.2.1 2001/07/30 17:31:39 wpaul Exp $ */
3 /*	$DragonFly: src/sys/dev/netif/txp/if_txpreg.h,v 1.6 2006/08/01 18:10:40 swildner Exp $ */
4 
5 /*
6  * Copyright (c) 2001 Aaron Campbell <aaron@monkey.org>.
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *      This product includes software developed by Aaron Campbell.
20  * 4. The name of the author may not be used to endorse or promote products
21  *    derived from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26  * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29  * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
31  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33  * THE POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #define	TXP_PCI_LOMEM			0x14	/* pci conf, memory map BAR */
37 #define	TXP_PCI_LOIO			0x10	/* pci conf, IO map BAR */
38 #define TXP_PCI_INTLINE			0x3C
39 
40 /*
41  * Typhoon registers.
42  */
43 #define	TXP_SRR				0x00	/* soft reset register */
44 #define	TXP_ISR				0x04	/* interrupt status register */
45 #define	TXP_IER				0x08	/* interrupt enable register */
46 #define	TXP_IMR				0x0c	/* interrupt mask register */
47 #define	TXP_SIR				0x10	/* self interrupt register */
48 #define	TXP_H2A_7			0x14	/* host->arm comm 7 */
49 #define	TXP_H2A_6			0x18	/* host->arm comm 6 */
50 #define	TXP_H2A_5			0x1c	/* host->arm comm 5 */
51 #define	TXP_H2A_4			0x20	/* host->arm comm 4 */
52 #define	TXP_H2A_3			0x24	/* host->arm comm 3 */
53 #define	TXP_H2A_2			0x28	/* host->arm comm 2 */
54 #define	TXP_H2A_1			0x2c	/* host->arm comm 1 */
55 #define	TXP_H2A_0			0x30	/* host->arm comm 0 */
56 #define	TXP_A2H_3			0x34	/* arm->host comm 3 */
57 #define	TXP_A2H_2			0x38	/* arm->host comm 2 */
58 #define	TXP_A2H_1			0x3c	/* arm->host comm 1 */
59 #define	TXP_A2H_0			0x40	/* arm->host comm 0 */
60 
61 /*
62  * interrupt bits (IMR, ISR, IER)
63  */
64 #define	TXP_INT_RESERVED	0xffff0000
65 #define	TXP_INT_A2H_7		0x00008000	/* arm->host comm 7 */
66 #define	TXP_INT_A2H_6		0x00004000	/* arm->host comm 6 */
67 #define	TXP_INT_A2H_5		0x00002000	/* arm->host comm 5 */
68 #define	TXP_INT_A2H_4		0x00001000	/* arm->host comm 4 */
69 #define	TXP_INT_SELF		0x00000800	/* self interrupt */
70 #define	TXP_INT_PCI_TABORT	0x00000400	/* pci target abort */
71 #define	TXP_INT_PCI_MABORT	0x00000200	/* pci master abort */
72 #define	TXP_INT_DMA3		0x00000100	/* dma3 done */
73 #define	TXP_INT_DMA2		0x00000080	/* dma2 done */
74 #define	TXP_INT_DMA1		0x00000040	/* dma1 done */
75 #define	TXP_INT_DMA0		0x00000020	/* dma0 done */
76 #define	TXP_INT_A2H_3		0x00000010	/* arm->host comm 3 */
77 #define	TXP_INT_A2H_2		0x00000008	/* arm->host comm 2 */
78 #define	TXP_INT_A2H_1		0x00000004	/* arm->host comm 1 */
79 #define	TXP_INT_A2H_0		0x00000002	/* arm->host comm 0 */
80 #define	TXP_INT_LATCH		0x00000001	/* interrupt latch */
81 
82 /*
83  * soft reset register (SRR)
84  */
85 #define	TXP_SRR_ALL		0x0000007f	/* full reset */
86 
87 /*
88  * Typhoon boot commands.
89  */
90 #define	TXP_BOOTCMD_NULL			0x00
91 #define	TXP_BOOTCMD_DOWNLOAD_COMPLETE		0xfb
92 #define	TXP_BOOTCMD_SEGMENT_AVAILABLE		0xfc
93 #define	TXP_BOOTCMD_RUNTIME_IMAGE		0xfd
94 #define	TXP_BOOTCMD_REGISTER_BOOT_RECORD	0xff
95 
96 /*
97  * Typhoon runtime commands.
98  */
99 #define	TXP_CMD_GLOBAL_RESET			0x00
100 #define	TXP_CMD_TX_ENABLE			0x01
101 #define	TXP_CMD_TX_DISABLE			0x02
102 #define	TXP_CMD_RX_ENABLE			0x03
103 #define	TXP_CMD_RX_DISABLE			0x04
104 #define	TXP_CMD_RX_FILTER_WRITE			0x05
105 #define	TXP_CMD_RX_FILTER_READ			0x06
106 #define	TXP_CMD_READ_STATISTICS			0x07
107 #define	TXP_CMD_CYCLE_STATISTICS		0x08
108 #define	TXP_CMD_CLEAR_STATISTICS		0x09
109 #define	TXP_CMD_MEMORY_READ			0x0a
110 #define	TXP_CMD_MEMORY_WRITE_SINGLE		0x0b
111 #define	TXP_CMD_VARIABLE_SECTION_READ		0x0c
112 #define	TXP_CMD_VARIABLE_SECTION_WRITE		0x0d
113 #define	TXP_CMD_STATIC_SECTION_READ		0x0e
114 #define	TXP_CMD_STATIC_SECTION_WRITE		0x0f
115 #define	TXP_CMD_IMAGE_SECTION_PROGRAM		0x10
116 #define	TXP_CMD_NVRAM_PAGE_READ			0x11
117 #define	TXP_CMD_NVRAM_PAGE_WRITE		0x12
118 #define	TXP_CMD_XCVR_SELECT			0x13
119 #define	TXP_CMD_TEST_MUX			0x14
120 #define	TXP_CMD_PHYLOOPBACK_ENABLE		0x15
121 #define	TXP_CMD_PHYLOOPBACK_DISABLE		0x16
122 #define	TXP_CMD_MAC_CONTROL_READ		0x17
123 #define	TXP_CMD_MAC_CONTROL_WRITE		0x18
124 #define	TXP_CMD_MAX_PKT_SIZE_READ		0x19
125 #define	TXP_CMD_MAX_PKT_SIZE_WRITE		0x1a
126 #define	TXP_CMD_MEDIA_STATUS_READ		0x1b
127 #define	TXP_CMD_MEDIA_STATUS_WRITE		0x1c
128 #define	TXP_CMD_NETWORK_DIAGS_READ		0x1d
129 #define	TXP_CMD_NETWORK_DIAGS_WRITE		0x1e
130 #define	TXP_CMD_PHY_MGMT_READ			0x1f
131 #define	TXP_CMD_PHY_MGMT_WRITE			0x20
132 #define	TXP_CMD_VARIABLE_PARAMETER_READ		0x21
133 #define	TXP_CMD_VARIABLE_PARAMETER_WRITE	0x22
134 #define	TXP_CMD_GOTO_SLEEP			0x23
135 #define	TXP_CMD_FIREWALL_CONTROL		0x24
136 #define	TXP_CMD_MCAST_HASH_MASK_WRITE		0x25
137 #define	TXP_CMD_STATION_ADDRESS_WRITE		0x26
138 #define	TXP_CMD_STATION_ADDRESS_READ		0x27
139 #define	TXP_CMD_STATION_MASK_WRITE		0x28
140 #define	TXP_CMD_STATION_MASK_READ		0x29
141 #define	TXP_CMD_VLAN_ETHER_TYPE_READ		0x2a
142 #define	TXP_CMD_VLAN_ETHER_TYPE_WRITE		0x2b
143 #define	TXP_CMD_VLAN_MASK_READ			0x2c
144 #define	TXP_CMD_VLAN_MASK_WRITE			0x2d
145 #define	TXP_CMD_BCAST_THROTTLE_WRITE		0x2e
146 #define	TXP_CMD_BCAST_THROTTLE_READ		0x2f
147 #define	TXP_CMD_DHCP_PREVENT_WRITE		0x30
148 #define	TXP_CMD_DHCP_PREVENT_READ		0x31
149 #define	TXP_CMD_RECV_BUFFER_CONTROL		0x32
150 #define	TXP_CMD_SOFTWARE_RESET			0x33
151 #define	TXP_CMD_CREATE_SA			0x34
152 #define	TXP_CMD_DELETE_SA			0x35
153 #define	TXP_CMD_ENABLE_RX_IP_OPTION		0x36
154 #define	TXP_CMD_RANDOM_NUMBER_CONTROL		0x37
155 #define	TXP_CMD_RANDOM_NUMBER_READ		0x38
156 #define	TXP_CMD_MATRIX_TABLE_MODE_WRITE		0x39
157 #define	TXP_CMD_MATRIX_DETAIL_READ		0x3a
158 #define	TXP_CMD_FILTER_ARRAY_READ		0x3b
159 #define	TXP_CMD_FILTER_DETAIL_READ		0x3c
160 #define	TXP_CMD_FILTER_TABLE_MODE_WRITE		0x3d
161 #define	TXP_CMD_FILTER_TCL_WRITE		0x3e
162 #define	TXP_CMD_FILTER_TBL_READ			0x3f
163 #define	TXP_CMD_FILTER_DEFINE			0x45
164 #define	TXP_CMD_ADD_WAKEUP_PKT			0x46
165 #define	TXP_CMD_ADD_SLEEP_PKT			0x47
166 #define	TXP_CMD_ENABLE_SLEEP_EVENTS		0x48
167 #define	TXP_CMD_ENABLE_WAKEUP_EVENTS		0x49
168 #define	TXP_CMD_GET_IP_ADDRESS			0x4a
169 #define	TXP_CMD_READ_PCI_REG			0x4c
170 #define	TXP_CMD_WRITE_PCI_REG			0x4d
171 #define	TXP_CMD_OFFLOAD_READ			0x4e
172 #define	TXP_CMD_OFFLOAD_WRITE			0x4f
173 #define	TXP_CMD_HELLO_RESPONSE			0x57
174 #define	TXP_CMD_ENABLE_RX_FILTER		0x58
175 #define	TXP_CMD_RX_FILTER_CAPABILITY		0x59
176 #define	TXP_CMD_HALT				0x5d
177 #define	TXP_CMD_READ_IPSEC_INFO			0x54
178 #define	TXP_CMD_GET_IPSEC_ENABLE		0x67
179 #define	TXP_CMD_INVALID				0xffff
180 
181 #define	TXP_FRAGMENT		0x0000
182 #define	TXP_TXFRAME		0x0001
183 #define	TXP_COMMAND		0x0002
184 #define	TXP_OPTION		0x0003
185 #define	TXP_RECEIVE		0x0004
186 #define	TXP_RESPONSE		0x0005
187 
188 #define	TXP_TYPE_IPSEC		0x0000
189 #define	TXP_TYPE_TCPSEGMENT	0x0001
190 
191 #define	TXP_PFLAG_NOCRC		0x0000
192 #define	TXP_PFLAG_IPCKSUM	0x0001
193 #define	TXP_PFLAG_TCPCKSUM	0x0002
194 #define	TXP_PFLAG_TCPSEGMENT	0x0004
195 #define	TXP_PFLAG_INSERTVLAN	0x0008
196 #define	TXP_PFLAG_IPSEC		0x0010
197 #define	TXP_PFLAG_PRIORITY	0x0020
198 #define	TXP_PFLAG_UDPCKSUM	0x0040
199 #define	TXP_PFLAG_PADFRAME	0x0080
200 
201 #define	TXP_MISC_FIRSTDESC	0x0000
202 #define	TXP_MISC_LASTDESC	0x0001
203 
204 #define	TXP_ERR_INTERNAL	0x0000
205 #define	TXP_ERR_FIFOUNDERRUN	0x0001
206 #define	TXP_ERR_BADSSD		0x0002
207 #define	TXP_ERR_RUNT		0x0003
208 #define	TXP_ERR_CRC		0x0004
209 #define	TXP_ERR_OVERSIZE	0x0005
210 #define	TXP_ERR_ALIGNMENT	0x0006
211 #define	TXP_ERR_DRIBBLEBIT	0x0007
212 
213 #define	TXP_PROTO_UNKNOWN	0x0000
214 #define	TXP_PROTO_IP		0x0001
215 #define	TXP_PROTO_IPX		0x0002
216 #define	TXP_PROTO_RESERVED	0x0003
217 
218 #define	TXP_STAT_PROTO		0x0001
219 #define	TXP_STAT_VLAN		0x0002
220 #define	TXP_STAT_IPFRAGMENT	0x0004
221 #define	TXP_STAT_IPSEC		0x0008
222 #define	TXP_STAT_IPCKSUMBAD	0x0010
223 #define	TXP_STAT_TCPCKSUMBAD	0x0020
224 #define	TXP_STAT_UDPCKSUMBAD	0x0040
225 #define	TXP_STAT_IPCKSUMGOOD	0x0080
226 #define	TXP_STAT_TCPCKSUMGOOD	0x0100
227 #define	TXP_STAT_UDPCKSUMGOOD	0x0200
228 
229 struct txp_tx_desc {
230 	volatile u_int8_t	tx_flags;	/* type/descriptor flags */
231 	volatile u_int8_t	tx_numdesc;	/* number of descriptors */
232 	volatile u_int16_t	tx_totlen;	/* total packet length */
233 	volatile u_int32_t	tx_addrlo;	/* virt addr low word */
234 	volatile u_int32_t	tx_addrhi;	/* virt addr high word */
235 	volatile u_int32_t	tx_pflags;	/* processing flags */
236 };
237 #define	TX_FLAGS_TYPE_M		0x07		/* type mask */
238 #define	TX_FLAGS_TYPE_FRAG	0x00		/* type: fragment */
239 #define	TX_FLAGS_TYPE_DATA	0x01		/* type: data frame */
240 #define	TX_FLAGS_TYPE_CMD	0x02		/* type: command frame */
241 #define	TX_FLAGS_TYPE_OPT	0x03		/* type: options */
242 #define	TX_FLAGS_TYPE_RX	0x04		/* type: command */
243 #define	TX_FLAGS_TYPE_RESP	0x05		/* type: response */
244 #define	TX_FLAGS_RESP		0x40		/* response requested */
245 #define	TX_FLAGS_VALID		0x80		/* valid descriptor */
246 
247 #define	TX_PFLAGS_DNAC		0x00000001	/* do not add crc */
248 #define	TX_PFLAGS_IPCKSUM	0x00000002	/* ip checksum */
249 #define	TX_PFLAGS_TCPCKSUM	0x00000004	/* tcp checksum */
250 #define	TX_PFLAGS_TCPSEG	0x00000008	/* tcp segmentation */
251 #define	TX_PFLAGS_VLAN		0x00000010	/* insert vlan */
252 #define	TX_PFLAGS_IPSEC		0x00000020	/* perform ipsec */
253 #define	TX_PFLAGS_PRIO		0x00000040	/* priority field valid */
254 #define	TX_PFLAGS_UDPCKSUM	0x00000080	/* udp checksum */
255 #define	TX_PFLAGS_PADFRAME	0x00000100	/* pad frame */
256 #define	TX_PFLAGS_VLANTAG_M	0x0ffff000	/* vlan tag mask */
257 #define	TX_PFLAGS_VLANPRI_M	0x00700000	/* vlan priority mask */
258 #define	TX_PFLAGS_VLANTAG_S	12		/* amount to shift tag */
259 
260 struct txp_rx_desc {
261 	volatile u_int8_t	rx_flags;	/* type/descriptor flags */
262 	volatile u_int8_t	rx_numdesc;	/* number of descriptors */
263 	volatile u_int16_t	rx_len;		/* frame length */
264 #ifdef notdef
265 	volatile u_int32_t	rx_vaddrlo;	/* virtual address, lo word */
266 	volatile u_int32_t	rx_vaddrhi;	/* virtual address, hi word */
267 #endif
268 	union {
269 		struct txp_swdesc	*rx_sd;
270 		u_int64_t		rx_dummy;
271 	} txp_rx_u;
272 	volatile u_int32_t	rx_stat;	/* status */
273 	volatile u_int16_t	rx_filter;	/* filter status */
274 	volatile u_int16_t	rx_hash;	/* hash status */
275 	volatile u_int32_t	rx_vlan;	/* vlan tag/priority */
276 };
277 
278 #define rx_sd	txp_rx_u.rx_sd
279 
280 /* txp_rx_desc.rx_flags */
281 #define	RX_FLAGS_TYPE_M		0x07		/* type mask */
282 #define	RX_FLAGS_TYPE_FRAG	0x00		/* type: fragment */
283 #define	RX_FLAGS_TYPE_DATA	0x01		/* type: data frame */
284 #define	RX_FLAGS_TYPE_CMD	0x02		/* type: command frame */
285 #define	RX_FLAGS_TYPE_OPT	0x03		/* type: options */
286 #define	RX_FLAGS_TYPE_RX	0x04		/* type: command */
287 #define	RX_FLAGS_TYPE_RESP	0x05		/* type: response */
288 #define	RX_FLAGS_RCV_TYPE_M	0x18		/* rcvtype mask */
289 #define	RX_FLAGS_RCV_TYPE_RX	0x00		/* rcvtype: receive */
290 #define	RX_FLAGS_RCV_TYPE_RSP	0x08		/* rcvtype: response */
291 #define	RX_FLAGS_ERROR		0x40		/* error in packet */
292 
293 /* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR bit set) */
294 #define	RX_ERROR_ADAPTER	0x00000000	/* adapter internal error */
295 #define	RX_ERROR_FIFO		0x00000001	/* fifo underrun */
296 #define	RX_ERROR_BADSSD		0x00000002	/* bad ssd */
297 #define	RX_ERROR_RUNT		0x00000003	/* runt packet */
298 #define	RX_ERROR_CRC		0x00000004	/* bad crc */
299 #define	RX_ERROR_OVERSIZE	0x00000005	/* oversized packet */
300 #define	RX_ERROR_ALIGN		0x00000006	/* alignment error */
301 #define	RX_ERROR_DRIBBLE	0x00000007	/* dribble bit */
302 
303 /* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR not bit set) */
304 #define	RX_STAT_PROTO_M		0x00000003	/* protocol mask */
305 #define	RX_STAT_PROTO_UK	0x00000000	/* unknown protocol */
306 #define	RX_STAT_PROTO_IPX	0x00000001	/* IPX */
307 #define	RX_STAT_PROTO_IP	0x00000002	/* IP */
308 #define	RX_STAT_PROTO_RSV	0x00000003	/* reserved */
309 #define	RX_STAT_VLAN		0x00000004	/* vlan tag (in rxd) */
310 #define	RX_STAT_IPFRAG		0x00000008	/* fragment, ipsec not done */
311 #define	RX_STAT_IPSEC		0x00000010	/* ipsec decoded packet */
312 #define	RX_STAT_IPCKSUMBAD	0x00000020	/* ip checksum failed */
313 #define	RX_STAT_UDPCKSUMBAD	0x00000040	/* udp checksum failed */
314 #define	RX_STAT_TCPCKSUMBAD	0x00000080	/* tcp checksum failed */
315 #define	RX_STAT_IPCKSUMGOOD	0x00000100	/* ip checksum succeeded */
316 #define	RX_STAT_UDPCKSUMGOOD	0x00000200	/* udp checksum succeeded */
317 #define	RX_STAT_TCPCKSUMGOOD	0x00000400	/* tcp checksum succeeded */
318 
319 
320 struct txp_rxbuf_desc {
321 	volatile u_int32_t	rb_paddrlo;
322 	volatile u_int32_t	rb_paddrhi;
323 #ifdef notdef
324 	volatile u_int32_t	rb_vaddrlo;
325 	volatile u_int32_t	rb_vaddrhi;
326 #endif
327 	union {
328 		struct txp_swdesc	*rb_sd;
329 		u_int64_t		rb_dummy;
330 	} txp_rb_u;
331 };
332 
333 #define rb_sd	txp_rb_u.rb_sd
334 
335 /* Extension descriptor */
336 struct txp_ext_desc {
337 	volatile u_int32_t	ext_1;
338 	volatile u_int32_t	ext_2;
339 	volatile u_int32_t	ext_3;
340 	volatile u_int32_t	ext_4;
341 };
342 
343 struct txp_cmd_desc {
344 	volatile u_int8_t	cmd_flags;
345 	volatile u_int8_t	cmd_numdesc;
346 	volatile u_int16_t	cmd_id;
347 	volatile u_int16_t	cmd_seq;
348 	volatile u_int16_t	cmd_par1;
349 	volatile u_int32_t	cmd_par2;
350 	volatile u_int32_t	cmd_par3;
351 };
352 #define	CMD_FLAGS_TYPE_M	0x07		/* type mask */
353 #define	CMD_FLAGS_TYPE_FRAG	0x00		/* type: fragment */
354 #define	CMD_FLAGS_TYPE_DATA	0x01		/* type: data frame */
355 #define	CMD_FLAGS_TYPE_CMD	0x02		/* type: command frame */
356 #define	CMD_FLAGS_TYPE_OPT	0x03		/* type: options */
357 #define	CMD_FLAGS_TYPE_RX	0x04		/* type: command */
358 #define	CMD_FLAGS_TYPE_RESP	0x05		/* type: response */
359 #define	CMD_FLAGS_RESP		0x40		/* response requested */
360 #define	CMD_FLAGS_VALID		0x80		/* valid descriptor */
361 
362 struct txp_rsp_desc {
363 	volatile u_int8_t	rsp_flags;
364 	volatile u_int8_t	rsp_numdesc;
365 	volatile u_int16_t	rsp_id;
366 	volatile u_int16_t	rsp_seq;
367 	volatile u_int16_t	rsp_par1;
368 	volatile u_int32_t	rsp_par2;
369 	volatile u_int32_t	rsp_par3;
370 };
371 #define	RSP_FLAGS_TYPE_M	0x07		/* type mask */
372 #define	RSP_FLAGS_TYPE_FRAG	0x00		/* type: fragment */
373 #define	RSP_FLAGS_TYPE_DATA	0x01		/* type: data frame */
374 #define	RSP_FLAGS_TYPE_CMD	0x02		/* type: command frame */
375 #define	RSP_FLAGS_TYPE_OPT	0x03		/* type: options */
376 #define	RSP_FLAGS_TYPE_RX	0x04		/* type: command */
377 #define	RSP_FLAGS_TYPE_RESP	0x05		/* type: response */
378 #define	RSP_FLAGS_ERROR		0x40		/* response error */
379 
380 struct txp_frag_desc {
381 	volatile u_int8_t	frag_flags;	/* type/descriptor flags */
382 	volatile u_int8_t	frag_rsvd1;
383 	volatile u_int16_t	frag_len;	/* bytes in this fragment */
384 	volatile u_int32_t	frag_addrlo;	/* phys addr low word */
385 	volatile u_int32_t	frag_addrhi;	/* phys addr high word */
386 	volatile u_int32_t	frag_rsvd2;
387 };
388 #define	FRAG_FLAGS_TYPE_M	0x07		/* type mask */
389 #define	FRAG_FLAGS_TYPE_FRAG	0x00		/* type: fragment */
390 #define	FRAG_FLAGS_TYPE_DATA	0x01		/* type: data frame */
391 #define	FRAG_FLAGS_TYPE_CMD	0x02		/* type: command frame */
392 #define	FRAG_FLAGS_TYPE_OPT	0x03		/* type: options */
393 #define	FRAG_FLAGS_TYPE_RX	0x04		/* type: command */
394 #define	FRAG_FLAGS_TYPE_RESP	0x05		/* type: response */
395 
396 struct txp_opt_desc {
397 	u_int8_t		opt_desctype:3,
398 				opt_rsvd:1,
399 				opt_type:4;
400 
401 	u_int8_t		opt_num;
402 	u_int16_t		opt_dep1;
403 	u_int32_t		opt_dep2;
404 	u_int32_t		opt_dep3;
405 	u_int32_t		opt_dep4;
406 };
407 
408 struct txp_ipsec_desc {
409 	u_int8_t		ipsec_desctpe:3,
410 				ipsec_rsvd:1,
411 				ipsec_type:4;
412 
413 	u_int8_t		ipsec_num;
414 	u_int16_t		ipsec_flags;
415 	u_int16_t		ipsec_ah1;
416 	u_int16_t		ipsec_esp1;
417 	u_int16_t		ipsec_ah2;
418 	u_int16_t		ipsec_esp2;
419 	u_int32_t		ipsec_rsvd1;
420 };
421 
422 struct txp_tcpseg_desc {
423 	u_int8_t		tcpseg_desctype:3,
424 				tcpseg_rsvd:1,
425 				tcpseg_type:4;
426 
427 	u_int8_t		tcpseg_num;
428 
429 	u_int16_t		tcpseg_mss:12,
430 				tcpseg_misc:4;
431 
432 	u_int32_t		tcpseg_respaddr;
433 	u_int32_t		tcpseg_txbytes;
434 	u_int32_t		tcpseg_lss;
435 };
436 
437 /*
438  * Transceiver types
439  */
440 #define	TXP_XCVR_10_HDX		0
441 #define	TXP_XCVR_10_FDX		1
442 #define	TXP_XCVR_100_HDX	2
443 #define	TXP_XCVR_100_FDX	3
444 #define	TXP_XCVR_AUTO		4
445 
446 #define TXP_MEDIA_CRC		0x0004	/* crc strip disable */
447 #define	TXP_MEDIA_CD		0x0010	/* collision detection */
448 #define	TXP_MEDIA_CS		0x0020	/* carrier sense */
449 #define	TXP_MEDIA_POL		0x0400	/* polarity reversed */
450 #define	TXP_MEDIA_NOLINK	0x0800	/* 0 = link, 1 = no link */
451 
452 /*
453  * receive filter bits (par1 to TXP_CMD_RX_FILTER_{READ|WRITE}
454  */
455 #define	TXP_RXFILT_DIRECT	0x0001	/* directed packets */
456 #define	TXP_RXFILT_ALLMULTI	0x0002	/* all multicast packets */
457 #define	TXP_RXFILT_BROADCAST	0x0004	/* broadcast packets */
458 #define	TXP_RXFILT_PROMISC	0x0008	/* promiscuous mode */
459 #define	TXP_RXFILT_HASHMULTI	0x0010	/* use multicast filter */
460 
461 /*
462  * boot record (pointers to rings)
463  */
464 struct txp_boot_record {
465 	volatile u_int32_t	br_hostvar_lo;		/* host ring pointer */
466 	volatile u_int32_t	br_hostvar_hi;
467 	volatile u_int32_t	br_txlopri_lo;		/* tx low pri ring */
468 	volatile u_int32_t	br_txlopri_hi;
469 	volatile u_int32_t	br_txlopri_siz;
470 	volatile u_int32_t	br_txhipri_lo;		/* tx high pri ring */
471 	volatile u_int32_t	br_txhipri_hi;
472 	volatile u_int32_t	br_txhipri_siz;
473 	volatile u_int32_t	br_rxlopri_lo;		/* rx low pri ring */
474 	volatile u_int32_t	br_rxlopri_hi;
475 	volatile u_int32_t	br_rxlopri_siz;
476 	volatile u_int32_t	br_rxbuf_lo;		/* rx buffer ring */
477 	volatile u_int32_t	br_rxbuf_hi;
478 	volatile u_int32_t	br_rxbuf_siz;
479 	volatile u_int32_t	br_cmd_lo;		/* command ring */
480 	volatile u_int32_t	br_cmd_hi;
481 	volatile u_int32_t	br_cmd_siz;
482 	volatile u_int32_t	br_resp_lo;		/* response ring */
483 	volatile u_int32_t	br_resp_hi;
484 	volatile u_int32_t	br_resp_siz;
485 	volatile u_int32_t	br_zero_lo;		/* zero word */
486 	volatile u_int32_t	br_zero_hi;
487 	volatile u_int32_t	br_rxhipri_lo;		/* rx high pri ring */
488 	volatile u_int32_t	br_rxhipri_hi;
489 	volatile u_int32_t	br_rxhipri_siz;
490 };
491 
492 /*
493  * hostvar structure (shared with typhoon)
494  */
495 struct txp_hostvar {
496 	volatile u_int32_t	hv_rx_hi_read_idx;	/* host->arm */
497 	volatile u_int32_t	hv_rx_lo_read_idx;	/* host->arm */
498 	volatile u_int32_t	hv_rx_buf_write_idx;	/* host->arm */
499 	volatile u_int32_t	hv_resp_read_idx;	/* host->arm */
500 	volatile u_int32_t	hv_tx_lo_desc_read_idx;	/* arm->host */
501 	volatile u_int32_t	hv_tx_hi_desc_read_idx;	/* arm->host */
502 	volatile u_int32_t	hv_rx_lo_write_idx;	/* arm->host */
503 	volatile u_int32_t	hv_rx_buf_read_idx;	/* arm->host */
504 	volatile u_int32_t	hv_cmd_read_idx;	/* arm->host */
505 	volatile u_int32_t	hv_resp_write_idx;	/* arm->host */
506 	volatile u_int32_t	hv_rx_hi_write_idx;	/* arm->host */
507 };
508 
509 /*
510  * TYPHOON status register state (in TXP_A2H_0)
511  */
512 #define	STAT_ROM_CODE			0x00000001
513 #define	STAT_ROM_EEPROM_LOAD		0x00000002
514 #define	STAT_WAITING_FOR_BOOT		0x00000007
515 #define	STAT_RUNNING			0x00000009
516 #define	STAT_WAITING_FOR_HOST_REQUEST	0x0000000d
517 #define	STAT_WAITING_FOR_SEGMENT	0x00000010
518 #define	STAT_SLEEPING			0x00000011
519 #define	STAT_HALTED			0x00000014
520 
521 #define	TX_ENTRIES			256
522 #define	RX_ENTRIES			128
523 #define	RXBUF_ENTRIES			256
524 #define	CMD_ENTRIES			32
525 #define	RSP_ENTRIES			32
526 
527 #define	OFFLOAD_TCPCKSUM		0x00000002	/* tcp checksum */
528 #define	OFFLOAD_UDPCKSUM		0x00000004	/* udp checksum */
529 #define	OFFLOAD_IPCKSUM			0x00000008	/* ip checksum */
530 #define	OFFLOAD_IPSEC			0x00000010	/* ipsec enable */
531 #define	OFFLOAD_BCAST			0x00000020	/* broadcast throttle */
532 #define	OFFLOAD_DHCP			0x00000040	/* dhcp prevention */
533 #define	OFFLOAD_VLAN			0x00000080	/* vlan enable */
534 #define	OFFLOAD_FILTER			0x00000100	/* filter enable */
535 #define	OFFLOAD_TCPSEG			0x00000200	/* tcp segmentation */
536 #define	OFFLOAD_MASK			0xfffffffe	/* mask off low bit */
537 
538 /*
539  * Macros for converting array indices to offsets within the descriptor
540  * arrays.  The chip operates on offsets, but it's much easier for us
541  * to operate on indices.  Assumes descriptor entries are 16 bytes.
542  */
543 #define	TXP_IDX2OFFSET(idx)	((idx) << 4)
544 #define	TXP_OFFSET2IDX(off)	((off) >> 4)
545 
546 struct txp_cmd_ring {
547 	struct txp_cmd_desc	*base;
548 	u_int32_t		lastwrite;
549 	u_int32_t		size;
550 };
551 
552 struct txp_rsp_ring {
553 	struct txp_rsp_desc	*base;
554 	u_int32_t		lastwrite;
555 	u_int32_t		size;
556 };
557 
558 struct txp_tx_ring {
559 	struct txp_tx_desc	*r_desc;	/* base address of descs */
560 	u_int32_t		r_reg;		/* register to activate */
561 	u_int32_t		r_prod;		/* producer */
562 	u_int32_t		r_cons;		/* consumer */
563 	u_int32_t		r_cnt;		/* # descs in use */
564 	volatile u_int32_t	*r_off;		/* hostvar index pointer */
565 };
566 
567 struct txp_swdesc {
568 	struct mbuf *		sd_mbuf;
569 	bus_dmamap_t		sd_map;
570 };
571 
572 struct txp_rx_ring {
573 	struct txp_rx_desc	*r_desc;	/* base address of descs */
574 	volatile u_int32_t	*r_roff;	/* hv read offset ptr */
575 	volatile u_int32_t	*r_woff;	/* hv write offset ptr */
576 };
577 
578 struct txp_ldata {
579 	struct txp_boot_record	txp_boot;
580 	struct txp_hostvar	txp_hostvar;
581 	struct txp_tx_desc	txp_txhiring[TX_ENTRIES];
582 	struct txp_tx_desc	txp_txloring[TX_ENTRIES];
583 	struct txp_rxbuf_desc	txp_rxbufs[RXBUF_ENTRIES];
584 	struct txp_rx_desc	txp_rxhiring[RX_ENTRIES];
585 	struct txp_rx_desc	txp_rxloring[RX_ENTRIES];
586 	struct txp_cmd_desc	txp_cmdring[CMD_ENTRIES];
587 	struct txp_rsp_desc	txp_rspring[RSP_ENTRIES];
588 	u_int32_t		txp_zero;
589 };
590 
591 struct txp_softc {
592 	struct arpcom		sc_arpcom;	/* ethernet common */
593 	struct txp_hostvar	*sc_hostvar;
594 	struct txp_boot_record	*sc_boot;
595 	bus_space_handle_t	sc_bh;		/* bus handle (regs) */
596 	bus_space_tag_t		sc_bt;		/* bus tag (regs) */
597 	struct resource		*sc_res;
598 	struct resource		*sc_irq;
599 	void			*sc_intrhand;
600 	struct txp_ldata	*sc_ldata;
601 	void			*sc_fwbuf;
602 	int			sc_rxbufprod;
603 	struct txp_cmd_ring	sc_cmdring;
604 	struct txp_rsp_ring	sc_rspring;
605 	struct txp_swdesc	sc_txd[TX_ENTRIES];
606 	struct callout		txp_stat_timer;
607 	struct ifmedia		sc_ifmedia;
608 	struct txp_tx_ring	sc_txhir, sc_txlor;
609 	struct txp_rxbuf_desc	*sc_rxbufs;
610 	struct txp_rx_ring	sc_rxhir, sc_rxlor;
611 	u_int16_t		sc_xcvr;
612 	u_int16_t		sc_seq;
613 	u_int32_t		sc_rx_capability, sc_tx_capability;
614 };
615 
616 struct txp_fw_file_header {
617 	u_int8_t	magicid[8];	/* TYPHOON\0 */
618 	u_int32_t	version;
619 	u_int32_t	nsections;
620 	u_int32_t	addr;
621 };
622 
623 struct txp_fw_section_header {
624 	u_int32_t	nbytes;
625 	u_int16_t	cksum;
626 	u_int16_t	reserved;
627 	u_int32_t	addr;
628 };
629 
630 #define	TXP_MAX_SEGLEN	0xffff
631 #define	TXP_MAX_PKTLEN	0x0800
632 
633 #define	WRITE_REG(sc,reg,val) \
634     bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val)
635 #define	READ_REG(sc,reg) \
636     bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg)
637 
638 struct txp_type {
639 	u_int16_t		txp_vid;
640 	u_int16_t		txp_did;
641 	char			*txp_name;
642 };
643