1 /* Copyright (c) 2002, Marek Michalkiewicz 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: io2313.h 2456 2014-11-19 09:57:29Z saaadhu $ */ 32 33 /* avr/io2313.h - definitions for AT90S2313 */ 34 35 #ifndef _AVR_IO2313_H_ 36 #define _AVR_IO2313_H_ 1 37 38 /* This file should only be included from <avr/io.h>, never directly. */ 39 40 #ifndef _AVR_IO_H_ 41 # error "Include <avr/io.h> instead of this file." 42 #endif 43 44 #ifndef _AVR_IOXXX_H_ 45 # define _AVR_IOXXX_H_ "io2313.h" 46 #else 47 # error "Attempt to include more than one <avr/ioXXX.h> file." 48 #endif 49 50 /* I/O registers */ 51 52 /* Analog Comparator Control and Status Register */ 53 #define ACSR _SFR_IO8(0x08) 54 55 /* UART Baud Rate Register */ 56 #define UBRR _SFR_IO8(0x09) 57 58 /* UART Control Register */ 59 #define UCR _SFR_IO8(0x0A) 60 61 /* UART Status Register */ 62 #define USR _SFR_IO8(0x0B) 63 64 /* UART I/O Data Register */ 65 #define UDR _SFR_IO8(0x0C) 66 67 /* Input Pins, Port D */ 68 #define PIND _SFR_IO8(0x10) 69 70 /* Data Direction Register, Port D */ 71 #define DDRD _SFR_IO8(0x11) 72 73 /* Data Register, Port D */ 74 #define PORTD _SFR_IO8(0x12) 75 76 /* Input Pins, Port B */ 77 #define PINB _SFR_IO8(0x16) 78 79 /* Data Direction Register, Port B */ 80 #define DDRB _SFR_IO8(0x17) 81 82 /* Data Register, Port B */ 83 #define PORTB _SFR_IO8(0x18) 84 85 /* EEPROM Control Register */ 86 #define EECR _SFR_IO8(0x1C) 87 88 /* EEPROM Data Register */ 89 #define EEDR _SFR_IO8(0x1D) 90 91 /* EEPROM Address Register */ 92 #define EEAR _SFR_IO8(0x1E) 93 #define EEARL _SFR_IO8(0x1E) 94 95 /* Watchdog Timer Control Register */ 96 #define WDTCR _SFR_IO8(0x21) 97 98 /* T/C 1 Input Capture Register */ 99 #define ICR1 _SFR_IO16(0x24) 100 #define ICR1L _SFR_IO8(0x24) 101 #define ICR1H _SFR_IO8(0x25) 102 103 /* Output Compare Register 1 */ 104 #define OCR1 _SFR_IO16(0x2A) 105 #define OCR1L _SFR_IO8(0x2A) 106 #define OCR1H _SFR_IO8(0x2B) 107 #define OCR1A _SFR_IO16(0x2A) 108 #define OCR1AL _SFR_IO8(0x2A) 109 #define OCR1AH _SFR_IO8(0x2B) 110 111 /* Timer/Counter 1 */ 112 #define TCNT1 _SFR_IO16(0x2C) 113 #define TCNT1L _SFR_IO8(0x2C) 114 #define TCNT1H _SFR_IO8(0x2D) 115 116 /* Timer/Counter 1 Control and Status Register */ 117 #define TCCR1B _SFR_IO8(0x2E) 118 119 /* Timer/Counter 1 Control Register */ 120 #define TCCR1A _SFR_IO8(0x2F) 121 122 /* Timer/Counter 0 */ 123 #define TCNT0 _SFR_IO8(0x32) 124 125 /* Timer/Counter 0 Control Register */ 126 #define TCCR0 _SFR_IO8(0x33) 127 128 /* MCU general Control Register */ 129 #define MCUCR _SFR_IO8(0x35) 130 131 /* Timer/Counter Interrupt Flag register */ 132 #define TIFR _SFR_IO8(0x38) 133 134 /* Timer/Counter Interrupt MaSK register */ 135 #define TIMSK _SFR_IO8(0x39) 136 137 /* General Interrupt Flag Register */ 138 #define GIFR _SFR_IO8(0x3A) 139 140 /* General Interrupt MaSK register */ 141 #define GIMSK _SFR_IO8(0x3B) 142 143 /* 0x3C..0x3D SP */ 144 145 /* 0x3F SREG */ 146 147 /* Interrupt vectors */ 148 149 /* External Interrupt Request 0 */ 150 #define INT0_vect_num 1 151 #define INT0_vect _VECTOR(1) 152 #define SIG_INTERRUPT0 _VECTOR(1) 153 154 /* External Interrupt Request 1 */ 155 #define INT1_vect_num 2 156 #define INT1_vect _VECTOR(2) 157 #define SIG_INTERRUPT1 _VECTOR(2) 158 159 /* Timer/Counter1 Capture Event */ 160 #define TIMER1_CAPT1_vect_num 3 161 #define TIMER1_CAPT1_vect _VECTOR(3) 162 #define SIG_INPUT_CAPTURE1 _VECTOR(3) 163 164 /* Timer/Counter1 Compare Match */ 165 #define TIMER1_COMP1_vect_num 4 166 #define TIMER1_COMP1_vect _VECTOR(4) 167 #define SIG_OUTPUT_COMPARE1A _VECTOR(4) 168 169 /* Timer/Counter1 Overflow */ 170 #define TIMER1_OVF1_vect_num 5 171 #define TIMER1_OVF1_vect _VECTOR(5) 172 #define SIG_OVERFLOW1 _VECTOR(5) 173 174 /* Timer/Counter0 Overflow */ 175 #define TIMER0_OVF0_vect_num 6 176 #define TIMER0_OVF0_vect _VECTOR(6) 177 #define SIG_OVERFLOW0 _VECTOR(6) 178 179 /* UART, Rx Complete */ 180 #define UART_RX_vect_num 7 181 #define UART_RX_vect _VECTOR(7) 182 #define SIG_UART_RECV _VECTOR(7) 183 184 /* UART Data Register Empty */ 185 #define UART_UDRE_vect_num 8 186 #define UART_UDRE_vect _VECTOR(8) 187 #define SIG_UART_DATA _VECTOR(8) 188 189 /* UART, Tx Complete */ 190 #define UART_TX_vect_num 9 191 #define UART_TX_vect _VECTOR(9) 192 #define SIG_UART_TRANS _VECTOR(9) 193 194 /* Analog Comparator */ 195 #define ANA_COMP_vect_num 10 196 #define ANA_COMP_vect _VECTOR(10) 197 #define SIG_COMPARATOR _VECTOR(10) 198 199 #define _VECTORS_SIZE 22 200 201 /* 202 * The Register Bit names are represented by their bit number (0-7). 203 */ 204 205 /* General Interrupt MaSK register */ 206 #define INT1 7 207 #define INT0 6 208 209 /* General Interrupt Flag Register */ 210 #define INTF1 7 211 #define INTF0 6 212 213 /* Timer/Counter Interrupt MaSK register */ 214 #define TOIE1 7 215 #define OCIE1A 6 216 #define TICIE 3 /* old name */ 217 #define TICIE1 3 218 #define TOIE0 1 219 220 /* Timer/Counter Interrupt Flag register */ 221 #define TOV1 7 222 #define OCF1A 6 223 #define ICF1 3 224 #define TOV0 1 225 226 /* MCU general Control Register */ 227 #define SE 5 228 #define SM 4 229 #define ISC11 3 230 #define ISC10 2 231 #define ISC01 1 232 #define ISC00 0 233 234 /* Timer/Counter 0 Control Register */ 235 #define CS02 2 236 #define CS01 1 237 #define CS00 0 238 239 /* Timer/Counter 1 Control Register */ 240 #define COM1A1 7 241 #define COM1A0 6 242 #define PWM11 1 243 #define PWM10 0 244 245 /* Timer/Counter 1 Control and Status Register */ 246 #define ICNC1 7 247 #define ICES1 6 248 #define CTC1 3 249 #define CS12 2 250 #define CS11 1 251 #define CS10 0 252 253 /* Watchdog Timer Control Register */ 254 #define WDTOE 4 255 #define WDE 3 256 #define WDP2 2 257 #define WDP1 1 258 #define WDP0 0 259 260 /* EEPROM Control Register */ 261 #define EEMWE 2 262 #define EEWE 1 263 #define EERE 0 264 265 /* Data Register, Port B */ 266 #define PB7 7 267 #define PB6 6 268 #define PB5 5 269 #define PB4 4 270 #define PB3 3 271 #define PB2 2 272 #define PB1 1 273 #define PB0 0 274 275 /* Data Direction Register, Port B */ 276 #define DDB7 7 277 #define DDB6 6 278 #define DDB5 5 279 #define DDB4 4 280 #define DDB3 3 281 #define DDB2 2 282 #define DDB1 1 283 #define DDB0 0 284 285 /* Input Pins, Port B */ 286 #define PINB7 7 287 #define PINB6 6 288 #define PINB5 5 289 #define PINB4 4 290 #define PINB3 3 291 #define PINB2 2 292 #define PINB1 1 293 #define PINB0 0 294 295 /* Data Register, Port D */ 296 #define PD6 6 297 #define PD5 5 298 #define PD4 4 299 #define PD3 3 300 #define PD2 2 301 #define PD1 1 302 #define PD0 0 303 304 /* Data Direction Register, Port D */ 305 #define DDD6 6 306 #define DDD5 5 307 #define DDD4 4 308 #define DDD3 3 309 #define DDD2 2 310 #define DDD1 1 311 #define DDD0 0 312 313 /* Input Pins, Port D */ 314 #define PIND6 6 315 #define PIND5 5 316 #define PIND4 4 317 #define PIND3 3 318 #define PIND2 2 319 #define PIND1 1 320 #define PIND0 0 321 322 /* UART Status Register */ 323 #define RXC 7 324 #define TXC 6 325 #define UDRE 5 326 #define FE 4 327 #define DOR 3 328 329 /* UART Control Register */ 330 #define RXCIE 7 331 #define TXCIE 6 332 #define UDRIE 5 333 #define RXEN 4 334 #define TXEN 3 335 #define CHR9 2 336 #define RXB8 1 337 #define TXB8 0 338 339 /* Analog Comparator Control and Status Register */ 340 #define ACD 7 341 #define ACO 5 342 #define ACI 4 343 #define ACIE 3 344 #define ACIC 2 345 #define ACIS1 1 346 #define ACIS0 0 347 348 /* EEPROM Control Register */ 349 #define EERIE 3 350 #define EEMWE 2 351 #define EEWE 1 352 #define EERE 0 353 354 /* Constants */ 355 #define RAMSTART 0x60 356 #define RAMEND 0xDF 357 #define XRAMEND RAMEND 358 #define E2END 0x7F 359 #define E2PAGESIZE 0 360 #define FLASHEND 0x07FF 361 362 363 /* Fuses */ 364 #define FUSE_MEMORY_SIZE 1 365 366 /* Low Fuse Byte */ 367 #define FUSE_FSTRT (unsigned char)~_BV(0) 368 #define FUSE_SPIEN (unsigned char)~_BV(5) 369 #define LFUSE_DEFAULT (0xFF) 370 371 372 /* Lock Bits */ 373 #define __LOCK_BITS_EXIST 374 375 376 /* Signature */ 377 #define SIGNATURE_0 0x1E 378 #define SIGNATURE_1 0x91 379 #define SIGNATURE_2 0x01 380 381 382 #define SLEEP_MODE_IDLE 0 383 #define SLEEP_MODE_PWR_DOWN _BV(SM) 384 385 386 #endif /* _AVR_IO2313_H_ */ 387