1 /* Copyright (c) 2002, Marek Michalkiewicz 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: io8515.h 2456 2014-11-19 09:57:29Z saaadhu $ */ 32 33 /* avr/io8515.h - definitions for AT90S8515 */ 34 35 #ifndef _AVR_IO8515_H_ 36 #define _AVR_IO8515_H_ 1 37 38 /* This file should only be included from <avr/io.h>, never directly. */ 39 40 #ifndef _AVR_IO_H_ 41 # error "Include <avr/io.h> instead of this file." 42 #endif 43 44 #ifndef _AVR_IOXXX_H_ 45 # define _AVR_IOXXX_H_ "io8515.h" 46 #else 47 # error "Attempt to include more than one <avr/ioXXX.h> file." 48 #endif 49 50 /* I/O registers */ 51 52 /* Analog Comparator Control and Status Register */ 53 #define ACSR _SFR_IO8(0x08) 54 55 /* UART Baud Rate Register */ 56 #define UBRR _SFR_IO8(0x09) 57 58 /* UART Control Register */ 59 #define UCR _SFR_IO8(0x0A) 60 61 /* UART Status Register */ 62 #define USR _SFR_IO8(0x0B) 63 64 /* UART I/O Data Register */ 65 #define UDR _SFR_IO8(0x0C) 66 67 /* SPI Control Register */ 68 #define SPCR _SFR_IO8(0x0D) 69 70 /* SPI Status Register */ 71 #define SPSR _SFR_IO8(0x0E) 72 73 /* SPI I/O Data Register */ 74 #define SPDR _SFR_IO8(0x0F) 75 76 /* Input Pins, Port D */ 77 #define PIND _SFR_IO8(0x10) 78 79 /* Data Direction Register, Port D */ 80 #define DDRD _SFR_IO8(0x11) 81 82 /* Data Register, Port D */ 83 #define PORTD _SFR_IO8(0x12) 84 85 /* Input Pins, Port C */ 86 #define PINC _SFR_IO8(0x13) 87 88 /* Data Direction Register, Port C */ 89 #define DDRC _SFR_IO8(0x14) 90 91 /* Data Register, Port C */ 92 #define PORTC _SFR_IO8(0x15) 93 94 /* Input Pins, Port B */ 95 #define PINB _SFR_IO8(0x16) 96 97 /* Data Direction Register, Port B */ 98 #define DDRB _SFR_IO8(0x17) 99 100 /* Data Register, Port B */ 101 #define PORTB _SFR_IO8(0x18) 102 103 /* Input Pins, Port A */ 104 #define PINA _SFR_IO8(0x19) 105 106 /* Data Direction Register, Port A */ 107 #define DDRA _SFR_IO8(0x1A) 108 109 /* Data Register, Port A */ 110 #define PORTA _SFR_IO8(0x1B) 111 112 /* EEPROM Control Register */ 113 #define EECR _SFR_IO8(0x1C) 114 115 /* EEPROM Data Register */ 116 #define EEDR _SFR_IO8(0x1D) 117 118 /* EEPROM Address Register */ 119 #define EEAR _SFR_IO16(0x1E) 120 #define EEARL _SFR_IO8(0x1E) 121 #define EEARH _SFR_IO8(0x1F) 122 123 /* Watchdog Timer Control Register */ 124 #define WDTCR _SFR_IO8(0x21) 125 126 /* T/C 1 Input Capture Register */ 127 #define ICR1 _SFR_IO16(0x24) 128 #define ICR1L _SFR_IO8(0x24) 129 #define ICR1H _SFR_IO8(0x25) 130 131 /* Timer/Counter1 Output Compare Register B */ 132 #define OCR1B _SFR_IO16(0x28) 133 #define OCR1BL _SFR_IO8(0x28) 134 #define OCR1BH _SFR_IO8(0x29) 135 136 /* Timer/Counter1 Output Compare Register A */ 137 #define OCR1A _SFR_IO16(0x2A) 138 #define OCR1AL _SFR_IO8(0x2A) 139 #define OCR1AH _SFR_IO8(0x2B) 140 141 /* Timer/Counter 1 */ 142 #define TCNT1 _SFR_IO16(0x2C) 143 #define TCNT1L _SFR_IO8(0x2C) 144 #define TCNT1H _SFR_IO8(0x2D) 145 146 /* Timer/Counter 1 Control and Status Register */ 147 #define TCCR1B _SFR_IO8(0x2E) 148 149 /* Timer/Counter 1 Control Register */ 150 #define TCCR1A _SFR_IO8(0x2F) 151 152 /* Timer/Counter 0 */ 153 #define TCNT0 _SFR_IO8(0x32) 154 155 /* Timer/Counter 0 Control Register */ 156 #define TCCR0 _SFR_IO8(0x33) 157 158 /* MCU general Control Register */ 159 #define MCUCR _SFR_IO8(0x35) 160 161 /* Timer/Counter Interrupt Flag register */ 162 #define TIFR _SFR_IO8(0x38) 163 164 /* Timer/Counter Interrupt MaSK register */ 165 #define TIMSK _SFR_IO8(0x39) 166 167 /* General Interrupt Flag Register */ 168 #define GIFR _SFR_IO8(0x3A) 169 170 /* General Interrupt MaSK register */ 171 #define GIMSK _SFR_IO8(0x3B) 172 173 /* 0x3D..0x3E SP */ 174 175 /* 0x3F SREG */ 176 177 /* Interrupt vectors */ 178 179 /* External Interrupt Request 0 */ 180 #define INT0_vect_num 1 181 #define INT0_vect _VECTOR(1) 182 #define SIG_INTERRUPT0 _VECTOR(1) 183 184 /* External Interrupt Request 1 */ 185 #define INT1_vect_num 2 186 #define INT1_vect _VECTOR(2) 187 #define SIG_INTERRUPT1 _VECTOR(2) 188 189 /* Timer/Counter Capture Event */ 190 #define TIMER1_CAPT_vect_num 3 191 #define TIMER1_CAPT_vect _VECTOR(3) 192 #define SIG_INPUT_CAPTURE1 _VECTOR(3) 193 194 /* Timer/Counter1 Compare Match A */ 195 #define TIMER1_COMPA_vect_num 4 196 #define TIMER1_COMPA_vect _VECTOR(4) 197 #define SIG_OUTPUT_COMPARE1A _VECTOR(4) 198 199 /* Timer/Counter1 Compare MatchB */ 200 #define TIMER1_COMPB_vect_num 5 201 #define TIMER1_COMPB_vect _VECTOR(5) 202 #define SIG_OUTPUT_COMPARE1B _VECTOR(5) 203 204 /* Timer/Counter1 Overflow */ 205 #define TIMER1_OVF_vect_num 6 206 #define TIMER1_OVF_vect _VECTOR(6) 207 #define SIG_OVERFLOW1 _VECTOR(6) 208 209 /* Timer/Counter0 Overflow */ 210 #define TIMER0_OVF_vect_num 7 211 #define TIMER0_OVF_vect _VECTOR(7) 212 #define SIG_OVERFLOW0 _VECTOR(7) 213 214 /* Serial Transfer Complete */ 215 #define SPI_STC_vect_num 8 216 #define SPI_STC_vect _VECTOR(8) 217 #define SIG_SPI _VECTOR(8) 218 219 /* UART, Rx Complete */ 220 #define UART_RX_vect_num 9 221 #define UART_RX_vect _VECTOR(9) 222 #define SIG_UART_RECV _VECTOR(9) 223 224 /* UART Data Register Empty */ 225 #define UART_UDRE_vect_num 10 226 #define UART_UDRE_vect _VECTOR(10) 227 #define SIG_UART_DATA _VECTOR(10) 228 229 /* UART, Tx Complete */ 230 #define UART_TX_vect_num 11 231 #define UART_TX_vect _VECTOR(11) 232 #define SIG_UART_TRANS _VECTOR(11) 233 234 /* Analog Comparator */ 235 #define ANA_COMP_vect_num 12 236 #define ANA_COMP_vect _VECTOR(12) 237 #define SIG_COMPARATOR _VECTOR(12) 238 239 #define _VECTORS_SIZE 26 240 241 /* 242 The Register Bit names are represented by their bit number (0-7). 243 */ 244 245 /* General Interrupt MaSK register */ 246 #define INT1 7 247 #define INT0 6 248 249 /* General Interrupt Flag Register */ 250 #define INTF1 7 251 #define INTF0 6 252 253 /* Timer/Counter Interrupt MaSK register */ 254 #define TOIE1 7 255 #define OCIE1A 6 256 #define OCIE1B 5 257 #define TICIE1 3 258 #define TOIE0 1 259 260 /* Timer/Counter Interrupt Flag register */ 261 #define TOV1 7 262 #define OCF1A 6 263 #define OCF1B 5 264 #define ICF1 3 265 #define TOV0 1 266 267 /* MCU general Control Register */ 268 #define SRE 7 269 #define SRW 6 270 #define SE 5 271 #define SM 4 272 #define ISC11 3 273 #define ISC10 2 274 #define ISC01 1 275 #define ISC00 0 276 277 /* Timer/Counter 0 Control Register */ 278 #define CS02 2 279 #define CS01 1 280 #define CS00 0 281 282 /* Timer/Counter 1 Control Register */ 283 #define COM1A1 7 284 #define COM1A0 6 285 #define COM1B1 5 286 #define COM1B0 4 287 #define PWM11 1 288 #define PWM10 0 289 290 /* Timer/Counter 1 Control and Status Register */ 291 #define ICNC1 7 292 #define ICES1 6 293 #define CTC1 3 294 #define CS12 2 295 #define CS11 1 296 #define CS10 0 297 298 /* Watchdog Timer Control Register */ 299 #define WDTOE 4 300 #define WDE 3 301 #define WDP2 2 302 #define WDP1 1 303 #define WDP0 0 304 305 /* Data Register, Port A */ 306 #define PA7 7 307 #define PA6 6 308 #define PA5 5 309 #define PA4 4 310 #define PA3 3 311 #define PA2 2 312 #define PA1 1 313 #define PA0 0 314 315 /* Data Direction Register, Port A */ 316 #define DDA7 7 317 #define DDA6 6 318 #define DDA5 5 319 #define DDA4 4 320 #define DDA3 3 321 #define DDA2 2 322 #define DDA1 1 323 #define DDA0 0 324 325 /* Input Pins, Port A */ 326 #define PINA7 7 327 #define PINA6 6 328 #define PINA5 5 329 #define PINA4 4 330 #define PINA3 3 331 #define PINA2 2 332 #define PINA1 1 333 #define PINA0 0 334 335 /* Data Register, Port B */ 336 #define PB7 7 337 #define PB6 6 338 #define PB5 5 339 #define PB4 4 340 #define PB3 3 341 #define PB2 2 342 #define PB1 1 343 #define PB0 0 344 345 /* Data Direction Register, Port B */ 346 #define DDB7 7 347 #define DDB6 6 348 #define DDB5 5 349 #define DDB4 4 350 #define DDB3 3 351 #define DDB2 2 352 #define DDB1 1 353 #define DDB0 0 354 355 /* Input Pins, Port B */ 356 #define PINB7 7 357 #define PINB6 6 358 #define PINB5 5 359 #define PINB4 4 360 #define PINB3 3 361 #define PINB2 2 362 #define PINB1 1 363 #define PINB0 0 364 365 /* Data Register, Port C */ 366 #define PC7 7 367 #define PC6 6 368 #define PC5 5 369 #define PC4 4 370 #define PC3 3 371 #define PC2 2 372 #define PC1 1 373 #define PC0 0 374 375 /* Data Direction Register, Port C */ 376 #define DDC7 7 377 #define DDC6 6 378 #define DDC5 5 379 #define DDC4 4 380 #define DDC3 3 381 #define DDC2 2 382 #define DDC1 1 383 #define DDC0 0 384 385 /* Input Pins, Port C */ 386 #define PINC7 7 387 #define PINC6 6 388 #define PINC5 5 389 #define PINC4 4 390 #define PINC3 3 391 #define PINC2 2 392 #define PINC1 1 393 #define PINC0 0 394 395 /* Data Register, Port D */ 396 #define PD7 7 397 #define PD6 6 398 #define PD5 5 399 #define PD4 4 400 #define PD3 3 401 #define PD2 2 402 #define PD1 1 403 #define PD0 0 404 405 /* Data Direction Register, Port D */ 406 #define DDD7 7 407 #define DDD6 6 408 #define DDD5 5 409 #define DDD4 4 410 #define DDD3 3 411 #define DDD2 2 412 #define DDD1 1 413 #define DDD0 0 414 415 /* Input Pins, Port D */ 416 #define PIND7 7 417 #define PIND6 6 418 #define PIND5 5 419 #define PIND4 4 420 #define PIND3 3 421 #define PIND2 2 422 #define PIND1 1 423 #define PIND0 0 424 425 /* SPI Status Register */ 426 #define SPIF 7 427 #define WCOL 6 428 429 /* SPI Control Register */ 430 #define SPIE 7 431 #define SPE 6 432 #define DORD 5 433 #define MSTR 4 434 #define CPOL 3 435 #define CPHA 2 436 #define SPR1 1 437 #define SPR0 0 438 439 /* UART Status Register */ 440 #define RXC 7 441 #define TXC 6 442 #define UDRE 5 443 #define FE 4 444 #define DOR 3 445 446 /* UART Control Register */ 447 #define RXCIE 7 448 #define TXCIE 6 449 #define UDRIE 5 450 #define RXEN 4 451 #define TXEN 3 452 #define CHR9 2 453 #define RXB8 1 454 #define TXB8 0 455 456 /* Analog Comparator Control and Status Register */ 457 #define ACD 7 458 #define ACO 5 459 #define ACI 4 460 #define ACIE 3 461 #define ACIC 2 462 #define ACIS1 1 463 #define ACIS0 0 464 465 /* EEPROM Control Register */ 466 #define EERIE 3 467 #define EEMWE 2 468 #define EEWE 1 469 #define EERE 0 470 471 /* Constants */ 472 #define RAMSTART 0x60 473 #define RAMEND 0x25F /* Last On-Chip SRAM Location */ 474 #define XRAMEND 0xFFFF 475 #define E2END 0x1FF 476 #define E2PAGESIZE 0 477 #define FLASHEND 0x1FFF 478 479 480 /* Fuses */ 481 #define FUSE_MEMORY_SIZE 1 482 483 /* Low Fuse Byte */ 484 #define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */ 485 #define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */ 486 #define LFUSE_DEFAULT (0xFF) 487 488 489 /* Lock Bits */ 490 #define __LOCK_BITS_EXIST 491 492 493 /* Signature */ 494 #define SIGNATURE_0 0x1E 495 #define SIGNATURE_1 0x93 496 #define SIGNATURE_2 0x01 497 498 499 #define SLEEP_MODE_IDLE 0 500 #define SLEEP_MODE_PWR_DOWN _BV(SM) 501 502 503 #endif /* _AVR_IO8515_H_ */ 504