1 /* Copyright (c) 2009-2010 Atmel Corporation 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iox32d4.h 2482 2015-08-06 08:54:17Z pitchumani $ */ 32 33 /* avr/iox32d4.h - definitions for ATxmega32D4 */ 34 35 /* This file should only be included from <avr/io.h>, never directly. */ 36 37 #ifndef _AVR_IO_H_ 38 # error "Include <avr/io.h> instead of this file." 39 #endif 40 41 #ifndef _AVR_IOXXX_H_ 42 # define _AVR_IOXXX_H_ "iox32d4.h" 43 #else 44 # error "Attempt to include more than one <avr/ioXXX.h> file." 45 #endif 46 47 48 #ifndef _AVR_ATxmega32D4_H_ 49 #define _AVR_ATxmega32D4_H_ 1 50 51 52 /* Ungrouped common registers */ 53 #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ 54 #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ 55 #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ 56 #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ 57 #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ 58 #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ 59 #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ 60 #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ 61 #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ 62 #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ 63 #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ 64 #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ 65 #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ 66 #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ 67 #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ 68 #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ 69 70 #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ 71 #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ 72 #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ 73 #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ 74 #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ 75 #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ 76 #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ 77 #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ 78 #define SREG _SFR_MEM8(0x003F) /* Status Register */ 79 80 81 /* C Language Only */ 82 #if !defined (__ASSEMBLER__) 83 84 #include <stdint.h> 85 86 typedef volatile uint8_t register8_t; 87 typedef volatile uint16_t register16_t; 88 typedef volatile uint32_t register32_t; 89 90 91 #ifdef _WORDREGISTER 92 #undef _WORDREGISTER 93 #endif 94 #define _WORDREGISTER(regname) \ 95 __extension__ union \ 96 { \ 97 register16_t regname; \ 98 struct \ 99 { \ 100 register8_t regname ## L; \ 101 register8_t regname ## H; \ 102 }; \ 103 } 104 105 #ifdef _DWORDREGISTER 106 #undef _DWORDREGISTER 107 #endif 108 #define _DWORDREGISTER(regname) \ 109 __extension__ union \ 110 { \ 111 register32_t regname; \ 112 struct \ 113 { \ 114 register8_t regname ## 0; \ 115 register8_t regname ## 1; \ 116 register8_t regname ## 2; \ 117 register8_t regname ## 3; \ 118 }; \ 119 } 120 121 122 /* 123 ========================================================================== 124 IO Module Structures 125 ========================================================================== 126 */ 127 128 129 /* 130 -------------------------------------------------------------------------- 131 XOCD - On-Chip Debug System 132 -------------------------------------------------------------------------- 133 */ 134 135 /* On-Chip Debug System */ 136 typedef struct OCD_struct 137 { 138 register8_t OCDR0; /* OCD Register 0 */ 139 register8_t OCDR1; /* OCD Register 1 */ 140 } OCD_t; 141 142 143 /* CCP signatures */ 144 typedef enum CCP_enum 145 { 146 CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ 147 CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ 148 } CCP_t; 149 150 151 /* 152 -------------------------------------------------------------------------- 153 CLK - Clock System 154 -------------------------------------------------------------------------- 155 */ 156 157 /* Clock System */ 158 typedef struct CLK_struct 159 { 160 register8_t CTRL; /* Control Register */ 161 register8_t PSCTRL; /* Prescaler Control Register */ 162 register8_t LOCK; /* Lock register */ 163 register8_t RTCCTRL; /* RTC Control Register */ 164 } CLK_t; 165 166 /* 167 -------------------------------------------------------------------------- 168 CLK - Clock System 169 -------------------------------------------------------------------------- 170 */ 171 172 /* Power Reduction */ 173 typedef struct PR_struct 174 { 175 register8_t PRGEN; /* General Power Reduction */ 176 register8_t PRPA; /* Power Reduction Port A */ 177 register8_t PRPB; /* Power Reduction Port B */ 178 register8_t PRPC; /* Power Reduction Port C */ 179 register8_t PRPD; /* Power Reduction Port D */ 180 register8_t PRPE; /* Power Reduction Port E */ 181 register8_t PRPF; /* Power Reduction Port F */ 182 } PR_t; 183 184 /* System Clock Selection */ 185 typedef enum CLK_SCLKSEL_enum 186 { 187 CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ 188 CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ 189 CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ 190 CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ 191 CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ 192 } CLK_SCLKSEL_t; 193 194 /* Prescaler A Division Factor */ 195 typedef enum CLK_PSADIV_enum 196 { 197 CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ 198 CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ 199 CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ 200 CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ 201 CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ 202 CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ 203 CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ 204 CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ 205 CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ 206 CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ 207 } CLK_PSADIV_t; 208 209 /* Prescaler B and C Division Factor */ 210 typedef enum CLK_PSBCDIV_enum 211 { 212 CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ 213 CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ 214 CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ 215 CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ 216 } CLK_PSBCDIV_t; 217 218 /* RTC Clock Source */ 219 typedef enum CLK_RTCSRC_enum 220 { 221 CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ 222 CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ 223 CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ 224 CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ 225 } CLK_RTCSRC_t; 226 227 228 /* 229 -------------------------------------------------------------------------- 230 SLEEP - Sleep Controller 231 -------------------------------------------------------------------------- 232 */ 233 234 /* Sleep Controller */ 235 typedef struct SLEEP_struct 236 { 237 register8_t CTRL; /* Control Register */ 238 } SLEEP_t; 239 240 /* Sleep Mode */ 241 typedef enum SLEEP_SMODE_enum 242 { 243 SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ 244 SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ 245 SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ 246 SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ 247 SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ 248 } SLEEP_SMODE_t; 249 250 251 #define SLEEP_MODE_IDLE (0x00<<1) 252 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 253 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 254 #define SLEEP_MODE_STANDBY (0x06<<1) 255 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 256 257 258 /* 259 -------------------------------------------------------------------------- 260 OSC - Oscillator 261 -------------------------------------------------------------------------- 262 */ 263 264 /* Oscillator */ 265 typedef struct OSC_struct 266 { 267 register8_t CTRL; /* Control Register */ 268 register8_t STATUS; /* Status Register */ 269 register8_t XOSCCTRL; /* External Oscillator Control Register */ 270 register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ 271 register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ 272 register8_t PLLCTRL; /* PLL Control REgister */ 273 register8_t DFLLCTRL; /* DFLL Control Register */ 274 } OSC_t; 275 276 /* Oscillator Frequency Range */ 277 typedef enum OSC_FRQRANGE_enum 278 { 279 OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ 280 OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ 281 OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ 282 OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ 283 } OSC_FRQRANGE_t; 284 285 /* External Oscillator Selection and Startup Time */ 286 typedef enum OSC_XOSCSEL_enum 287 { 288 OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ 289 OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ 290 OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ 291 OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ 292 OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ 293 } OSC_XOSCSEL_t; 294 295 /* PLL Clock Source */ 296 typedef enum OSC_PLLSRC_enum 297 { 298 OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ 299 OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ 300 OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ 301 } OSC_PLLSRC_t; 302 303 304 /* 305 -------------------------------------------------------------------------- 306 DFLL - DFLL 307 -------------------------------------------------------------------------- 308 */ 309 310 /* DFLL */ 311 typedef struct DFLL_struct 312 { 313 register8_t CTRL; /* Control Register */ 314 register8_t reserved_0x01; 315 register8_t CALA; /* Calibration Register A */ 316 register8_t CALB; /* Calibration Register B */ 317 register8_t COMP0; /* Oscillator Compare Register 0 */ 318 register8_t COMP1; /* Oscillator Compare Register 1 */ 319 register8_t COMP2; /* Oscillator Compare Register 2 */ 320 register8_t reserved_0x07; 321 } DFLL_t; 322 323 324 /* 325 -------------------------------------------------------------------------- 326 RST - Reset 327 -------------------------------------------------------------------------- 328 */ 329 330 /* Reset */ 331 typedef struct RST_struct 332 { 333 register8_t STATUS; /* Status Register */ 334 register8_t CTRL; /* Control Register */ 335 } RST_t; 336 337 338 /* 339 -------------------------------------------------------------------------- 340 WDT - Watch-Dog Timer 341 -------------------------------------------------------------------------- 342 */ 343 344 /* Watch-Dog Timer */ 345 typedef struct WDT_struct 346 { 347 register8_t CTRL; /* Control */ 348 register8_t WINCTRL; /* Windowed Mode Control */ 349 register8_t STATUS; /* Status */ 350 } WDT_t; 351 352 /* Period setting */ 353 typedef enum WDT_PER_enum 354 { 355 WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 356 WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 357 WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 358 WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 359 WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ 360 WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ 361 WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ 362 WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 363 WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 364 WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 365 WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 366 } WDT_PER_t; 367 368 /* Closed window period */ 369 typedef enum WDT_WPER_enum 370 { 371 WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ 372 WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ 373 WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ 374 WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ 375 WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ 376 WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ 377 WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ 378 WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ 379 WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ 380 WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ 381 WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ 382 } WDT_WPER_t; 383 384 385 /* 386 -------------------------------------------------------------------------- 387 MCU - MCU Control 388 -------------------------------------------------------------------------- 389 */ 390 391 /* MCU Control */ 392 typedef struct MCU_struct 393 { 394 register8_t DEVID0; /* Device ID byte 0 */ 395 register8_t DEVID1; /* Device ID byte 1 */ 396 register8_t DEVID2; /* Device ID byte 2 */ 397 register8_t REVID; /* Revision ID */ 398 register8_t JTAGUID; /* JTAG User ID */ 399 register8_t reserved_0x05; 400 register8_t MCUCR; /* MCU Control */ 401 register8_t reserved_0x07; 402 register8_t EVSYSLOCK; /* Event System Lock */ 403 register8_t AWEXLOCK; /* AWEX Lock */ 404 register8_t reserved_0x0A; 405 register8_t reserved_0x0B; 406 } MCU_t; 407 408 409 /* 410 -------------------------------------------------------------------------- 411 PMIC - Programmable Multi-level Interrupt Controller 412 -------------------------------------------------------------------------- 413 */ 414 415 /* Programmable Multi-level Interrupt Controller */ 416 typedef struct PMIC_struct 417 { 418 register8_t STATUS; /* Status Register */ 419 register8_t INTPRI; /* Interrupt Priority */ 420 register8_t CTRL; /* Control Register */ 421 } PMIC_t; 422 423 424 425 /* 426 -------------------------------------------------------------------------- 427 CRC - Cyclic Redundancy Checker 428 -------------------------------------------------------------------------- 429 */ 430 431 /* Cyclic Redundancy Checker */ 432 typedef struct CRC_struct 433 { 434 register8_t CTRL; /* Control Register */ 435 register8_t STATUS; /* Status Register */ 436 register8_t reserved_0x02; 437 register8_t DATAIN; /* Data Input */ 438 register8_t CHECKSUM0; /* Checksum byte 0 */ 439 register8_t CHECKSUM1; /* Checksum byte 1 */ 440 register8_t CHECKSUM2; /* Checksum byte 2 */ 441 register8_t CHECKSUM3; /* Checksum byte 3 */ 442 } CRC_t; 443 444 /* Reset */ 445 typedef enum CRC_RESET_enum 446 { 447 CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ 448 CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ 449 CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ 450 } CRC_RESET_t; 451 452 /* Input Source */ 453 typedef enum CRC_SOURCE_enum 454 { 455 CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ 456 CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ 457 CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ 458 } CRC_SOURCE_t; 459 460 461 /* 462 -------------------------------------------------------------------------- 463 EVSYS - Event System 464 -------------------------------------------------------------------------- 465 */ 466 467 /* Event System */ 468 typedef struct EVSYS_struct 469 { 470 register8_t CH0MUX; /* Event Channel 0 Multiplexer */ 471 register8_t CH1MUX; /* Event Channel 1 Multiplexer */ 472 register8_t CH2MUX; /* Event Channel 2 Multiplexer */ 473 register8_t CH3MUX; /* Event Channel 3 Multiplexer */ 474 register8_t reserved_0x04; 475 register8_t reserved_0x05; 476 register8_t reserved_0x06; 477 register8_t reserved_0x07; 478 register8_t CH0CTRL; /* Channel 0 Control Register */ 479 register8_t CH1CTRL; /* Channel 1 Control Register */ 480 register8_t CH2CTRL; /* Channel 2 Control Register */ 481 register8_t CH3CTRL; /* Channel 3 Control Register */ 482 register8_t reserved_0x0C; 483 register8_t reserved_0x0D; 484 register8_t reserved_0x0E; 485 register8_t reserved_0x0F; 486 register8_t STROBE; /* Event Strobe */ 487 register8_t DATA; /* Event Data */ 488 } EVSYS_t; 489 490 /* Quadrature Decoder Index Recognition Mode */ 491 typedef enum EVSYS_QDIRM_enum 492 { 493 EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ 494 EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ 495 EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ 496 EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ 497 } EVSYS_QDIRM_t; 498 499 /* Digital filter coefficient */ 500 typedef enum EVSYS_DIGFILT_enum 501 { 502 EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ 503 EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ 504 EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ 505 EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ 506 EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ 507 EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ 508 EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ 509 EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ 510 } EVSYS_DIGFILT_t; 511 512 /* Event Channel multiplexer input selection */ 513 typedef enum EVSYS_CHMUX_enum 514 { 515 EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ 516 EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ 517 EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ 518 EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ 519 EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ 520 EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ 521 EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ 522 EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ 523 EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ 524 EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ 525 EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ 526 EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ 527 EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ 528 EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ 529 EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ 530 EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ 531 EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ 532 EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ 533 EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ 534 EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ 535 EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ 536 EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ 537 EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ 538 EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ 539 EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ 540 EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ 541 EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ 542 EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ 543 EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ 544 EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ 545 EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ 546 EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ 547 EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ 548 EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ 549 EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ 550 EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ 551 EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ 552 EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ 553 EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ 554 EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ 555 EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ 556 EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ 557 EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ 558 EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ 559 EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ 560 EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ 561 EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ 562 EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ 563 EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ 564 EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ 565 EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ 566 EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ 567 EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ 568 EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ 569 EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ 570 EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ 571 EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ 572 EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ 573 EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ 574 EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ 575 EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ 576 EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ 577 EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ 578 EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ 579 EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ 580 EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ 581 EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ 582 EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ 583 EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ 584 EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ 585 EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ 586 EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ 587 EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ 588 EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ 589 EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ 590 EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ 591 EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ 592 EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ 593 EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ 594 EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ 595 EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ 596 EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ 597 EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ 598 EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ 599 EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ 600 EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ 601 EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ 602 EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ 603 EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ 604 EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ 605 EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ 606 EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ 607 EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ 608 EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ 609 EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ 610 EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ 611 EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ 612 EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ 613 EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ 614 EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ 615 EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ 616 EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ 617 EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ 618 EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ 619 EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ 620 EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ 621 EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ 622 EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ 623 EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ 624 EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ 625 EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ 626 } EVSYS_CHMUX_t; 627 628 629 /* 630 -------------------------------------------------------------------------- 631 NVM - Non Volatile Memory Controller 632 -------------------------------------------------------------------------- 633 */ 634 635 /* Non-volatile Memory Controller */ 636 typedef struct NVM_struct 637 { 638 register8_t ADDR0; /* Address Register 0 */ 639 register8_t ADDR1; /* Address Register 1 */ 640 register8_t ADDR2; /* Address Register 2 */ 641 register8_t reserved_0x03; 642 register8_t DATA0; /* Data Register 0 */ 643 register8_t DATA1; /* Data Register 1 */ 644 register8_t DATA2; /* Data Register 2 */ 645 register8_t reserved_0x07; 646 register8_t reserved_0x08; 647 register8_t reserved_0x09; 648 register8_t CMD; /* Command */ 649 register8_t CTRLA; /* Control Register A */ 650 register8_t CTRLB; /* Control Register B */ 651 register8_t INTCTRL; /* Interrupt Control */ 652 register8_t reserved_0x0E; 653 register8_t STATUS; /* Status */ 654 register8_t LOCK_BITS; /* Lock Bits */ 655 } NVM_t; 656 657 /* 658 -------------------------------------------------------------------------- 659 NVM - Non Volatile Memory Controller 660 -------------------------------------------------------------------------- 661 */ 662 663 /* Lock Bits */ 664 typedef struct NVM_LOCKBITS_struct 665 { 666 register8_t LOCKBITS; /* Lock Bits */ 667 } NVM_LOCKBITS_t; 668 669 /* 670 -------------------------------------------------------------------------- 671 NVM - Non Volatile Memory Controller 672 -------------------------------------------------------------------------- 673 */ 674 675 /* Fuses */ 676 typedef struct NVM_FUSES_struct 677 { 678 register8_t FUSEBYTE0; /* User ID */ 679 register8_t FUSEBYTE1; /* Watchdog Configuration */ 680 register8_t FUSEBYTE2; /* Reset Configuration */ 681 register8_t reserved_0x03; 682 register8_t FUSEBYTE4; /* Start-up Configuration */ 683 register8_t FUSEBYTE5; /* EESAVE and BOD Level */ 684 } NVM_FUSES_t; 685 686 /* 687 -------------------------------------------------------------------------- 688 NVM - Non Volatile Memory Controller 689 -------------------------------------------------------------------------- 690 */ 691 692 /* Production Signatures */ 693 typedef struct NVM_PROD_SIGNATURES_struct 694 { 695 register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ 696 register8_t reserved_0x01; 697 register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ 698 register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ 699 register8_t reserved_0x04; 700 register8_t reserved_0x05; 701 register8_t reserved_0x06; 702 register8_t reserved_0x07; 703 register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ 704 register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ 705 register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ 706 register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ 707 register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ 708 register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ 709 register8_t reserved_0x0E; 710 register8_t reserved_0x0F; 711 register8_t WAFNUM; /* Wafer Number */ 712 register8_t reserved_0x11; 713 register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ 714 register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ 715 register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ 716 register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ 717 register8_t reserved_0x16; 718 register8_t reserved_0x17; 719 register8_t reserved_0x18; 720 register8_t reserved_0x19; 721 register8_t reserved_0x1A; 722 register8_t reserved_0x1B; 723 register8_t reserved_0x1C; 724 register8_t reserved_0x1D; 725 register8_t reserved_0x1E; 726 register8_t reserved_0x1F; 727 register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ 728 register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ 729 register8_t reserved_0x22; 730 register8_t reserved_0x23; 731 register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ 732 register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ 733 register8_t reserved_0x26; 734 register8_t reserved_0x27; 735 register8_t reserved_0x28; 736 register8_t reserved_0x29; 737 register8_t reserved_0x2A; 738 register8_t reserved_0x2B; 739 register8_t reserved_0x2C; 740 register8_t reserved_0x2D; 741 register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ 742 register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ 743 register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ 744 register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ 745 register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ 746 register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ 747 register8_t reserved_0x34; 748 register8_t reserved_0x35; 749 register8_t reserved_0x36; 750 register8_t reserved_0x37; 751 register8_t reserved_0x38; 752 register8_t reserved_0x39; 753 register8_t reserved_0x3A; 754 register8_t reserved_0x3B; 755 register8_t reserved_0x3C; 756 register8_t reserved_0x3D; 757 register8_t reserved_0x3E; 758 } NVM_PROD_SIGNATURES_t; 759 760 /* NVM Command */ 761 typedef enum NVM_CMD_enum 762 { 763 NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ 764 NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ 765 NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ 766 NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ 767 NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ 768 NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ 769 NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ 770 NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ 771 NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ 772 NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ 773 NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ 774 NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ 775 NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ 776 NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ 777 NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ 778 NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ 779 NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ 780 NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ 781 NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ 782 NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ 783 NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ 784 NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ 785 NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ 786 NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ 787 NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ 788 NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ 789 } NVM_CMD_t; 790 791 /* SPM ready interrupt level */ 792 typedef enum NVM_SPMLVL_enum 793 { 794 NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ 795 NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ 796 NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ 797 NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ 798 } NVM_SPMLVL_t; 799 800 /* EEPROM ready interrupt level */ 801 typedef enum NVM_EELVL_enum 802 { 803 NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 804 NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ 805 NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ 806 NVM_EELVL_HI_gc = (0x03<<0), /* High level */ 807 } NVM_EELVL_t; 808 809 /* Boot lock bits - boot setcion */ 810 typedef enum NVM_BLBB_enum 811 { 812 NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ 813 NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ 814 NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ 815 NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ 816 } NVM_BLBB_t; 817 818 /* Boot lock bits - application section */ 819 typedef enum NVM_BLBA_enum 820 { 821 NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ 822 NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ 823 NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ 824 NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ 825 } NVM_BLBA_t; 826 827 /* Boot lock bits - application table section */ 828 typedef enum NVM_BLBAT_enum 829 { 830 NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ 831 NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ 832 NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ 833 NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ 834 } NVM_BLBAT_t; 835 836 /* Lock bits */ 837 typedef enum NVM_LB_enum 838 { 839 NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ 840 NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ 841 NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ 842 } NVM_LB_t; 843 844 /* Boot Loader Section Reset Vector */ 845 typedef enum BOOTRST_enum 846 { 847 BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ 848 BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ 849 } BOOTRST_t; 850 851 /* BOD operation */ 852 typedef enum BOD_enum 853 { 854 BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ 855 BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ 856 BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ 857 } BOD_t; 858 859 /* Watchdog (Window) Timeout Period */ 860 typedef enum WD_enum 861 { 862 WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ 863 WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ 864 WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ 865 WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ 866 WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ 867 WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ 868 WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ 869 WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ 870 WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ 871 WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ 872 WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ 873 } WD_t; 874 875 /* Start-up Time */ 876 typedef enum SUT_enum 877 { 878 SUT_0MS_gc = (0x03<<2), /* 0 ms */ 879 SUT_4MS_gc = (0x01<<2), /* 4 ms */ 880 SUT_64MS_gc = (0x00<<2), /* 64 ms */ 881 } SUT_t; 882 883 /* Brown Out Detection Voltage Level */ 884 typedef enum BODLVL_enum 885 { 886 BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ 887 BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ 888 BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ 889 BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ 890 BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ 891 BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ 892 BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ 893 } BODLVL_t; 894 895 /* 896 -------------------------------------------------------------------------- 897 AC - Analog Comparator 898 -------------------------------------------------------------------------- 899 */ 900 901 /* Analog Comparator */ 902 typedef struct AC_struct 903 { 904 register8_t AC0CTRL; /* Comparator 0 Control */ 905 register8_t AC1CTRL; /* Comparator 1 Control */ 906 register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ 907 register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ 908 register8_t CTRLA; /* Control Register A */ 909 register8_t CTRLB; /* Control Register B */ 910 register8_t WINCTRL; /* Window Mode Control */ 911 register8_t STATUS; /* Status */ 912 } AC_t; 913 914 /* Interrupt mode */ 915 typedef enum AC_INTMODE_enum 916 { 917 AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ 918 AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ 919 AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ 920 } AC_INTMODE_t; 921 922 /* Interrupt level */ 923 typedef enum AC_INTLVL_enum 924 { 925 AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ 926 AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ 927 AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ 928 AC_INTLVL_HI_gc = (0x03<<4), /* High level */ 929 } AC_INTLVL_t; 930 931 /* Hysteresis mode selection */ 932 typedef enum AC_HYSMODE_enum 933 { 934 AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ 935 AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ 936 AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ 937 } AC_HYSMODE_t; 938 939 /* Positive input multiplexer selection */ 940 typedef enum AC_MUXPOS_enum 941 { 942 AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ 943 AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ 944 AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ 945 AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ 946 AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ 947 AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ 948 AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ 949 AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ 950 } AC_MUXPOS_t; 951 952 /* Negative input multiplexer selection */ 953 typedef enum AC_MUXNEG_enum 954 { 955 AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ 956 AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ 957 AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ 958 AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ 959 AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ 960 AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ 961 AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ 962 AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ 963 } AC_MUXNEG_t; 964 965 /* Windows interrupt mode */ 966 typedef enum AC_WINTMODE_enum 967 { 968 AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ 969 AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ 970 AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ 971 AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ 972 } AC_WINTMODE_t; 973 974 /* Window interrupt level */ 975 typedef enum AC_WINTLVL_enum 976 { 977 AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 978 AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ 979 AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ 980 AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ 981 } AC_WINTLVL_t; 982 983 /* Window mode state */ 984 typedef enum AC_WSTATE_enum 985 { 986 AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ 987 AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ 988 AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ 989 } AC_WSTATE_t; 990 991 992 /* 993 -------------------------------------------------------------------------- 994 ADC - Analog/Digital Converter 995 -------------------------------------------------------------------------- 996 */ 997 998 /* ADC Channel */ 999 typedef struct ADC_CH_struct 1000 { 1001 register8_t CTRL; /* Control Register */ 1002 register8_t MUXCTRL; /* MUX Control */ 1003 register8_t INTCTRL; /* Channel Interrupt Control */ 1004 register8_t INTFLAGS; /* Interrupt Flags */ 1005 _WORDREGISTER(RES); /* Channel Result */ 1006 register8_t reserved_0x6; 1007 register8_t reserved_0x7; 1008 } ADC_CH_t; 1009 1010 /* 1011 -------------------------------------------------------------------------- 1012 ADC - Analog/Digital Converter 1013 -------------------------------------------------------------------------- 1014 */ 1015 1016 /* Analog-to-Digital Converter */ 1017 typedef struct ADC_struct 1018 { 1019 register8_t CTRLA; /* Control Register A */ 1020 register8_t CTRLB; /* Control Register B */ 1021 register8_t REFCTRL; /* Reference Control */ 1022 register8_t EVCTRL; /* Event Control */ 1023 register8_t PRESCALER; /* Clock Prescaler */ 1024 register8_t reserved_0x05; 1025 register8_t INTFLAGS; /* Interrupt Flags */ 1026 register8_t reserved_0x07; 1027 register8_t reserved_0x08; 1028 register8_t reserved_0x09; 1029 register8_t reserved_0x0A; 1030 register8_t reserved_0x0B; 1031 _WORDREGISTER(CAL); /* Calibration Value */ 1032 register8_t reserved_0x0E; 1033 register8_t reserved_0x0F; 1034 _WORDREGISTER(CH0RES); /* Channel 0 Result */ 1035 register8_t reserved_0x12; 1036 register8_t reserved_0x13; 1037 register8_t reserved_0x14; 1038 register8_t reserved_0x15; 1039 register8_t reserved_0x16; 1040 register8_t reserved_0x17; 1041 _WORDREGISTER(CMP); /* Compare Value */ 1042 register8_t reserved_0x1A; 1043 register8_t reserved_0x1B; 1044 register8_t reserved_0x1C; 1045 register8_t reserved_0x1D; 1046 register8_t reserved_0x1E; 1047 register8_t reserved_0x1F; 1048 ADC_CH_t CH0; /* ADC Channel 0 */ 1049 } ADC_t; 1050 1051 /* Positive input multiplexer selection */ 1052 typedef enum ADC_CH_MUXPOS_enum 1053 { 1054 ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ 1055 ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ 1056 ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ 1057 ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ 1058 ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ 1059 ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ 1060 ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ 1061 ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ 1062 ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ 1063 ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ 1064 ADC_CH_MUXPOS_PIN10_gc = (0x10<<3), /* Input pin 10 */ 1065 ADC_CH_MUXPOS_PIN11_gc = (0x11<<3), /* Input pin 11 */ 1066 } ADC_CH_MUXPOS_t; 1067 1068 /* Internal input multiplexer selections */ 1069 typedef enum ADC_CH_MUXINT_enum 1070 { 1071 ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ 1072 ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ 1073 ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ 1074 ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ 1075 } ADC_CH_MUXINT_t; 1076 1077 /* Negative input multiplexer selection */ 1078 typedef enum ADC_CH_MUXNEG_enum 1079 { 1080 ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ 1081 ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ 1082 ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ 1083 ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ 1084 ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ 1085 ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ 1086 ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ 1087 ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ 1088 } ADC_CH_MUXNEG_t; 1089 1090 /* Input mode */ 1091 typedef enum ADC_CH_INPUTMODE_enum 1092 { 1093 ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ 1094 ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ 1095 ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ 1096 ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ 1097 } ADC_CH_INPUTMODE_t; 1098 1099 /* Gain factor */ 1100 typedef enum ADC_CH_GAIN_enum 1101 { 1102 ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ 1103 ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ 1104 ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ 1105 ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ 1106 ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ 1107 ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ 1108 ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ 1109 ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ 1110 } ADC_CH_GAIN_t; 1111 1112 /* Conversion result resolution */ 1113 typedef enum ADC_RESOLUTION_enum 1114 { 1115 ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ 1116 ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ 1117 ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ 1118 } ADC_RESOLUTION_t; 1119 1120 typedef enum ADC_CURRLIMIT_enum 1121 { 1122 ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ 1123 ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ 1124 ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ 1125 ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ 1126 } ADC_CURRLIMIT_t; 1127 1128 /* Voltage reference selection */ 1129 typedef enum ADC_REFSEL_enum 1130 { 1131 ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ 1132 ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ 1133 ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ 1134 ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ 1135 } ADC_REFSEL_t; 1136 1137 /* Channel sweep selection */ 1138 typedef enum ADC_SWEEP_enum 1139 { 1140 ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ 1141 } ADC_SWEEP_t; 1142 1143 /* Event channel input selection */ 1144 typedef enum ADC_EVSEL_enum 1145 { 1146 ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ 1147 ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ 1148 ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ 1149 ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ 1150 ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ 1151 ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ 1152 ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ 1153 ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ 1154 } ADC_EVSEL_t; 1155 1156 /* Event action selection */ 1157 typedef enum ADC_EVACT_enum 1158 { 1159 ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ 1160 ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ 1161 } ADC_EVACT_t; 1162 1163 /* Interupt mode */ 1164 typedef enum ADC_CH_INTMODE_enum 1165 { 1166 ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ 1167 ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ 1168 ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ 1169 } ADC_CH_INTMODE_t; 1170 1171 /* Interrupt level */ 1172 typedef enum ADC_CH_INTLVL_enum 1173 { 1174 ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ 1175 ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ 1176 ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ 1177 ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ 1178 } ADC_CH_INTLVL_t; 1179 1180 /* Clock prescaler */ 1181 typedef enum ADC_PRESCALER_enum 1182 { 1183 ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ 1184 ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ 1185 ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ 1186 ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ 1187 ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ 1188 ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ 1189 ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ 1190 ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ 1191 } ADC_PRESCALER_t; 1192 1193 1194 /* 1195 -------------------------------------------------------------------------- 1196 RTC - Real-Time Clounter 1197 -------------------------------------------------------------------------- 1198 */ 1199 1200 /* Real-Time Counter */ 1201 typedef struct RTC_struct 1202 { 1203 register8_t CTRL; /* Control Register */ 1204 register8_t STATUS; /* Status Register */ 1205 register8_t INTCTRL; /* Interrupt Control Register */ 1206 register8_t INTFLAGS; /* Interrupt Flags */ 1207 register8_t TEMP; /* Temporary register */ 1208 register8_t reserved_0x05; 1209 register8_t reserved_0x06; 1210 register8_t reserved_0x07; 1211 _WORDREGISTER(CNT); /* Count Register */ 1212 _WORDREGISTER(PER); /* Period Register */ 1213 _WORDREGISTER(COMP); /* Compare Register */ 1214 } RTC_t; 1215 1216 /* Prescaler Factor */ 1217 typedef enum RTC_PRESCALER_enum 1218 { 1219 RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ 1220 RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ 1221 RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ 1222 RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ 1223 RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ 1224 RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ 1225 RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ 1226 RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ 1227 } RTC_PRESCALER_t; 1228 1229 /* Compare Interrupt level */ 1230 typedef enum RTC_COMPINTLVL_enum 1231 { 1232 RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1233 RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1234 RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1235 RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ 1236 } RTC_COMPINTLVL_t; 1237 1238 /* Overflow Interrupt level */ 1239 typedef enum RTC_OVFINTLVL_enum 1240 { 1241 RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1242 RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 1243 RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 1244 RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 1245 } RTC_OVFINTLVL_t; 1246 1247 1248 /* 1249 -------------------------------------------------------------------------- 1250 EBI - External Bus Interface 1251 -------------------------------------------------------------------------- 1252 */ 1253 1254 /* EBI Chip Select Module */ 1255 typedef struct EBI_CS_struct 1256 { 1257 register8_t CTRLA; /* Chip Select Control Register A */ 1258 register8_t CTRLB; /* Chip Select Control Register B */ 1259 _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ 1260 } EBI_CS_t; 1261 1262 /* 1263 -------------------------------------------------------------------------- 1264 EBI - External Bus Interface 1265 -------------------------------------------------------------------------- 1266 */ 1267 1268 /* External Bus Interface */ 1269 typedef struct EBI_struct 1270 { 1271 register8_t CTRL; /* Control */ 1272 register8_t SDRAMCTRLA; /* SDRAM Control Register A */ 1273 register8_t reserved_0x02; 1274 register8_t reserved_0x03; 1275 _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ 1276 _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ 1277 register8_t SDRAMCTRLB; /* SDRAM Control Register B */ 1278 register8_t SDRAMCTRLC; /* SDRAM Control Register C */ 1279 register8_t reserved_0x0A; 1280 register8_t reserved_0x0B; 1281 register8_t reserved_0x0C; 1282 register8_t reserved_0x0D; 1283 register8_t reserved_0x0E; 1284 register8_t reserved_0x0F; 1285 EBI_CS_t CS0; /* Chip Select 0 */ 1286 EBI_CS_t CS1; /* Chip Select 1 */ 1287 EBI_CS_t CS2; /* Chip Select 2 */ 1288 EBI_CS_t CS3; /* Chip Select 3 */ 1289 } EBI_t; 1290 1291 /* Chip Select adress space */ 1292 typedef enum EBI_CS_ASIZE_enum 1293 { 1294 EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ 1295 EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ 1296 EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ 1297 EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ 1298 EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ 1299 EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ 1300 EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ 1301 EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ 1302 EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ 1303 EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ 1304 EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ 1305 EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ 1306 EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ 1307 EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ 1308 EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ 1309 EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ 1310 EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ 1311 } EBI_CS_ASIZE_t; 1312 1313 /* */ 1314 typedef enum EBI_CS_SRWS_enum 1315 { 1316 EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ 1317 EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ 1318 EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ 1319 EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ 1320 EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ 1321 EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ 1322 EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ 1323 EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ 1324 } EBI_CS_SRWS_t; 1325 1326 /* Chip Select address mode */ 1327 typedef enum EBI_CS_MODE_enum 1328 { 1329 EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ 1330 EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ 1331 EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ 1332 EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ 1333 } EBI_CS_MODE_t; 1334 1335 /* Chip Select SDRAM mode */ 1336 typedef enum EBI_CS_SDMODE_enum 1337 { 1338 EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ 1339 EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ 1340 } EBI_CS_SDMODE_t; 1341 1342 /* */ 1343 typedef enum EBI_SDDATAW_enum 1344 { 1345 EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ 1346 EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ 1347 } EBI_SDDATAW_t; 1348 1349 /* */ 1350 typedef enum EBI_LPCMODE_enum 1351 { 1352 EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ 1353 EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ 1354 } EBI_LPCMODE_t; 1355 1356 /* */ 1357 typedef enum EBI_SRMODE_enum 1358 { 1359 EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ 1360 EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ 1361 EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ 1362 EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ 1363 } EBI_SRMODE_t; 1364 1365 /* */ 1366 typedef enum EBI_IFMODE_enum 1367 { 1368 EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ 1369 EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ 1370 EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ 1371 EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ 1372 } EBI_IFMODE_t; 1373 1374 /* */ 1375 typedef enum EBI_SDCOL_enum 1376 { 1377 EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ 1378 EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ 1379 EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ 1380 EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ 1381 } EBI_SDCOL_t; 1382 1383 /* */ 1384 typedef enum EBI_MRDLY_enum 1385 { 1386 EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ 1387 EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ 1388 EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ 1389 EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ 1390 } EBI_MRDLY_t; 1391 1392 /* */ 1393 typedef enum EBI_ROWCYCDLY_enum 1394 { 1395 EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ 1396 EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ 1397 EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ 1398 EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ 1399 EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ 1400 EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ 1401 EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ 1402 EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ 1403 } EBI_ROWCYCDLY_t; 1404 1405 /* */ 1406 typedef enum EBI_RPDLY_enum 1407 { 1408 EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ 1409 EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ 1410 EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ 1411 EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ 1412 EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ 1413 EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ 1414 EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ 1415 EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ 1416 } EBI_RPDLY_t; 1417 1418 /* */ 1419 typedef enum EBI_WRDLY_enum 1420 { 1421 EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ 1422 EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ 1423 EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ 1424 EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ 1425 } EBI_WRDLY_t; 1426 1427 /* */ 1428 typedef enum EBI_ESRDLY_enum 1429 { 1430 EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ 1431 EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ 1432 EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ 1433 EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ 1434 EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ 1435 EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ 1436 EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ 1437 EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ 1438 } EBI_ESRDLY_t; 1439 1440 /* */ 1441 typedef enum EBI_ROWCOLDLY_enum 1442 { 1443 EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ 1444 EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ 1445 EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ 1446 EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ 1447 EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ 1448 EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ 1449 EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ 1450 EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ 1451 } EBI_ROWCOLDLY_t; 1452 1453 1454 /* 1455 -------------------------------------------------------------------------- 1456 TWI - Two-Wire Interface 1457 -------------------------------------------------------------------------- 1458 */ 1459 1460 /* */ 1461 typedef struct TWI_MASTER_struct 1462 { 1463 register8_t CTRLA; /* Control Register A */ 1464 register8_t CTRLB; /* Control Register B */ 1465 register8_t CTRLC; /* Control Register C */ 1466 register8_t STATUS; /* Status Register */ 1467 register8_t BAUD; /* Baurd Rate Control Register */ 1468 register8_t ADDR; /* Address Register */ 1469 register8_t DATA; /* Data Register */ 1470 } TWI_MASTER_t; 1471 1472 /* 1473 -------------------------------------------------------------------------- 1474 TWI - Two-Wire Interface 1475 -------------------------------------------------------------------------- 1476 */ 1477 1478 /* */ 1479 typedef struct TWI_SLAVE_struct 1480 { 1481 register8_t CTRLA; /* Control Register A */ 1482 register8_t CTRLB; /* Control Register B */ 1483 register8_t STATUS; /* Status Register */ 1484 register8_t ADDR; /* Address Register */ 1485 register8_t DATA; /* Data Register */ 1486 register8_t ADDRMASK; /* Address Mask Register */ 1487 } TWI_SLAVE_t; 1488 1489 /* 1490 -------------------------------------------------------------------------- 1491 TWI - Two-Wire Interface 1492 -------------------------------------------------------------------------- 1493 */ 1494 1495 /* Two-Wire Interface */ 1496 typedef struct TWI_struct 1497 { 1498 register8_t CTRL; /* TWI Common Control Register */ 1499 TWI_MASTER_t MASTER; /* TWI master module */ 1500 TWI_SLAVE_t SLAVE; /* TWI slave module */ 1501 } TWI_t; 1502 1503 /* Master Interrupt Level */ 1504 typedef enum TWI_MASTER_INTLVL_enum 1505 { 1506 TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1507 TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1508 TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1509 TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1510 } TWI_MASTER_INTLVL_t; 1511 1512 /* Inactive Timeout */ 1513 typedef enum TWI_MASTER_TIMEOUT_enum 1514 { 1515 TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ 1516 TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ 1517 TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ 1518 TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ 1519 } TWI_MASTER_TIMEOUT_t; 1520 1521 /* Master Command */ 1522 typedef enum TWI_MASTER_CMD_enum 1523 { 1524 TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1525 TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ 1526 TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ 1527 TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ 1528 } TWI_MASTER_CMD_t; 1529 1530 /* Master Bus State */ 1531 typedef enum TWI_MASTER_BUSSTATE_enum 1532 { 1533 TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ 1534 TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ 1535 TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ 1536 TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ 1537 } TWI_MASTER_BUSSTATE_t; 1538 1539 /* Slave Interrupt Level */ 1540 typedef enum TWI_SLAVE_INTLVL_enum 1541 { 1542 TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 1543 TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ 1544 TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ 1545 TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ 1546 } TWI_SLAVE_INTLVL_t; 1547 1548 /* Slave Command */ 1549 typedef enum TWI_SLAVE_CMD_enum 1550 { 1551 TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ 1552 TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ 1553 TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ 1554 } TWI_SLAVE_CMD_t; 1555 1556 1557 /* 1558 -------------------------------------------------------------------------- 1559 PORT - Port Configuration 1560 -------------------------------------------------------------------------- 1561 */ 1562 1563 /* I/O port Configuration */ 1564 typedef struct PORTCFG_struct 1565 { 1566 register8_t MPCMASK; /* Multi-pin Configuration Mask */ 1567 register8_t reserved_0x01; 1568 register8_t VPCTRLA; /* Virtual Port Control Register A */ 1569 register8_t VPCTRLB; /* Virtual Port Control Register B */ 1570 register8_t CLKEVOUT; /* Clock and Event Out Register */ 1571 } PORTCFG_t; 1572 1573 /* 1574 -------------------------------------------------------------------------- 1575 PORT - Port Configuration 1576 -------------------------------------------------------------------------- 1577 */ 1578 1579 /* Virtual Port */ 1580 typedef struct VPORT_struct 1581 { 1582 register8_t DIR; /* I/O Port Data Direction */ 1583 register8_t OUT; /* I/O Port Output */ 1584 register8_t IN; /* I/O Port Input */ 1585 register8_t INTFLAGS; /* Interrupt Flag Register */ 1586 } VPORT_t; 1587 1588 /* 1589 -------------------------------------------------------------------------- 1590 PORT - Port Configuration 1591 -------------------------------------------------------------------------- 1592 */ 1593 1594 /* I/O Ports */ 1595 typedef struct PORT_struct 1596 { 1597 register8_t DIR; /* I/O Port Data Direction */ 1598 register8_t DIRSET; /* I/O Port Data Direction Set */ 1599 register8_t DIRCLR; /* I/O Port Data Direction Clear */ 1600 register8_t DIRTGL; /* I/O Port Data Direction Toggle */ 1601 register8_t OUT; /* I/O Port Output */ 1602 register8_t OUTSET; /* I/O Port Output Set */ 1603 register8_t OUTCLR; /* I/O Port Output Clear */ 1604 register8_t OUTTGL; /* I/O Port Output Toggle */ 1605 register8_t IN; /* I/O port Input */ 1606 register8_t INTCTRL; /* Interrupt Control Register */ 1607 register8_t INT0MASK; /* Port Interrupt 0 Mask */ 1608 register8_t INT1MASK; /* Port Interrupt 1 Mask */ 1609 register8_t INTFLAGS; /* Interrupt Flag Register */ 1610 register8_t reserved_0x0D; 1611 register8_t reserved_0x0E; 1612 register8_t reserved_0x0F; 1613 register8_t PIN0CTRL; /* Pin 0 Control Register */ 1614 register8_t PIN1CTRL; /* Pin 1 Control Register */ 1615 register8_t PIN2CTRL; /* Pin 2 Control Register */ 1616 register8_t PIN3CTRL; /* Pin 3 Control Register */ 1617 register8_t PIN4CTRL; /* Pin 4 Control Register */ 1618 register8_t PIN5CTRL; /* Pin 5 Control Register */ 1619 register8_t PIN6CTRL; /* Pin 6 Control Register */ 1620 register8_t PIN7CTRL; /* Pin 7 Control Register */ 1621 } PORT_t; 1622 1623 /* Virtual Port 0 Mapping */ 1624 typedef enum PORTCFG_VP0MAP_enum 1625 { 1626 PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ 1627 PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ 1628 PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ 1629 PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ 1630 PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ 1631 PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ 1632 PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ 1633 PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ 1634 PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ 1635 PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ 1636 PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ 1637 PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ 1638 PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ 1639 PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ 1640 PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ 1641 PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ 1642 } PORTCFG_VP0MAP_t; 1643 1644 /* Virtual Port 1 Mapping */ 1645 typedef enum PORTCFG_VP1MAP_enum 1646 { 1647 PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ 1648 PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ 1649 PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ 1650 PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ 1651 PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ 1652 PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ 1653 PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ 1654 PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ 1655 PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ 1656 PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ 1657 PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ 1658 PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ 1659 PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ 1660 PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ 1661 PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ 1662 PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ 1663 } PORTCFG_VP1MAP_t; 1664 1665 /* Virtual Port 2 Mapping */ 1666 typedef enum PORTCFG_VP2MAP_enum 1667 { 1668 PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ 1669 PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ 1670 PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ 1671 PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ 1672 PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ 1673 PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ 1674 PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ 1675 PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ 1676 PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ 1677 PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ 1678 PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ 1679 PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ 1680 PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ 1681 PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ 1682 PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ 1683 PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ 1684 } PORTCFG_VP2MAP_t; 1685 1686 /* Virtual Port 3 Mapping */ 1687 typedef enum PORTCFG_VP3MAP_enum 1688 { 1689 PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ 1690 PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ 1691 PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ 1692 PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ 1693 PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ 1694 PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ 1695 PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ 1696 PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ 1697 PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ 1698 PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ 1699 PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ 1700 PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ 1701 PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ 1702 PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ 1703 PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ 1704 PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ 1705 } PORTCFG_VP3MAP_t; 1706 1707 /* Clock Output Port */ 1708 typedef enum PORTCFG_CLKOUT_enum 1709 { 1710 PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ 1711 PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ 1712 PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ 1713 PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ 1714 } PORTCFG_CLKOUT_t; 1715 1716 /* Event Output Port */ 1717 typedef enum PORTCFG_EVOUT_enum 1718 { 1719 PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ 1720 PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ 1721 PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ 1722 PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ 1723 } PORTCFG_EVOUT_t; 1724 1725 /* Port Interrupt 0 Level */ 1726 typedef enum PORT_INT0LVL_enum 1727 { 1728 PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 1729 PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ 1730 PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ 1731 PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ 1732 } PORT_INT0LVL_t; 1733 1734 /* Port Interrupt 1 Level */ 1735 typedef enum PORT_INT1LVL_enum 1736 { 1737 PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1738 PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ 1739 PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ 1740 PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ 1741 } PORT_INT1LVL_t; 1742 1743 /* Output/Pull Configuration */ 1744 typedef enum PORT_OPC_enum 1745 { 1746 PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ 1747 PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ 1748 PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ 1749 PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ 1750 PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ 1751 PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ 1752 PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ 1753 PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ 1754 } PORT_OPC_t; 1755 1756 /* Input/Sense Configuration */ 1757 typedef enum PORT_ISC_enum 1758 { 1759 PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ 1760 PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ 1761 PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ 1762 PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ 1763 PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ 1764 } PORT_ISC_t; 1765 1766 1767 /* 1768 -------------------------------------------------------------------------- 1769 TC - 16-bit Timer/Counter With PWM 1770 -------------------------------------------------------------------------- 1771 */ 1772 1773 /* 16-bit Timer/Counter 0 */ 1774 typedef struct TC0_struct 1775 { 1776 register8_t CTRLA; /* Control Register A */ 1777 register8_t CTRLB; /* Control Register B */ 1778 register8_t CTRLC; /* Control register C */ 1779 register8_t CTRLD; /* Control Register D */ 1780 register8_t CTRLE; /* Control Register E */ 1781 register8_t reserved_0x05; 1782 register8_t INTCTRLA; /* Interrupt Control Register A */ 1783 register8_t INTCTRLB; /* Interrupt Control Register B */ 1784 register8_t CTRLFCLR; /* Control Register F Clear */ 1785 register8_t CTRLFSET; /* Control Register F Set */ 1786 register8_t CTRLGCLR; /* Control Register G Clear */ 1787 register8_t CTRLGSET; /* Control Register G Set */ 1788 register8_t INTFLAGS; /* Interrupt Flag Register */ 1789 register8_t reserved_0x0D; 1790 register8_t reserved_0x0E; 1791 register8_t TEMP; /* Temporary Register For 16-bit Access */ 1792 register8_t reserved_0x10; 1793 register8_t reserved_0x11; 1794 register8_t reserved_0x12; 1795 register8_t reserved_0x13; 1796 register8_t reserved_0x14; 1797 register8_t reserved_0x15; 1798 register8_t reserved_0x16; 1799 register8_t reserved_0x17; 1800 register8_t reserved_0x18; 1801 register8_t reserved_0x19; 1802 register8_t reserved_0x1A; 1803 register8_t reserved_0x1B; 1804 register8_t reserved_0x1C; 1805 register8_t reserved_0x1D; 1806 register8_t reserved_0x1E; 1807 register8_t reserved_0x1F; 1808 _WORDREGISTER(CNT); /* Count */ 1809 register8_t reserved_0x22; 1810 register8_t reserved_0x23; 1811 register8_t reserved_0x24; 1812 register8_t reserved_0x25; 1813 _WORDREGISTER(PER); /* Period */ 1814 _WORDREGISTER(CCA); /* Compare or Capture A */ 1815 _WORDREGISTER(CCB); /* Compare or Capture B */ 1816 _WORDREGISTER(CCC); /* Compare or Capture C */ 1817 _WORDREGISTER(CCD); /* Compare or Capture D */ 1818 register8_t reserved_0x30; 1819 register8_t reserved_0x31; 1820 register8_t reserved_0x32; 1821 register8_t reserved_0x33; 1822 register8_t reserved_0x34; 1823 register8_t reserved_0x35; 1824 _WORDREGISTER(PERBUF); /* Period Buffer */ 1825 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 1826 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 1827 _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ 1828 _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ 1829 } TC0_t; 1830 1831 /* 1832 -------------------------------------------------------------------------- 1833 TC - 16-bit Timer/Counter With PWM 1834 -------------------------------------------------------------------------- 1835 */ 1836 1837 /* 16-bit Timer/Counter 1 */ 1838 typedef struct TC1_struct 1839 { 1840 register8_t CTRLA; /* Control Register A */ 1841 register8_t CTRLB; /* Control Register B */ 1842 register8_t CTRLC; /* Control register C */ 1843 register8_t CTRLD; /* Control Register D */ 1844 register8_t CTRLE; /* Control Register E */ 1845 register8_t reserved_0x05; 1846 register8_t INTCTRLA; /* Interrupt Control Register A */ 1847 register8_t INTCTRLB; /* Interrupt Control Register B */ 1848 register8_t CTRLFCLR; /* Control Register F Clear */ 1849 register8_t CTRLFSET; /* Control Register F Set */ 1850 register8_t CTRLGCLR; /* Control Register G Clear */ 1851 register8_t CTRLGSET; /* Control Register G Set */ 1852 register8_t INTFLAGS; /* Interrupt Flag Register */ 1853 register8_t reserved_0x0D; 1854 register8_t reserved_0x0E; 1855 register8_t TEMP; /* Temporary Register For 16-bit Access */ 1856 register8_t reserved_0x10; 1857 register8_t reserved_0x11; 1858 register8_t reserved_0x12; 1859 register8_t reserved_0x13; 1860 register8_t reserved_0x14; 1861 register8_t reserved_0x15; 1862 register8_t reserved_0x16; 1863 register8_t reserved_0x17; 1864 register8_t reserved_0x18; 1865 register8_t reserved_0x19; 1866 register8_t reserved_0x1A; 1867 register8_t reserved_0x1B; 1868 register8_t reserved_0x1C; 1869 register8_t reserved_0x1D; 1870 register8_t reserved_0x1E; 1871 register8_t reserved_0x1F; 1872 _WORDREGISTER(CNT); /* Count */ 1873 register8_t reserved_0x22; 1874 register8_t reserved_0x23; 1875 register8_t reserved_0x24; 1876 register8_t reserved_0x25; 1877 _WORDREGISTER(PER); /* Period */ 1878 _WORDREGISTER(CCA); /* Compare or Capture A */ 1879 _WORDREGISTER(CCB); /* Compare or Capture B */ 1880 register8_t reserved_0x2C; 1881 register8_t reserved_0x2D; 1882 register8_t reserved_0x2E; 1883 register8_t reserved_0x2F; 1884 register8_t reserved_0x30; 1885 register8_t reserved_0x31; 1886 register8_t reserved_0x32; 1887 register8_t reserved_0x33; 1888 register8_t reserved_0x34; 1889 register8_t reserved_0x35; 1890 _WORDREGISTER(PERBUF); /* Period Buffer */ 1891 _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ 1892 _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ 1893 } TC1_t; 1894 1895 /* 1896 -------------------------------------------------------------------------- 1897 TC - 16-bit Timer/Counter With PWM 1898 -------------------------------------------------------------------------- 1899 */ 1900 1901 /* Advanced Waveform Extension */ 1902 typedef struct AWEX_struct 1903 { 1904 register8_t CTRL; /* Control Register */ 1905 register8_t reserved_0x01; 1906 register8_t FDEMASK; /* Fault Detection Event Mask */ 1907 register8_t FDCTRL; /* Fault Detection Control Register */ 1908 register8_t STATUS; /* Status Register */ 1909 register8_t reserved_0x05; 1910 register8_t DTBOTH; /* Dead Time Both Sides */ 1911 register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ 1912 register8_t DTLS; /* Dead Time Low Side */ 1913 register8_t DTHS; /* Dead Time High Side */ 1914 register8_t DTLSBUF; /* Dead Time Low Side Buffer */ 1915 register8_t DTHSBUF; /* Dead Time High Side Buffer */ 1916 register8_t OUTOVEN; /* Output Override Enable */ 1917 } AWEX_t; 1918 1919 /* 1920 -------------------------------------------------------------------------- 1921 TC - 16-bit Timer/Counter With PWM 1922 -------------------------------------------------------------------------- 1923 */ 1924 1925 /* High-Resolution Extension */ 1926 typedef struct HIRES_struct 1927 { 1928 register8_t CTRLA; /* Control Register */ 1929 } HIRES_t; 1930 1931 /* Clock Selection */ 1932 typedef enum TC_CLKSEL_enum 1933 { 1934 TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ 1935 TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ 1936 TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ 1937 TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ 1938 TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ 1939 TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ 1940 TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ 1941 TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ 1942 TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ 1943 TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ 1944 TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ 1945 TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ 1946 TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ 1947 TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ 1948 TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ 1949 TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ 1950 } TC_CLKSEL_t; 1951 1952 /* Waveform Generation Mode */ 1953 typedef enum TC_WGMODE_enum 1954 { 1955 TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ 1956 TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ 1957 TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ 1958 TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ 1959 TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ 1960 TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ 1961 } TC_WGMODE_t; 1962 1963 /* Event Action */ 1964 typedef enum TC_EVACT_enum 1965 { 1966 TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ 1967 TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ 1968 TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ 1969 TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ 1970 TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ 1971 TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ 1972 TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture (typo in earlier header file) */ 1973 TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ 1974 } TC_EVACT_t; 1975 1976 /* Event Selection */ 1977 typedef enum TC_EVSEL_enum 1978 { 1979 TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 1980 TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ 1981 TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ 1982 TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ 1983 TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ 1984 TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ 1985 TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ 1986 TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ 1987 TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ 1988 } TC_EVSEL_t; 1989 1990 /* Error Interrupt Level */ 1991 typedef enum TC_ERRINTLVL_enum 1992 { 1993 TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 1994 TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ 1995 TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 1996 TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ 1997 } TC_ERRINTLVL_t; 1998 1999 /* Overflow Interrupt Level */ 2000 typedef enum TC_OVFINTLVL_enum 2001 { 2002 TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2003 TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ 2004 TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2005 TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ 2006 } TC_OVFINTLVL_t; 2007 2008 /* Compare or Capture D Interrupt Level */ 2009 typedef enum TC_CCDINTLVL_enum 2010 { 2011 TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ 2012 TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ 2013 TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ 2014 TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ 2015 } TC_CCDINTLVL_t; 2016 2017 /* Compare or Capture C Interrupt Level */ 2018 typedef enum TC_CCCINTLVL_enum 2019 { 2020 TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 2021 TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 2022 TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 2023 TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ 2024 } TC_CCCINTLVL_t; 2025 2026 /* Compare or Capture B Interrupt Level */ 2027 typedef enum TC_CCBINTLVL_enum 2028 { 2029 TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2030 TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ 2031 TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 2032 TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ 2033 } TC_CCBINTLVL_t; 2034 2035 /* Compare or Capture A Interrupt Level */ 2036 typedef enum TC_CCAINTLVL_enum 2037 { 2038 TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2039 TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ 2040 TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2041 TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ 2042 } TC_CCAINTLVL_t; 2043 2044 /* Timer/Counter Command */ 2045 typedef enum TC_CMD_enum 2046 { 2047 TC_CMD_NONE_gc = (0x00<<2), /* No Command */ 2048 TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ 2049 TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ 2050 TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ 2051 } TC_CMD_t; 2052 2053 /* Fault Detect Action */ 2054 typedef enum AWEX_FDACT_enum 2055 { 2056 AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ 2057 AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ 2058 AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ 2059 } AWEX_FDACT_t; 2060 2061 /* High Resolution Enable */ 2062 typedef enum HIRES_HREN_enum 2063 { 2064 HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ 2065 HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ 2066 HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ 2067 HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ 2068 } HIRES_HREN_t; 2069 2070 2071 /* 2072 -------------------------------------------------------------------------- 2073 USART - Universal Asynchronous Receiver-Transmitter 2074 -------------------------------------------------------------------------- 2075 */ 2076 2077 /* Universal Synchronous/Asynchronous Receiver/Transmitter */ 2078 typedef struct USART_struct 2079 { 2080 register8_t DATA; /* Data Register */ 2081 register8_t STATUS; /* Status Register */ 2082 register8_t reserved_0x02; 2083 register8_t CTRLA; /* Control Register A */ 2084 register8_t CTRLB; /* Control Register B */ 2085 register8_t CTRLC; /* Control Register C */ 2086 register8_t BAUDCTRLA; /* Baud Rate Control Register A */ 2087 register8_t BAUDCTRLB; /* Baud Rate Control Register B */ 2088 } USART_t; 2089 2090 /* Receive Complete Interrupt level */ 2091 typedef enum USART_RXCINTLVL_enum 2092 { 2093 USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ 2094 USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ 2095 USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ 2096 USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ 2097 } USART_RXCINTLVL_t; 2098 2099 /* Transmit Complete Interrupt level */ 2100 typedef enum USART_TXCINTLVL_enum 2101 { 2102 USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ 2103 USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ 2104 USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ 2105 USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ 2106 } USART_TXCINTLVL_t; 2107 2108 /* Data Register Empty Interrupt level */ 2109 typedef enum USART_DREINTLVL_enum 2110 { 2111 USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2112 USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ 2113 USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2114 USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ 2115 } USART_DREINTLVL_t; 2116 2117 /* Character Size */ 2118 typedef enum USART_CHSIZE_enum 2119 { 2120 USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ 2121 USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ 2122 USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ 2123 USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ 2124 USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ 2125 } USART_CHSIZE_t; 2126 2127 /* Communication Mode */ 2128 typedef enum USART_CMODE_enum 2129 { 2130 USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ 2131 USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ 2132 USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ 2133 USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ 2134 } USART_CMODE_t; 2135 2136 /* Parity Mode */ 2137 typedef enum USART_PMODE_enum 2138 { 2139 USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ 2140 USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ 2141 USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ 2142 } USART_PMODE_t; 2143 2144 2145 /* 2146 -------------------------------------------------------------------------- 2147 SPI - Serial Peripheral Interface 2148 -------------------------------------------------------------------------- 2149 */ 2150 2151 /* Serial Peripheral Interface */ 2152 typedef struct SPI_struct 2153 { 2154 register8_t CTRL; /* Control Register */ 2155 register8_t INTCTRL; /* Interrupt Control Register */ 2156 register8_t STATUS; /* Status Register */ 2157 register8_t DATA; /* Data Register */ 2158 } SPI_t; 2159 2160 /* SPI Mode */ 2161 typedef enum SPI_MODE_enum 2162 { 2163 SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ 2164 SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ 2165 SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ 2166 SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ 2167 } SPI_MODE_t; 2168 2169 /* Prescaler setting */ 2170 typedef enum SPI_PRESCALER_enum 2171 { 2172 SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ 2173 SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ 2174 SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ 2175 SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ 2176 } SPI_PRESCALER_t; 2177 2178 /* Interrupt level */ 2179 typedef enum SPI_INTLVL_enum 2180 { 2181 SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ 2182 SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ 2183 SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ 2184 SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ 2185 } SPI_INTLVL_t; 2186 2187 2188 /* 2189 -------------------------------------------------------------------------- 2190 IRCOM - IR Communication Module 2191 -------------------------------------------------------------------------- 2192 */ 2193 2194 /* IR Communication Module */ 2195 typedef struct IRCOM_struct 2196 { 2197 register8_t CTRL; /* Control Register */ 2198 register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ 2199 register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ 2200 } IRCOM_t; 2201 2202 /* Event channel selection */ 2203 typedef enum IRDA_EVSEL_enum 2204 { 2205 IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ 2206 IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ 2207 IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ 2208 IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ 2209 IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ 2210 IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ 2211 IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ 2212 IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ 2213 IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ 2214 } IRDA_EVSEL_t; 2215 2216 2217 2218 /* 2219 ========================================================================== 2220 IO Module Instances. Mapped to memory. 2221 ========================================================================== 2222 */ 2223 2224 #define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ 2225 #define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ 2226 #define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ 2227 #define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ 2228 #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ 2229 #define CLK (*(CLK_t *) 0x0040) /* Clock System */ 2230 #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ 2231 #define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ 2232 #define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ 2233 #define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ 2234 #define PR (*(PR_t *) 0x0070) /* Power Reduction */ 2235 #define RST (*(RST_t *) 0x0078) /* Reset Controller */ 2236 #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ 2237 #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ 2238 #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ 2239 #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ 2240 #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ 2241 #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ 2242 #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ 2243 #define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ 2244 #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ 2245 #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ 2246 #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ 2247 #define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ 2248 #define PORTA (*(PORT_t *) 0x0600) /* Port A */ 2249 #define PORTB (*(PORT_t *) 0x0620) /* Port B */ 2250 #define PORTC (*(PORT_t *) 0x0640) /* Port C */ 2251 #define PORTD (*(PORT_t *) 0x0660) /* Port D */ 2252 #define PORTE (*(PORT_t *) 0x0680) /* Port E */ 2253 #define PORTR (*(PORT_t *) 0x07E0) /* Port R */ 2254 #define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ 2255 #define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ 2256 #define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ 2257 #define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ 2258 #define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ 2259 #define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ 2260 #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ 2261 #define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ 2262 #define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ 2263 #define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ 2264 #define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ 2265 2266 2267 #endif /* !defined (__ASSEMBLER__) */ 2268 2269 2270 /* ========== Flattened fully qualified IO register names ========== */ 2271 2272 /* GPIO - General Purpose IO Registers */ 2273 #define GPIO_GPIO0 _SFR_MEM8(0x0000) 2274 #define GPIO_GPIO1 _SFR_MEM8(0x0001) 2275 #define GPIO_GPIO2 _SFR_MEM8(0x0002) 2276 #define GPIO_GPIO3 _SFR_MEM8(0x0003) 2277 #define GPIO_GPIO4 _SFR_MEM8(0x0004) 2278 #define GPIO_GPIO5 _SFR_MEM8(0x0005) 2279 #define GPIO_GPIO6 _SFR_MEM8(0x0006) 2280 #define GPIO_GPIO7 _SFR_MEM8(0x0007) 2281 #define GPIO_GPIO8 _SFR_MEM8(0x0008) 2282 #define GPIO_GPIO9 _SFR_MEM8(0x0009) 2283 #define GPIO_GPIOA _SFR_MEM8(0x000A) 2284 #define GPIO_GPIOB _SFR_MEM8(0x000B) 2285 #define GPIO_GPIOC _SFR_MEM8(0x000C) 2286 #define GPIO_GPIOD _SFR_MEM8(0x000D) 2287 #define GPIO_GPIOE _SFR_MEM8(0x000E) 2288 #define GPIO_GPIOF _SFR_MEM8(0x000F) 2289 2290 /* VPORT0 - Virtual Port 0 */ 2291 #define VPORT0_DIR _SFR_MEM8(0x0010) 2292 #define VPORT0_OUT _SFR_MEM8(0x0011) 2293 #define VPORT0_IN _SFR_MEM8(0x0012) 2294 #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) 2295 2296 /* VPORT1 - Virtual Port 1 */ 2297 #define VPORT1_DIR _SFR_MEM8(0x0014) 2298 #define VPORT1_OUT _SFR_MEM8(0x0015) 2299 #define VPORT1_IN _SFR_MEM8(0x0016) 2300 #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) 2301 2302 /* VPORT2 - Virtual Port 2 */ 2303 #define VPORT2_DIR _SFR_MEM8(0x0018) 2304 #define VPORT2_OUT _SFR_MEM8(0x0019) 2305 #define VPORT2_IN _SFR_MEM8(0x001A) 2306 #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) 2307 2308 /* VPORT3 - Virtual Port 3 */ 2309 #define VPORT3_DIR _SFR_MEM8(0x001C) 2310 #define VPORT3_OUT _SFR_MEM8(0x001D) 2311 #define VPORT3_IN _SFR_MEM8(0x001E) 2312 #define VPORT3_INTFLAGS _SFR_MEM8(0x001F) 2313 2314 /* OCD - On-Chip Debug System */ 2315 #define OCD_OCDR0 _SFR_MEM8(0x002E) 2316 #define OCD_OCDR1 _SFR_MEM8(0x002F) 2317 2318 /* CPU - CPU Registers */ 2319 #define CPU_CCP _SFR_MEM8(0x0034) 2320 #define CPU_RAMPD _SFR_MEM8(0x0038) 2321 #define CPU_RAMPX _SFR_MEM8(0x0039) 2322 #define CPU_RAMPY _SFR_MEM8(0x003A) 2323 #define CPU_RAMPZ _SFR_MEM8(0x003B) 2324 #define CPU_EIND _SFR_MEM8(0x003C) 2325 #define CPU_SPL _SFR_MEM8(0x003D) 2326 #define CPU_SPH _SFR_MEM8(0x003E) 2327 #define CPU_SREG _SFR_MEM8(0x003F) 2328 2329 /* CLK - Clock System */ 2330 #define CLK_CTRL _SFR_MEM8(0x0040) 2331 #define CLK_PSCTRL _SFR_MEM8(0x0041) 2332 #define CLK_LOCK _SFR_MEM8(0x0042) 2333 #define CLK_RTCCTRL _SFR_MEM8(0x0043) 2334 2335 /* SLEEP - Sleep Controller */ 2336 #define SLEEP_CTRL _SFR_MEM8(0x0048) 2337 2338 /* OSC - Oscillator Control */ 2339 #define OSC_CTRL _SFR_MEM8(0x0050) 2340 #define OSC_STATUS _SFR_MEM8(0x0051) 2341 #define OSC_XOSCCTRL _SFR_MEM8(0x0052) 2342 #define OSC_XOSCFAIL _SFR_MEM8(0x0053) 2343 #define OSC_RC32KCAL _SFR_MEM8(0x0054) 2344 #define OSC_PLLCTRL _SFR_MEM8(0x0055) 2345 #define OSC_DFLLCTRL _SFR_MEM8(0x0056) 2346 2347 /* DFLLRC32M - DFLL for 32MHz RC Oscillator */ 2348 #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) 2349 #define DFLLRC32M_CALA _SFR_MEM8(0x0062) 2350 #define DFLLRC32M_CALB _SFR_MEM8(0x0063) 2351 #define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) 2352 #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) 2353 #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) 2354 2355 /* DFLLRC2M - DFLL for 2MHz RC Oscillator */ 2356 #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) 2357 #define DFLLRC2M_CALA _SFR_MEM8(0x006A) 2358 #define DFLLRC2M_CALB _SFR_MEM8(0x006B) 2359 #define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) 2360 #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) 2361 #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) 2362 2363 /* PR - Power Reduction */ 2364 #define PR_PRGEN _SFR_MEM8(0x0070) 2365 #define PR_PRPA _SFR_MEM8(0x0071) 2366 #define PR_PRPB _SFR_MEM8(0x0072) 2367 #define PR_PRPC _SFR_MEM8(0x0073) 2368 #define PR_PRPD _SFR_MEM8(0x0074) 2369 #define PR_PRPE _SFR_MEM8(0x0075) 2370 #define PR_PRPF _SFR_MEM8(0x0076) 2371 2372 /* RST - Reset Controller */ 2373 #define RST_STATUS _SFR_MEM8(0x0078) 2374 #define RST_CTRL _SFR_MEM8(0x0079) 2375 2376 /* WDT - Watch-Dog Timer */ 2377 #define WDT_CTRL _SFR_MEM8(0x0080) 2378 #define WDT_WINCTRL _SFR_MEM8(0x0081) 2379 #define WDT_STATUS _SFR_MEM8(0x0082) 2380 2381 /* MCU - MCU Control */ 2382 #define MCU_DEVID0 _SFR_MEM8(0x0090) 2383 #define MCU_DEVID1 _SFR_MEM8(0x0091) 2384 #define MCU_DEVID2 _SFR_MEM8(0x0092) 2385 #define MCU_REVID _SFR_MEM8(0x0093) 2386 #define MCU_JTAGUID _SFR_MEM8(0x0094) 2387 #define MCU_MCUCR _SFR_MEM8(0x0096) 2388 #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) 2389 #define MCU_AWEXLOCK _SFR_MEM8(0x0099) 2390 2391 /* PMIC - Programmable Interrupt Controller */ 2392 #define PMIC_STATUS _SFR_MEM8(0x00A0) 2393 #define PMIC_INTPRI _SFR_MEM8(0x00A1) 2394 #define PMIC_CTRL _SFR_MEM8(0x00A2) 2395 2396 /* PORTCFG - Port Configuration */ 2397 #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) 2398 #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) 2399 #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) 2400 #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) 2401 2402 /* EVSYS - Event System */ 2403 #define EVSYS_CH0MUX _SFR_MEM8(0x0180) 2404 #define EVSYS_CH1MUX _SFR_MEM8(0x0181) 2405 #define EVSYS_CH2MUX _SFR_MEM8(0x0182) 2406 #define EVSYS_CH3MUX _SFR_MEM8(0x0183) 2407 #define EVSYS_CH0CTRL _SFR_MEM8(0x0188) 2408 #define EVSYS_CH1CTRL _SFR_MEM8(0x0189) 2409 #define EVSYS_CH2CTRL _SFR_MEM8(0x018A) 2410 #define EVSYS_CH3CTRL _SFR_MEM8(0x018B) 2411 #define EVSYS_STROBE _SFR_MEM8(0x0190) 2412 #define EVSYS_DATA _SFR_MEM8(0x0191) 2413 2414 /* NVM - Non Volatile Memory Controller */ 2415 #define NVM_ADDR0 _SFR_MEM8(0x01C0) 2416 #define NVM_ADDR1 _SFR_MEM8(0x01C1) 2417 #define NVM_ADDR2 _SFR_MEM8(0x01C2) 2418 #define NVM_DATA0 _SFR_MEM8(0x01C4) 2419 #define NVM_DATA1 _SFR_MEM8(0x01C5) 2420 #define NVM_DATA2 _SFR_MEM8(0x01C6) 2421 #define NVM_CMD _SFR_MEM8(0x01CA) 2422 #define NVM_CTRLA _SFR_MEM8(0x01CB) 2423 #define NVM_CTRLB _SFR_MEM8(0x01CC) 2424 #define NVM_INTCTRL _SFR_MEM8(0x01CD) 2425 #define NVM_STATUS _SFR_MEM8(0x01CF) 2426 #define NVM_LOCKBITS _SFR_MEM8(0x01D0) 2427 2428 /* ADCA - Analog to Digital Converter A */ 2429 #define ADCA_CTRLA _SFR_MEM8(0x0200) 2430 #define ADCA_CTRLB _SFR_MEM8(0x0201) 2431 #define ADCA_REFCTRL _SFR_MEM8(0x0202) 2432 #define ADCA_EVCTRL _SFR_MEM8(0x0203) 2433 #define ADCA_PRESCALER _SFR_MEM8(0x0204) 2434 #define ADCA_INTFLAGS _SFR_MEM8(0x0206) 2435 #define ADCA_CAL _SFR_MEM16(0x020C) 2436 #define ADCA_CH0RES _SFR_MEM16(0x0210) 2437 #define ADCA_CMP _SFR_MEM16(0x0218) 2438 #define ADCA_CH0_CTRL _SFR_MEM8(0x0220) 2439 #define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) 2440 #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) 2441 #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) 2442 #define ADCA_CH0_RES _SFR_MEM16(0x0224) 2443 2444 /* DACB - Digital to Analog Converter B */ 2445 2446 /* ACA - Analog Comparator A */ 2447 #define ACA_AC0CTRL _SFR_MEM8(0x0380) 2448 #define ACA_AC1CTRL _SFR_MEM8(0x0381) 2449 #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) 2450 #define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) 2451 #define ACA_CTRLA _SFR_MEM8(0x0384) 2452 #define ACA_CTRLB _SFR_MEM8(0x0385) 2453 #define ACA_WINCTRL _SFR_MEM8(0x0386) 2454 #define ACA_STATUS _SFR_MEM8(0x0387) 2455 2456 /* RTC - Real-Time Counter */ 2457 #define RTC_CTRL _SFR_MEM8(0x0400) 2458 #define RTC_STATUS _SFR_MEM8(0x0401) 2459 #define RTC_INTCTRL _SFR_MEM8(0x0402) 2460 #define RTC_INTFLAGS _SFR_MEM8(0x0403) 2461 #define RTC_TEMP _SFR_MEM8(0x0404) 2462 #define RTC_CNT _SFR_MEM16(0x0408) 2463 #define RTC_PER _SFR_MEM16(0x040A) 2464 #define RTC_COMP _SFR_MEM16(0x040C) 2465 2466 /* TWIC - Two-Wire Interface C */ 2467 #define TWIC_CTRL _SFR_MEM8(0x0480) 2468 #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) 2469 #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) 2470 #define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) 2471 #define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) 2472 #define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) 2473 #define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) 2474 #define TWIC_MASTER_DATA _SFR_MEM8(0x0487) 2475 #define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) 2476 #define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) 2477 #define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) 2478 #define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) 2479 #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) 2480 #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) 2481 2482 /* TWIE - Two-Wire Interface E */ 2483 #define TWIE_CTRL _SFR_MEM8(0x04A0) 2484 #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) 2485 #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) 2486 #define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) 2487 #define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) 2488 #define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) 2489 #define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) 2490 #define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) 2491 #define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) 2492 #define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) 2493 #define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) 2494 #define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) 2495 #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) 2496 #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) 2497 2498 2499 /* PORTA - Port A */ 2500 #define PORTA_DIR _SFR_MEM8(0x0600) 2501 #define PORTA_DIRSET _SFR_MEM8(0x0601) 2502 #define PORTA_DIRCLR _SFR_MEM8(0x0602) 2503 #define PORTA_DIRTGL _SFR_MEM8(0x0603) 2504 #define PORTA_OUT _SFR_MEM8(0x0604) 2505 #define PORTA_OUTSET _SFR_MEM8(0x0605) 2506 #define PORTA_OUTCLR _SFR_MEM8(0x0606) 2507 #define PORTA_OUTTGL _SFR_MEM8(0x0607) 2508 #define PORTA_IN _SFR_MEM8(0x0608) 2509 #define PORTA_INTCTRL _SFR_MEM8(0x0609) 2510 #define PORTA_INT0MASK _SFR_MEM8(0x060A) 2511 #define PORTA_INT1MASK _SFR_MEM8(0x060B) 2512 #define PORTA_INTFLAGS _SFR_MEM8(0x060C) 2513 #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) 2514 #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) 2515 #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) 2516 #define PORTA_PIN3CTRL _SFR_MEM8(0x0613) 2517 #define PORTA_PIN4CTRL _SFR_MEM8(0x0614) 2518 #define PORTA_PIN5CTRL _SFR_MEM8(0x0615) 2519 #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) 2520 #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) 2521 2522 /* PORTB - Port B */ 2523 #define PORTB_DIR _SFR_MEM8(0x0620) 2524 #define PORTB_DIRSET _SFR_MEM8(0x0621) 2525 #define PORTB_DIRCLR _SFR_MEM8(0x0622) 2526 #define PORTB_DIRTGL _SFR_MEM8(0x0623) 2527 #define PORTB_OUT _SFR_MEM8(0x0624) 2528 #define PORTB_OUTSET _SFR_MEM8(0x0625) 2529 #define PORTB_OUTCLR _SFR_MEM8(0x0626) 2530 #define PORTB_OUTTGL _SFR_MEM8(0x0627) 2531 #define PORTB_IN _SFR_MEM8(0x0628) 2532 #define PORTB_INTCTRL _SFR_MEM8(0x0629) 2533 #define PORTB_INT0MASK _SFR_MEM8(0x062A) 2534 #define PORTB_INT1MASK _SFR_MEM8(0x062B) 2535 #define PORTB_INTFLAGS _SFR_MEM8(0x062C) 2536 #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) 2537 #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) 2538 #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) 2539 #define PORTB_PIN3CTRL _SFR_MEM8(0x0633) 2540 #define PORTB_PIN4CTRL _SFR_MEM8(0x0634) 2541 #define PORTB_PIN5CTRL _SFR_MEM8(0x0635) 2542 #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) 2543 #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) 2544 2545 /* PORTC - Port C */ 2546 #define PORTC_DIR _SFR_MEM8(0x0640) 2547 #define PORTC_DIRSET _SFR_MEM8(0x0641) 2548 #define PORTC_DIRCLR _SFR_MEM8(0x0642) 2549 #define PORTC_DIRTGL _SFR_MEM8(0x0643) 2550 #define PORTC_OUT _SFR_MEM8(0x0644) 2551 #define PORTC_OUTSET _SFR_MEM8(0x0645) 2552 #define PORTC_OUTCLR _SFR_MEM8(0x0646) 2553 #define PORTC_OUTTGL _SFR_MEM8(0x0647) 2554 #define PORTC_IN _SFR_MEM8(0x0648) 2555 #define PORTC_INTCTRL _SFR_MEM8(0x0649) 2556 #define PORTC_INT0MASK _SFR_MEM8(0x064A) 2557 #define PORTC_INT1MASK _SFR_MEM8(0x064B) 2558 #define PORTC_INTFLAGS _SFR_MEM8(0x064C) 2559 #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) 2560 #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) 2561 #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) 2562 #define PORTC_PIN3CTRL _SFR_MEM8(0x0653) 2563 #define PORTC_PIN4CTRL _SFR_MEM8(0x0654) 2564 #define PORTC_PIN5CTRL _SFR_MEM8(0x0655) 2565 #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) 2566 #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) 2567 2568 /* PORTD - Port D */ 2569 #define PORTD_DIR _SFR_MEM8(0x0660) 2570 #define PORTD_DIRSET _SFR_MEM8(0x0661) 2571 #define PORTD_DIRCLR _SFR_MEM8(0x0662) 2572 #define PORTD_DIRTGL _SFR_MEM8(0x0663) 2573 #define PORTD_OUT _SFR_MEM8(0x0664) 2574 #define PORTD_OUTSET _SFR_MEM8(0x0665) 2575 #define PORTD_OUTCLR _SFR_MEM8(0x0666) 2576 #define PORTD_OUTTGL _SFR_MEM8(0x0667) 2577 #define PORTD_IN _SFR_MEM8(0x0668) 2578 #define PORTD_INTCTRL _SFR_MEM8(0x0669) 2579 #define PORTD_INT0MASK _SFR_MEM8(0x066A) 2580 #define PORTD_INT1MASK _SFR_MEM8(0x066B) 2581 #define PORTD_INTFLAGS _SFR_MEM8(0x066C) 2582 #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) 2583 #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) 2584 #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) 2585 #define PORTD_PIN3CTRL _SFR_MEM8(0x0673) 2586 #define PORTD_PIN4CTRL _SFR_MEM8(0x0674) 2587 #define PORTD_PIN5CTRL _SFR_MEM8(0x0675) 2588 #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) 2589 #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) 2590 2591 /* PORTE - Port E */ 2592 #define PORTE_DIR _SFR_MEM8(0x0680) 2593 #define PORTE_DIRSET _SFR_MEM8(0x0681) 2594 #define PORTE_DIRCLR _SFR_MEM8(0x0682) 2595 #define PORTE_DIRTGL _SFR_MEM8(0x0683) 2596 #define PORTE_OUT _SFR_MEM8(0x0684) 2597 #define PORTE_OUTSET _SFR_MEM8(0x0685) 2598 #define PORTE_OUTCLR _SFR_MEM8(0x0686) 2599 #define PORTE_OUTTGL _SFR_MEM8(0x0687) 2600 #define PORTE_IN _SFR_MEM8(0x0688) 2601 #define PORTE_INTCTRL _SFR_MEM8(0x0689) 2602 #define PORTE_INT0MASK _SFR_MEM8(0x068A) 2603 #define PORTE_INT1MASK _SFR_MEM8(0x068B) 2604 #define PORTE_INTFLAGS _SFR_MEM8(0x068C) 2605 #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) 2606 #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) 2607 #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) 2608 #define PORTE_PIN3CTRL _SFR_MEM8(0x0693) 2609 #define PORTE_PIN4CTRL _SFR_MEM8(0x0694) 2610 #define PORTE_PIN5CTRL _SFR_MEM8(0x0695) 2611 #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) 2612 #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) 2613 2614 /* PORTR - Port R */ 2615 #define PORTR_DIR _SFR_MEM8(0x07E0) 2616 #define PORTR_DIRSET _SFR_MEM8(0x07E1) 2617 #define PORTR_DIRCLR _SFR_MEM8(0x07E2) 2618 #define PORTR_DIRTGL _SFR_MEM8(0x07E3) 2619 #define PORTR_OUT _SFR_MEM8(0x07E4) 2620 #define PORTR_OUTSET _SFR_MEM8(0x07E5) 2621 #define PORTR_OUTCLR _SFR_MEM8(0x07E6) 2622 #define PORTR_OUTTGL _SFR_MEM8(0x07E7) 2623 #define PORTR_IN _SFR_MEM8(0x07E8) 2624 #define PORTR_INTCTRL _SFR_MEM8(0x07E9) 2625 #define PORTR_INT0MASK _SFR_MEM8(0x07EA) 2626 #define PORTR_INT1MASK _SFR_MEM8(0x07EB) 2627 #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) 2628 #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) 2629 #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) 2630 #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) 2631 #define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) 2632 #define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) 2633 #define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) 2634 #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) 2635 #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) 2636 2637 /* TCC0 - Timer/Counter C0 */ 2638 #define TCC0_CTRLA _SFR_MEM8(0x0800) 2639 #define TCC0_CTRLB _SFR_MEM8(0x0801) 2640 #define TCC0_CTRLC _SFR_MEM8(0x0802) 2641 #define TCC0_CTRLD _SFR_MEM8(0x0803) 2642 #define TCC0_CTRLE _SFR_MEM8(0x0804) 2643 #define TCC0_INTCTRLA _SFR_MEM8(0x0806) 2644 #define TCC0_INTCTRLB _SFR_MEM8(0x0807) 2645 #define TCC0_CTRLFCLR _SFR_MEM8(0x0808) 2646 #define TCC0_CTRLFSET _SFR_MEM8(0x0809) 2647 #define TCC0_CTRLGCLR _SFR_MEM8(0x080A) 2648 #define TCC0_CTRLGSET _SFR_MEM8(0x080B) 2649 #define TCC0_INTFLAGS _SFR_MEM8(0x080C) 2650 #define TCC0_TEMP _SFR_MEM8(0x080F) 2651 #define TCC0_CNT _SFR_MEM16(0x0820) 2652 #define TCC0_PER _SFR_MEM16(0x0826) 2653 #define TCC0_CCA _SFR_MEM16(0x0828) 2654 #define TCC0_CCB _SFR_MEM16(0x082A) 2655 #define TCC0_CCC _SFR_MEM16(0x082C) 2656 #define TCC0_CCD _SFR_MEM16(0x082E) 2657 #define TCC0_PERBUF _SFR_MEM16(0x0836) 2658 #define TCC0_CCABUF _SFR_MEM16(0x0838) 2659 #define TCC0_CCBBUF _SFR_MEM16(0x083A) 2660 #define TCC0_CCCBUF _SFR_MEM16(0x083C) 2661 #define TCC0_CCDBUF _SFR_MEM16(0x083E) 2662 2663 /* TCC1 - Timer/Counter C1 */ 2664 #define TCC1_CTRLA _SFR_MEM8(0x0840) 2665 #define TCC1_CTRLB _SFR_MEM8(0x0841) 2666 #define TCC1_CTRLC _SFR_MEM8(0x0842) 2667 #define TCC1_CTRLD _SFR_MEM8(0x0843) 2668 #define TCC1_CTRLE _SFR_MEM8(0x0844) 2669 #define TCC1_INTCTRLA _SFR_MEM8(0x0846) 2670 #define TCC1_INTCTRLB _SFR_MEM8(0x0847) 2671 #define TCC1_CTRLFCLR _SFR_MEM8(0x0848) 2672 #define TCC1_CTRLFSET _SFR_MEM8(0x0849) 2673 #define TCC1_CTRLGCLR _SFR_MEM8(0x084A) 2674 #define TCC1_CTRLGSET _SFR_MEM8(0x084B) 2675 #define TCC1_INTFLAGS _SFR_MEM8(0x084C) 2676 #define TCC1_TEMP _SFR_MEM8(0x084F) 2677 #define TCC1_CNT _SFR_MEM16(0x0860) 2678 #define TCC1_PER _SFR_MEM16(0x0866) 2679 #define TCC1_CCA _SFR_MEM16(0x0868) 2680 #define TCC1_CCB _SFR_MEM16(0x086A) 2681 #define TCC1_PERBUF _SFR_MEM16(0x0876) 2682 #define TCC1_CCABUF _SFR_MEM16(0x0878) 2683 #define TCC1_CCBBUF _SFR_MEM16(0x087A) 2684 2685 /* AWEXC - Advanced Waveform Extension C */ 2686 #define AWEXC_CTRL _SFR_MEM8(0x0880) 2687 #define AWEXC_FDEMASK _SFR_MEM8(0x0882) 2688 #define AWEXC_FDCTRL _SFR_MEM8(0x0883) 2689 #define AWEXC_STATUS _SFR_MEM8(0x0884) 2690 #define AWEXC_DTBOTH _SFR_MEM8(0x0886) 2691 #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) 2692 #define AWEXC_DTLS _SFR_MEM8(0x0888) 2693 #define AWEXC_DTHS _SFR_MEM8(0x0889) 2694 #define AWEXC_DTLSBUF _SFR_MEM8(0x088A) 2695 #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) 2696 #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) 2697 2698 /* HIRESC - High-Resolution Extension C */ 2699 #define HIRESC_CTRLA _SFR_MEM8(0x0890) 2700 2701 /* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ 2702 #define USARTC0_DATA _SFR_MEM8(0x08A0) 2703 #define USARTC0_STATUS _SFR_MEM8(0x08A1) 2704 #define USARTC0_CTRLA _SFR_MEM8(0x08A3) 2705 #define USARTC0_CTRLB _SFR_MEM8(0x08A4) 2706 #define USARTC0_CTRLC _SFR_MEM8(0x08A5) 2707 #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) 2708 #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) 2709 2710 /* SPIC - Serial Peripheral Interface C */ 2711 #define SPIC_CTRL _SFR_MEM8(0x08C0) 2712 #define SPIC_INTCTRL _SFR_MEM8(0x08C1) 2713 #define SPIC_STATUS _SFR_MEM8(0x08C2) 2714 #define SPIC_DATA _SFR_MEM8(0x08C3) 2715 2716 /* IRCOM - IR Communication Module */ 2717 #define IRCOM_CTRL _SFR_MEM8(0x08F8) 2718 #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) 2719 #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) 2720 2721 /* TCD0 - Timer/Counter D0 */ 2722 #define TCD0_CTRLA _SFR_MEM8(0x0900) 2723 #define TCD0_CTRLB _SFR_MEM8(0x0901) 2724 #define TCD0_CTRLC _SFR_MEM8(0x0902) 2725 #define TCD0_CTRLD _SFR_MEM8(0x0903) 2726 #define TCD0_CTRLE _SFR_MEM8(0x0904) 2727 #define TCD0_INTCTRLA _SFR_MEM8(0x0906) 2728 #define TCD0_INTCTRLB _SFR_MEM8(0x0907) 2729 #define TCD0_CTRLFCLR _SFR_MEM8(0x0908) 2730 #define TCD0_CTRLFSET _SFR_MEM8(0x0909) 2731 #define TCD0_CTRLGCLR _SFR_MEM8(0x090A) 2732 #define TCD0_CTRLGSET _SFR_MEM8(0x090B) 2733 #define TCD0_INTFLAGS _SFR_MEM8(0x090C) 2734 #define TCD0_TEMP _SFR_MEM8(0x090F) 2735 #define TCD0_CNT _SFR_MEM16(0x0920) 2736 #define TCD0_PER _SFR_MEM16(0x0926) 2737 #define TCD0_CCA _SFR_MEM16(0x0928) 2738 #define TCD0_CCB _SFR_MEM16(0x092A) 2739 #define TCD0_CCC _SFR_MEM16(0x092C) 2740 #define TCD0_CCD _SFR_MEM16(0x092E) 2741 #define TCD0_PERBUF _SFR_MEM16(0x0936) 2742 #define TCD0_CCABUF _SFR_MEM16(0x0938) 2743 #define TCD0_CCBBUF _SFR_MEM16(0x093A) 2744 #define TCD0_CCCBUF _SFR_MEM16(0x093C) 2745 #define TCD0_CCDBUF _SFR_MEM16(0x093E) 2746 2747 /* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ 2748 #define USARTD0_DATA _SFR_MEM8(0x09A0) 2749 #define USARTD0_STATUS _SFR_MEM8(0x09A1) 2750 #define USARTD0_CTRLA _SFR_MEM8(0x09A3) 2751 #define USARTD0_CTRLB _SFR_MEM8(0x09A4) 2752 #define USARTD0_CTRLC _SFR_MEM8(0x09A5) 2753 #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) 2754 #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) 2755 2756 /* SPID - Serial Peripheral Interface D */ 2757 #define SPID_CTRL _SFR_MEM8(0x09C0) 2758 #define SPID_INTCTRL _SFR_MEM8(0x09C1) 2759 #define SPID_STATUS _SFR_MEM8(0x09C2) 2760 #define SPID_DATA _SFR_MEM8(0x09C3) 2761 2762 /* TCE0 - Timer/Counter E0 */ 2763 #define TCE0_CTRLA _SFR_MEM8(0x0A00) 2764 #define TCE0_CTRLB _SFR_MEM8(0x0A01) 2765 #define TCE0_CTRLC _SFR_MEM8(0x0A02) 2766 #define TCE0_CTRLD _SFR_MEM8(0x0A03) 2767 #define TCE0_CTRLE _SFR_MEM8(0x0A04) 2768 #define TCE0_INTCTRLA _SFR_MEM8(0x0A06) 2769 #define TCE0_INTCTRLB _SFR_MEM8(0x0A07) 2770 #define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) 2771 #define TCE0_CTRLFSET _SFR_MEM8(0x0A09) 2772 #define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) 2773 #define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) 2774 #define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) 2775 #define TCE0_TEMP _SFR_MEM8(0x0A0F) 2776 #define TCE0_CNT _SFR_MEM16(0x0A20) 2777 #define TCE0_PER _SFR_MEM16(0x0A26) 2778 #define TCE0_CCA _SFR_MEM16(0x0A28) 2779 #define TCE0_CCB _SFR_MEM16(0x0A2A) 2780 #define TCE0_CCC _SFR_MEM16(0x0A2C) 2781 #define TCE0_CCD _SFR_MEM16(0x0A2E) 2782 #define TCE0_PERBUF _SFR_MEM16(0x0A36) 2783 #define TCE0_CCABUF _SFR_MEM16(0x0A38) 2784 #define TCE0_CCBBUF _SFR_MEM16(0x0A3A) 2785 #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) 2786 #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) 2787 2788 2789 2790 /*================== Bitfield Definitions ================== */ 2791 2792 /* XOCD - On-Chip Debug System */ 2793 /* OCD.OCDR1 bit masks and bit positions */ 2794 #define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ 2795 #define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ 2796 2797 2798 /* CPU - CPU */ 2799 /* CPU.CCP bit masks and bit positions */ 2800 #define CPU_CCP_gm 0xFF /* CCP signature group mask. */ 2801 #define CPU_CCP_gp 0 /* CCP signature group position. */ 2802 #define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ 2803 #define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ 2804 #define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ 2805 #define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ 2806 #define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ 2807 #define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ 2808 #define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ 2809 #define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ 2810 #define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ 2811 #define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ 2812 #define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ 2813 #define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ 2814 #define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ 2815 #define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ 2816 #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ 2817 #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ 2818 2819 2820 /* CPU.SREG bit masks and bit positions */ 2821 #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ 2822 #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ 2823 2824 #define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ 2825 #define CPU_T_bp 6 /* Transfer Bit bit position. */ 2826 2827 #define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ 2828 #define CPU_H_bp 5 /* Half Carry Flag bit position. */ 2829 2830 #define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ 2831 #define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ 2832 2833 #define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ 2834 #define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ 2835 2836 #define CPU_N_bm 0x04 /* Negative Flag bit mask. */ 2837 #define CPU_N_bp 2 /* Negative Flag bit position. */ 2838 2839 #define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ 2840 #define CPU_Z_bp 1 /* Zero Flag bit position. */ 2841 2842 #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ 2843 #define CPU_C_bp 0 /* Carry Flag bit position. */ 2844 2845 2846 /* CLK - Clock System */ 2847 /* CLK.CTRL bit masks and bit positions */ 2848 #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ 2849 #define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ 2850 #define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ 2851 #define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ 2852 #define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ 2853 #define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ 2854 #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ 2855 #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ 2856 2857 2858 /* CLK.PSCTRL bit masks and bit positions */ 2859 #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ 2860 #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ 2861 #define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ 2862 #define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ 2863 #define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ 2864 #define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ 2865 #define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ 2866 #define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ 2867 #define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ 2868 #define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ 2869 #define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ 2870 #define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ 2871 2872 #define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ 2873 #define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ 2874 #define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ 2875 #define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ 2876 #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ 2877 #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ 2878 2879 2880 /* CLK.LOCK bit masks and bit positions */ 2881 #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ 2882 #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ 2883 2884 2885 /* CLK.RTCCTRL bit masks and bit positions */ 2886 #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ 2887 #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ 2888 #define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ 2889 #define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ 2890 #define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ 2891 #define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ 2892 #define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ 2893 #define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ 2894 2895 #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ 2896 #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ 2897 2898 2899 /* PR.PRGEN bit masks and bit positions */ 2900 #define PR_AES_bm 0x10 /* AES bit mask. */ 2901 #define PR_AES_bp 4 /* AES bit position. */ 2902 2903 #define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ 2904 #define PR_EBI_bp 3 /* External Bus Interface bit position. */ 2905 2906 #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ 2907 #define PR_RTC_bp 2 /* Real-time Counter bit position. */ 2908 2909 #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ 2910 #define PR_EVSYS_bp 1 /* Event System bit position. */ 2911 2912 #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ 2913 #define PR_DMA_bp 0 /* DMA-Controller bit position. */ 2914 2915 2916 /* PR.PRPA bit masks and bit positions */ 2917 #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ 2918 #define PR_DAC_bp 2 /* Port A DAC bit position. */ 2919 2920 #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ 2921 #define PR_ADC_bp 1 /* Port A ADC bit position. */ 2922 2923 #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ 2924 #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ 2925 2926 2927 /* PR.PRPB bit masks and bit positions */ 2928 /* PR_DAC_bm Predefined. */ 2929 /* PR_DAC_bp Predefined. */ 2930 2931 /* PR_ADC_bm Predefined. */ 2932 /* PR_ADC_bp Predefined. */ 2933 2934 /* PR_AC_bm Predefined. */ 2935 /* PR_AC_bp Predefined. */ 2936 2937 2938 /* PR.PRPC bit masks and bit positions */ 2939 #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ 2940 #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ 2941 2942 #define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ 2943 #define PR_USART1_bp 5 /* Port C USART1 bit position. */ 2944 2945 #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ 2946 #define PR_USART0_bp 4 /* Port C USART0 bit position. */ 2947 2948 #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ 2949 #define PR_SPI_bp 3 /* Port C SPI bit position. */ 2950 2951 #define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ 2952 #define PR_HIRES_bp 2 /* Port C AWEX bit position. */ 2953 2954 #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ 2955 #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ 2956 2957 #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ 2958 #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ 2959 2960 2961 /* PR.PRPD bit masks and bit positions */ 2962 /* PR_TWI_bm Predefined. */ 2963 /* PR_TWI_bp Predefined. */ 2964 2965 /* PR_USART1_bm Predefined. */ 2966 /* PR_USART1_bp Predefined. */ 2967 2968 /* PR_USART0_bm Predefined. */ 2969 /* PR_USART0_bp Predefined. */ 2970 2971 /* PR_SPI_bm Predefined. */ 2972 /* PR_SPI_bp Predefined. */ 2973 2974 /* PR_HIRES_bm Predefined. */ 2975 /* PR_HIRES_bp Predefined. */ 2976 2977 /* PR_TC1_bm Predefined. */ 2978 /* PR_TC1_bp Predefined. */ 2979 2980 /* PR_TC0_bm Predefined. */ 2981 /* PR_TC0_bp Predefined. */ 2982 2983 2984 /* PR.PRPE bit masks and bit positions */ 2985 /* PR_TWI_bm Predefined. */ 2986 /* PR_TWI_bp Predefined. */ 2987 2988 /* PR_USART1_bm Predefined. */ 2989 /* PR_USART1_bp Predefined. */ 2990 2991 /* PR_USART0_bm Predefined. */ 2992 /* PR_USART0_bp Predefined. */ 2993 2994 /* PR_SPI_bm Predefined. */ 2995 /* PR_SPI_bp Predefined. */ 2996 2997 /* PR_HIRES_bm Predefined. */ 2998 /* PR_HIRES_bp Predefined. */ 2999 3000 /* PR_TC1_bm Predefined. */ 3001 /* PR_TC1_bp Predefined. */ 3002 3003 /* PR_TC0_bm Predefined. */ 3004 /* PR_TC0_bp Predefined. */ 3005 3006 3007 /* PR.PRPF bit masks and bit positions */ 3008 /* PR_TWI_bm Predefined. */ 3009 /* PR_TWI_bp Predefined. */ 3010 3011 /* PR_USART1_bm Predefined. */ 3012 /* PR_USART1_bp Predefined. */ 3013 3014 /* PR_USART0_bm Predefined. */ 3015 /* PR_USART0_bp Predefined. */ 3016 3017 /* PR_SPI_bm Predefined. */ 3018 /* PR_SPI_bp Predefined. */ 3019 3020 /* PR_HIRES_bm Predefined. */ 3021 /* PR_HIRES_bp Predefined. */ 3022 3023 /* PR_TC1_bm Predefined. */ 3024 /* PR_TC1_bp Predefined. */ 3025 3026 /* PR_TC0_bm Predefined. */ 3027 /* PR_TC0_bp Predefined. */ 3028 3029 3030 /* SLEEP - Sleep Controller */ 3031 /* SLEEP.CTRL bit masks and bit positions */ 3032 #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ 3033 #define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ 3034 #define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ 3035 #define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ 3036 #define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ 3037 #define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ 3038 #define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ 3039 #define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ 3040 3041 #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ 3042 #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ 3043 3044 3045 /* OSC - Oscillator */ 3046 /* OSC.CTRL bit masks and bit positions */ 3047 #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ 3048 #define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ 3049 3050 #define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ 3051 #define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ 3052 3053 #define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ 3054 #define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ 3055 3056 #define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ 3057 #define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ 3058 3059 #define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ 3060 #define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ 3061 3062 3063 /* OSC.STATUS bit masks and bit positions */ 3064 #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ 3065 #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ 3066 3067 #define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ 3068 #define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ 3069 3070 #define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ 3071 #define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ 3072 3073 #define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ 3074 #define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ 3075 3076 #define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ 3077 #define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ 3078 3079 3080 /* OSC.XOSCCTRL bit masks and bit positions */ 3081 #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ 3082 #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ 3083 #define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ 3084 #define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ 3085 #define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ 3086 #define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ 3087 3088 #define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ 3089 #define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ 3090 3091 #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ 3092 #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ 3093 #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ 3094 #define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ 3095 #define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ 3096 #define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ 3097 #define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ 3098 #define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ 3099 #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ 3100 #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ 3101 3102 3103 /* OSC.XOSCFAIL bit masks and bit positions */ 3104 #define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ 3105 #define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ 3106 3107 #define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ 3108 #define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ 3109 3110 3111 /* OSC.PLLCTRL bit masks and bit positions */ 3112 #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ 3113 #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ 3114 #define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ 3115 #define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ 3116 #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ 3117 #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ 3118 3119 #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ 3120 #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ 3121 #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ 3122 #define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ 3123 #define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ 3124 #define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ 3125 #define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ 3126 #define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ 3127 #define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ 3128 #define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ 3129 #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ 3130 #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ 3131 3132 3133 /* OSC.DFLLCTRL bit masks and bit positions */ 3134 #define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ 3135 #define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ 3136 3137 #define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ 3138 #define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ 3139 3140 3141 /* DFLL - DFLL */ 3142 /* DFLL.CTRL bit masks and bit positions */ 3143 #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ 3144 #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ 3145 3146 3147 /* DFLL.CALA bit masks and bit positions */ 3148 #define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ 3149 #define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ 3150 #define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ 3151 #define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ 3152 #define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ 3153 #define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ 3154 #define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ 3155 #define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ 3156 #define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ 3157 #define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ 3158 #define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ 3159 #define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ 3160 #define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ 3161 #define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ 3162 #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ 3163 #define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ 3164 3165 3166 /* DFLL.CALB bit masks and bit positions */ 3167 #define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ 3168 #define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ 3169 #define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ 3170 #define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ 3171 #define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ 3172 #define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ 3173 #define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ 3174 #define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ 3175 #define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ 3176 #define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ 3177 #define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ 3178 #define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ 3179 #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ 3180 #define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ 3181 3182 3183 /* RST - Reset */ 3184 /* RST.STATUS bit masks and bit positions */ 3185 #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ 3186 #define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ 3187 3188 #define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ 3189 #define RST_SRF_bp 5 /* Software Reset Flag bit position. */ 3190 3191 #define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ 3192 #define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ 3193 3194 #define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ 3195 #define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ 3196 3197 #define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ 3198 #define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ 3199 3200 #define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ 3201 #define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ 3202 3203 #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ 3204 #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ 3205 3206 3207 /* RST.CTRL bit masks and bit positions */ 3208 #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ 3209 #define RST_SWRST_bp 0 /* Software Reset bit position. */ 3210 3211 3212 /* WDT - Watch-Dog Timer */ 3213 /* WDT.CTRL bit masks and bit positions */ 3214 #define WDT_PER_gm 0x3C /* Period group mask. */ 3215 #define WDT_PER_gp 2 /* Period group position. */ 3216 #define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ 3217 #define WDT_PER0_bp 2 /* Period bit 0 position. */ 3218 #define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ 3219 #define WDT_PER1_bp 3 /* Period bit 1 position. */ 3220 #define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ 3221 #define WDT_PER2_bp 4 /* Period bit 2 position. */ 3222 #define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ 3223 #define WDT_PER3_bp 5 /* Period bit 3 position. */ 3224 3225 #define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ 3226 #define WDT_ENABLE_bp 1 /* Enable bit position. */ 3227 3228 #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ 3229 #define WDT_CEN_bp 0 /* Change Enable bit position. */ 3230 3231 3232 /* WDT.WINCTRL bit masks and bit positions */ 3233 #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ 3234 #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ 3235 #define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ 3236 #define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ 3237 #define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ 3238 #define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ 3239 #define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ 3240 #define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ 3241 #define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ 3242 #define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ 3243 3244 #define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ 3245 #define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ 3246 3247 #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ 3248 #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ 3249 3250 3251 /* WDT.STATUS bit masks and bit positions */ 3252 #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ 3253 #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ 3254 3255 3256 /* MCU - MCU Control */ 3257 /* MCU.MCUCR bit masks and bit positions */ 3258 #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ 3259 #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ 3260 3261 3262 /* MCU.EVSYSLOCK bit masks and bit positions */ 3263 #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ 3264 #define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ 3265 3266 #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ 3267 #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ 3268 3269 3270 /* MCU.AWEXLOCK bit masks and bit positions */ 3271 #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ 3272 #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ 3273 3274 #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ 3275 #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ 3276 3277 3278 /* PMIC - Programmable Multi-level Interrupt Controller */ 3279 /* PMIC.STATUS bit masks and bit positions */ 3280 #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ 3281 #define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ 3282 3283 #define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ 3284 #define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ 3285 3286 #define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ 3287 #define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ 3288 3289 #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ 3290 #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ 3291 3292 3293 /* PMIC.CTRL bit masks and bit positions */ 3294 #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ 3295 #define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ 3296 3297 #define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ 3298 #define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ 3299 3300 #define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ 3301 #define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ 3302 3303 #define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ 3304 #define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ 3305 3306 #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ 3307 #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ 3308 3309 3310 /* EVSYS - Event System */ 3311 /* EVSYS.CH0MUX bit masks and bit positions */ 3312 #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ 3313 #define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ 3314 #define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ 3315 #define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ 3316 #define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ 3317 #define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ 3318 #define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ 3319 #define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ 3320 #define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ 3321 #define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ 3322 #define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ 3323 #define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ 3324 #define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ 3325 #define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ 3326 #define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ 3327 #define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ 3328 #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ 3329 #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ 3330 3331 3332 /* EVSYS.CH1MUX bit masks and bit positions */ 3333 /* EVSYS_CHMUX_gm Predefined. */ 3334 /* EVSYS_CHMUX_gp Predefined. */ 3335 /* EVSYS_CHMUX0_bm Predefined. */ 3336 /* EVSYS_CHMUX0_bp Predefined. */ 3337 /* EVSYS_CHMUX1_bm Predefined. */ 3338 /* EVSYS_CHMUX1_bp Predefined. */ 3339 /* EVSYS_CHMUX2_bm Predefined. */ 3340 /* EVSYS_CHMUX2_bp Predefined. */ 3341 /* EVSYS_CHMUX3_bm Predefined. */ 3342 /* EVSYS_CHMUX3_bp Predefined. */ 3343 /* EVSYS_CHMUX4_bm Predefined. */ 3344 /* EVSYS_CHMUX4_bp Predefined. */ 3345 /* EVSYS_CHMUX5_bm Predefined. */ 3346 /* EVSYS_CHMUX5_bp Predefined. */ 3347 /* EVSYS_CHMUX6_bm Predefined. */ 3348 /* EVSYS_CHMUX6_bp Predefined. */ 3349 /* EVSYS_CHMUX7_bm Predefined. */ 3350 /* EVSYS_CHMUX7_bp Predefined. */ 3351 3352 3353 /* EVSYS.CH2MUX bit masks and bit positions */ 3354 /* EVSYS_CHMUX_gm Predefined. */ 3355 /* EVSYS_CHMUX_gp Predefined. */ 3356 /* EVSYS_CHMUX0_bm Predefined. */ 3357 /* EVSYS_CHMUX0_bp Predefined. */ 3358 /* EVSYS_CHMUX1_bm Predefined. */ 3359 /* EVSYS_CHMUX1_bp Predefined. */ 3360 /* EVSYS_CHMUX2_bm Predefined. */ 3361 /* EVSYS_CHMUX2_bp Predefined. */ 3362 /* EVSYS_CHMUX3_bm Predefined. */ 3363 /* EVSYS_CHMUX3_bp Predefined. */ 3364 /* EVSYS_CHMUX4_bm Predefined. */ 3365 /* EVSYS_CHMUX4_bp Predefined. */ 3366 /* EVSYS_CHMUX5_bm Predefined. */ 3367 /* EVSYS_CHMUX5_bp Predefined. */ 3368 /* EVSYS_CHMUX6_bm Predefined. */ 3369 /* EVSYS_CHMUX6_bp Predefined. */ 3370 /* EVSYS_CHMUX7_bm Predefined. */ 3371 /* EVSYS_CHMUX7_bp Predefined. */ 3372 3373 3374 /* EVSYS.CH3MUX bit masks and bit positions */ 3375 /* EVSYS_CHMUX_gm Predefined. */ 3376 /* EVSYS_CHMUX_gp Predefined. */ 3377 /* EVSYS_CHMUX0_bm Predefined. */ 3378 /* EVSYS_CHMUX0_bp Predefined. */ 3379 /* EVSYS_CHMUX1_bm Predefined. */ 3380 /* EVSYS_CHMUX1_bp Predefined. */ 3381 /* EVSYS_CHMUX2_bm Predefined. */ 3382 /* EVSYS_CHMUX2_bp Predefined. */ 3383 /* EVSYS_CHMUX3_bm Predefined. */ 3384 /* EVSYS_CHMUX3_bp Predefined. */ 3385 /* EVSYS_CHMUX4_bm Predefined. */ 3386 /* EVSYS_CHMUX4_bp Predefined. */ 3387 /* EVSYS_CHMUX5_bm Predefined. */ 3388 /* EVSYS_CHMUX5_bp Predefined. */ 3389 /* EVSYS_CHMUX6_bm Predefined. */ 3390 /* EVSYS_CHMUX6_bp Predefined. */ 3391 /* EVSYS_CHMUX7_bm Predefined. */ 3392 /* EVSYS_CHMUX7_bp Predefined. */ 3393 3394 3395 /* EVSYS.CH0CTRL bit masks and bit positions */ 3396 #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ 3397 #define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ 3398 #define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ 3399 #define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ 3400 #define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ 3401 #define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ 3402 3403 #define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ 3404 #define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ 3405 3406 #define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ 3407 #define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ 3408 3409 #define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ 3410 #define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ 3411 #define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ 3412 #define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ 3413 #define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ 3414 #define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ 3415 #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ 3416 #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ 3417 3418 3419 /* EVSYS.CH1CTRL bit masks and bit positions */ 3420 /* EVSYS_DIGFILT_gm Predefined. */ 3421 /* EVSYS_DIGFILT_gp Predefined. */ 3422 /* EVSYS_DIGFILT0_bm Predefined. */ 3423 /* EVSYS_DIGFILT0_bp Predefined. */ 3424 /* EVSYS_DIGFILT1_bm Predefined. */ 3425 /* EVSYS_DIGFILT1_bp Predefined. */ 3426 /* EVSYS_DIGFILT2_bm Predefined. */ 3427 /* EVSYS_DIGFILT2_bp Predefined. */ 3428 3429 3430 /* EVSYS.CH2CTRL bit masks and bit positions */ 3431 /* EVSYS_QDIRM_gm Predefined. */ 3432 /* EVSYS_QDIRM_gp Predefined. */ 3433 /* EVSYS_QDIRM0_bm Predefined. */ 3434 /* EVSYS_QDIRM0_bp Predefined. */ 3435 /* EVSYS_QDIRM1_bm Predefined. */ 3436 /* EVSYS_QDIRM1_bp Predefined. */ 3437 3438 /* EVSYS_QDIEN_bm Predefined. */ 3439 /* EVSYS_QDIEN_bp Predefined. */ 3440 3441 /* EVSYS_QDEN_bm Predefined. */ 3442 /* EVSYS_QDEN_bp Predefined. */ 3443 3444 /* EVSYS_DIGFILT_gm Predefined. */ 3445 /* EVSYS_DIGFILT_gp Predefined. */ 3446 /* EVSYS_DIGFILT0_bm Predefined. */ 3447 /* EVSYS_DIGFILT0_bp Predefined. */ 3448 /* EVSYS_DIGFILT1_bm Predefined. */ 3449 /* EVSYS_DIGFILT1_bp Predefined. */ 3450 /* EVSYS_DIGFILT2_bm Predefined. */ 3451 /* EVSYS_DIGFILT2_bp Predefined. */ 3452 3453 3454 /* EVSYS.CH3CTRL bit masks and bit positions */ 3455 /* EVSYS_DIGFILT_gm Predefined. */ 3456 /* EVSYS_DIGFILT_gp Predefined. */ 3457 /* EVSYS_DIGFILT0_bm Predefined. */ 3458 /* EVSYS_DIGFILT0_bp Predefined. */ 3459 /* EVSYS_DIGFILT1_bm Predefined. */ 3460 /* EVSYS_DIGFILT1_bp Predefined. */ 3461 /* EVSYS_DIGFILT2_bm Predefined. */ 3462 /* EVSYS_DIGFILT2_bp Predefined. */ 3463 3464 3465 /* NVM - Non Volatile Memory Controller */ 3466 /* NVM.CMD bit masks and bit positions */ 3467 #define NVM_CMD_gm 0xFF /* Command group mask. */ 3468 #define NVM_CMD_gp 0 /* Command group position. */ 3469 #define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ 3470 #define NVM_CMD0_bp 0 /* Command bit 0 position. */ 3471 #define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ 3472 #define NVM_CMD1_bp 1 /* Command bit 1 position. */ 3473 #define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ 3474 #define NVM_CMD2_bp 2 /* Command bit 2 position. */ 3475 #define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ 3476 #define NVM_CMD3_bp 3 /* Command bit 3 position. */ 3477 #define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ 3478 #define NVM_CMD4_bp 4 /* Command bit 4 position. */ 3479 #define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ 3480 #define NVM_CMD5_bp 5 /* Command bit 5 position. */ 3481 #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ 3482 #define NVM_CMD6_bp 6 /* Command bit 6 position. */ 3483 #define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ 3484 #define NVM_CMD7_bp 7 /* Command bit 7 position. */ 3485 3486 3487 /* NVM.CTRLA bit masks and bit positions */ 3488 #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ 3489 #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ 3490 3491 3492 /* NVM.CTRLB bit masks and bit positions */ 3493 #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ 3494 #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ 3495 3496 #define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ 3497 #define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ 3498 3499 #define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ 3500 #define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ 3501 3502 #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ 3503 #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ 3504 3505 3506 /* NVM.INTCTRL bit masks and bit positions */ 3507 #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ 3508 #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ 3509 #define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ 3510 #define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ 3511 #define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ 3512 #define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ 3513 3514 #define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ 3515 #define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ 3516 #define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ 3517 #define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ 3518 #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ 3519 #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ 3520 3521 3522 /* NVM.STATUS bit masks and bit positions */ 3523 #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ 3524 #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ 3525 3526 #define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ 3527 #define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ 3528 3529 #define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ 3530 #define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ 3531 3532 #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ 3533 #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ 3534 3535 3536 /* NVM.LOCKBITS bit masks and bit positions */ 3537 #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 3538 #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 3539 #define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 3540 #define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 3541 #define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 3542 #define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 3543 3544 #define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 3545 #define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 3546 #define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 3547 #define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 3548 #define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 3549 #define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 3550 3551 #define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 3552 #define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 3553 #define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 3554 #define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 3555 #define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 3556 #define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 3557 3558 #define NVM_LB_gm 0x03 /* Lock Bits group mask. */ 3559 #define NVM_LB_gp 0 /* Lock Bits group position. */ 3560 #define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 3561 #define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ 3562 #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 3563 #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ 3564 3565 3566 /* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ 3567 #define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ 3568 #define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ 3569 #define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ 3570 #define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ 3571 #define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ 3572 #define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ 3573 3574 #define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ 3575 #define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ 3576 #define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ 3577 #define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ 3578 #define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ 3579 #define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ 3580 3581 #define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ 3582 #define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ 3583 #define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ 3584 #define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ 3585 #define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ 3586 #define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ 3587 3588 #define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ 3589 #define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ 3590 #define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ 3591 #define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ 3592 #define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ 3593 #define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ 3594 3595 3596 /* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ 3597 #define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ 3598 #define NVM_FUSES_USERID_gp 0 /* User ID group position. */ 3599 #define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ 3600 #define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ 3601 #define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ 3602 #define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ 3603 #define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ 3604 #define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ 3605 #define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ 3606 #define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ 3607 #define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ 3608 #define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ 3609 #define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ 3610 #define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ 3611 #define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ 3612 #define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ 3613 #define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ 3614 #define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ 3615 3616 3617 /* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ 3618 #define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ 3619 #define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ 3620 #define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ 3621 #define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ 3622 #define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ 3623 #define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ 3624 #define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ 3625 #define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ 3626 #define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ 3627 #define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ 3628 3629 #define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ 3630 #define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ 3631 #define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ 3632 #define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ 3633 #define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ 3634 #define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ 3635 #define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ 3636 #define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ 3637 #define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ 3638 #define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ 3639 3640 3641 /* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ 3642 #define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ 3643 #define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ 3644 3645 #define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ 3646 #define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ 3647 3648 #define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ 3649 #define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ 3650 #define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ 3651 #define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ 3652 #define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ 3653 #define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ 3654 3655 3656 /* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ 3657 #define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ 3658 #define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ 3659 #define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ 3660 #define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ 3661 #define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ 3662 #define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ 3663 3664 #define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ 3665 #define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ 3666 3667 3668 /* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ 3669 #define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ 3670 #define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ 3671 #define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ 3672 #define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ 3673 #define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ 3674 #define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ 3675 3676 #define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ 3677 #define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ 3678 3679 #define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ 3680 #define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ 3681 #define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ 3682 #define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ 3683 #define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ 3684 #define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ 3685 #define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ 3686 #define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ 3687 3688 3689 /* AC - Analog Comparator */ 3690 /* AC.AC0CTRL bit masks and bit positions */ 3691 #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ 3692 #define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ 3693 #define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ 3694 #define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ 3695 #define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ 3696 #define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ 3697 3698 #define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ 3699 #define AC_INTLVL_gp 4 /* Interrupt Level group position. */ 3700 #define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ 3701 #define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ 3702 #define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ 3703 #define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ 3704 3705 #define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ 3706 #define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ 3707 3708 #define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ 3709 #define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ 3710 #define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ 3711 #define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ 3712 #define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ 3713 #define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ 3714 3715 #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ 3716 #define AC_ENABLE_bp 0 /* Enable bit position. */ 3717 3718 3719 /* AC.AC1CTRL bit masks and bit positions */ 3720 /* AC_INTMODE_gm Predefined. */ 3721 /* AC_INTMODE_gp Predefined. */ 3722 /* AC_INTMODE0_bm Predefined. */ 3723 /* AC_INTMODE0_bp Predefined. */ 3724 /* AC_INTMODE1_bm Predefined. */ 3725 /* AC_INTMODE1_bp Predefined. */ 3726 3727 /* AC_INTLVL_gm Predefined. */ 3728 /* AC_INTLVL_gp Predefined. */ 3729 /* AC_INTLVL0_bm Predefined. */ 3730 /* AC_INTLVL0_bp Predefined. */ 3731 /* AC_INTLVL1_bm Predefined. */ 3732 /* AC_INTLVL1_bp Predefined. */ 3733 3734 /* AC_HSMODE_bm Predefined. */ 3735 /* AC_HSMODE_bp Predefined. */ 3736 3737 /* AC_HYSMODE_gm Predefined. */ 3738 /* AC_HYSMODE_gp Predefined. */ 3739 /* AC_HYSMODE0_bm Predefined. */ 3740 /* AC_HYSMODE0_bp Predefined. */ 3741 /* AC_HYSMODE1_bm Predefined. */ 3742 /* AC_HYSMODE1_bp Predefined. */ 3743 3744 /* AC_ENABLE_bm Predefined. */ 3745 /* AC_ENABLE_bp Predefined. */ 3746 3747 3748 /* AC.AC0MUXCTRL bit masks and bit positions */ 3749 #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ 3750 #define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ 3751 #define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ 3752 #define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ 3753 #define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ 3754 #define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ 3755 #define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ 3756 #define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ 3757 3758 #define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ 3759 #define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ 3760 #define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ 3761 #define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ 3762 #define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ 3763 #define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ 3764 #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ 3765 #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ 3766 3767 3768 /* AC.AC1MUXCTRL bit masks and bit positions */ 3769 /* AC_MUXPOS_gm Predefined. */ 3770 /* AC_MUXPOS_gp Predefined. */ 3771 /* AC_MUXPOS0_bm Predefined. */ 3772 /* AC_MUXPOS0_bp Predefined. */ 3773 /* AC_MUXPOS1_bm Predefined. */ 3774 /* AC_MUXPOS1_bp Predefined. */ 3775 /* AC_MUXPOS2_bm Predefined. */ 3776 /* AC_MUXPOS2_bp Predefined. */ 3777 3778 /* AC_MUXNEG_gm Predefined. */ 3779 /* AC_MUXNEG_gp Predefined. */ 3780 /* AC_MUXNEG0_bm Predefined. */ 3781 /* AC_MUXNEG0_bp Predefined. */ 3782 /* AC_MUXNEG1_bm Predefined. */ 3783 /* AC_MUXNEG1_bp Predefined. */ 3784 /* AC_MUXNEG2_bm Predefined. */ 3785 /* AC_MUXNEG2_bp Predefined. */ 3786 3787 3788 /* AC.CTRLA bit masks and bit positions */ 3789 #define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ 3790 #define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ 3791 3792 3793 /* AC.CTRLB bit masks and bit positions */ 3794 #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ 3795 #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ 3796 #define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ 3797 #define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ 3798 #define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ 3799 #define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ 3800 #define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ 3801 #define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ 3802 #define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ 3803 #define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ 3804 #define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ 3805 #define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ 3806 #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ 3807 #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ 3808 3809 3810 /* AC.WINCTRL bit masks and bit positions */ 3811 #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ 3812 #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ 3813 3814 #define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ 3815 #define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ 3816 #define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ 3817 #define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ 3818 #define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ 3819 #define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ 3820 3821 #define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ 3822 #define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ 3823 #define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ 3824 #define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ 3825 #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ 3826 #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ 3827 3828 3829 /* AC.STATUS bit masks and bit positions */ 3830 #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ 3831 #define AC_WSTATE_gp 6 /* Window Mode State group position. */ 3832 #define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ 3833 #define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ 3834 #define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ 3835 #define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ 3836 3837 #define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ 3838 #define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ 3839 3840 #define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ 3841 #define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ 3842 3843 #define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ 3844 #define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ 3845 3846 #define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ 3847 #define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ 3848 3849 #define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ 3850 #define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ 3851 3852 3853 /* ADC - Analog/Digital Converter */ 3854 /* ADC_CH.CTRL bit masks and bit positions */ 3855 #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ 3856 #define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ 3857 3858 #define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ 3859 #define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ 3860 #define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ 3861 #define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ 3862 #define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ 3863 #define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ 3864 #define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ 3865 #define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ 3866 3867 #define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ 3868 #define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ 3869 #define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ 3870 #define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ 3871 #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ 3872 #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ 3873 3874 3875 /* ADC_CH.MUXCTRL bit masks and bit positions */ 3876 #define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ 3877 #define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ 3878 #define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ 3879 #define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ 3880 #define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ 3881 #define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ 3882 #define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ 3883 #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ 3884 #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ 3885 #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ 3886 #define ADC_CH_MUXPOS4_bm (1<<7) /* Positive Input Select bit 3 mask. */ 3887 #define ADC_CH_MUXPOS4_bp 7 /* Positive Input Select bit 3 position. */ 3888 3889 #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ 3890 #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ 3891 #define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ 3892 #define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ 3893 #define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ 3894 #define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ 3895 #define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ 3896 #define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ 3897 #define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ 3898 #define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ 3899 3900 #define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ 3901 #define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ 3902 #define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ 3903 #define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ 3904 #define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ 3905 #define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ 3906 3907 3908 /* ADC_CH.INTCTRL bit masks and bit positions */ 3909 #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ 3910 #define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ 3911 #define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ 3912 #define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ 3913 #define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ 3914 #define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ 3915 3916 #define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ 3917 #define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ 3918 #define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ 3919 #define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ 3920 #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ 3921 #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ 3922 3923 3924 /* ADC_CH.INTFLAGS bit masks and bit positions */ 3925 #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ 3926 #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ 3927 3928 3929 /* ADC.CTRLA bit masks and bit positions */ 3930 #define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ 3931 #define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ 3932 3933 #define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ 3934 #define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ 3935 3936 #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ 3937 #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ 3938 3939 3940 /* ADC.CTRLB bit masks and bit positions */ 3941 #define ADC_IMPMODE_bm 0x80 /* Impedance Mode bit mask. */ 3942 #define ADC_IMPMODE_bp 7 /* Impedance Mode bit position. */ 3943 3944 #define ADC_CURRENT_bm 0x60 /* Current bit mask. */ 3945 #define ADC_CURRENT1_bp 6 /* Current bit position. */ 3946 #define ADC_CURRENT0_bp 5 /* Current bit position. */ 3947 3948 #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ 3949 #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ 3950 3951 #define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ 3952 #define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ 3953 3954 #define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ 3955 #define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ 3956 #define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ 3957 #define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ 3958 #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ 3959 #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ 3960 3961 3962 /* ADC.REFCTRL bit masks and bit positions */ 3963 #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ 3964 #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ 3965 #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ 3966 #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ 3967 #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ 3968 #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ 3969 #define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ 3970 #define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ 3971 3972 #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ 3973 #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ 3974 3975 #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ 3976 #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ 3977 3978 3979 /* ADC.EVCTRL bit masks and bit positions */ 3980 #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ 3981 #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ 3982 #define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ 3983 #define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ 3984 #define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ 3985 #define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ 3986 3987 #define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ 3988 #define ADC_EVSEL_gp 3 /* Event Input Select group position. */ 3989 #define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ 3990 #define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ 3991 #define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ 3992 #define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ 3993 #define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ 3994 #define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ 3995 3996 #define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ 3997 #define ADC_EVACT_gp 0 /* Event Action Select group position. */ 3998 #define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ 3999 #define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ 4000 #define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ 4001 #define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ 4002 #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ 4003 #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ 4004 4005 4006 /* ADC.PRESCALER bit masks and bit positions */ 4007 #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ 4008 #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ 4009 #define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ 4010 #define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ 4011 #define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ 4012 #define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ 4013 #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ 4014 #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ 4015 4016 4017 /* ADC.INTFLAGS bit masks and bit positions */ 4018 #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ 4019 #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ 4020 4021 4022 /* RTC - Real-Time Clounter */ 4023 /* RTC.CTRL bit masks and bit positions */ 4024 #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ 4025 #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ 4026 #define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ 4027 #define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ 4028 #define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ 4029 #define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ 4030 #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ 4031 #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ 4032 4033 4034 /* RTC.STATUS bit masks and bit positions */ 4035 #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ 4036 #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ 4037 4038 4039 /* RTC.INTCTRL bit masks and bit positions */ 4040 #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ 4041 #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ 4042 #define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ 4043 #define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ 4044 #define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ 4045 #define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ 4046 4047 #define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ 4048 #define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ 4049 #define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ 4050 #define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ 4051 #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ 4052 #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ 4053 4054 4055 /* RTC.INTFLAGS bit masks and bit positions */ 4056 #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ 4057 #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ 4058 4059 #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 4060 #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 4061 4062 4063 /* EBI - External Bus Interface */ 4064 /* EBI_CS.CTRLA bit masks and bit positions */ 4065 #define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ 4066 #define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ 4067 #define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ 4068 #define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ 4069 #define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ 4070 #define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ 4071 #define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ 4072 #define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ 4073 #define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ 4074 #define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ 4075 #define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ 4076 #define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ 4077 4078 #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ 4079 #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ 4080 #define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ 4081 #define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ 4082 #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ 4083 #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ 4084 4085 4086 /* EBI_CS.CTRLB bit masks and bit positions */ 4087 #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ 4088 #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ 4089 #define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ 4090 #define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ 4091 #define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ 4092 #define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ 4093 #define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ 4094 #define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ 4095 4096 #define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ 4097 #define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ 4098 4099 #define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ 4100 #define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ 4101 4102 #define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ 4103 #define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ 4104 #define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ 4105 #define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ 4106 #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ 4107 #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ 4108 4109 4110 /* EBI.CTRL bit masks and bit positions */ 4111 #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ 4112 #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ 4113 #define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ 4114 #define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ 4115 #define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ 4116 #define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ 4117 4118 #define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ 4119 #define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ 4120 #define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ 4121 #define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ 4122 #define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ 4123 #define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ 4124 4125 #define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ 4126 #define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ 4127 #define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ 4128 #define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ 4129 #define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ 4130 #define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ 4131 4132 #define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ 4133 #define EBI_IFMODE_gp 0 /* Interface Mode group position. */ 4134 #define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ 4135 #define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ 4136 #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ 4137 #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ 4138 4139 4140 /* EBI.SDRAMCTRLA bit masks and bit positions */ 4141 #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ 4142 #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ 4143 4144 #define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ 4145 #define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ 4146 4147 #define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ 4148 #define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ 4149 #define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ 4150 #define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ 4151 #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ 4152 #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ 4153 4154 4155 /* EBI.SDRAMCTRLB bit masks and bit positions */ 4156 #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ 4157 #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ 4158 #define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ 4159 #define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ 4160 #define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ 4161 #define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ 4162 4163 #define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ 4164 #define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ 4165 #define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ 4166 #define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ 4167 #define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ 4168 #define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ 4169 #define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ 4170 #define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ 4171 4172 #define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ 4173 #define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ 4174 #define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ 4175 #define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ 4176 #define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ 4177 #define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ 4178 #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ 4179 #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ 4180 4181 4182 /* EBI.SDRAMCTRLC bit masks and bit positions */ 4183 #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ 4184 #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ 4185 #define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ 4186 #define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ 4187 #define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ 4188 #define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ 4189 4190 #define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ 4191 #define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ 4192 #define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ 4193 #define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ 4194 #define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ 4195 #define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ 4196 #define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ 4197 #define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ 4198 4199 #define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ 4200 #define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ 4201 #define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ 4202 #define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ 4203 #define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ 4204 #define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ 4205 #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ 4206 #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ 4207 4208 4209 /* TWI - Two-Wire Interface */ 4210 /* TWI_MASTER.CTRLA bit masks and bit positions */ 4211 #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 4212 #define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ 4213 #define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 4214 #define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 4215 #define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 4216 #define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 4217 4218 #define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ 4219 #define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ 4220 4221 #define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ 4222 #define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ 4223 4224 #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ 4225 #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ 4226 4227 4228 /* TWI_MASTER.CTRLB bit masks and bit positions */ 4229 #define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ 4230 #define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ 4231 #define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ 4232 #define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ 4233 #define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ 4234 #define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ 4235 4236 #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ 4237 #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ 4238 4239 #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 4240 #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ 4241 4242 4243 /* TWI_MASTER.CTRLC bit masks and bit positions */ 4244 #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 4245 #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ 4246 4247 #define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ 4248 #define TWI_MASTER_CMD_gp 0 /* Command group position. */ 4249 #define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ 4250 #define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ 4251 #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ 4252 #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ 4253 4254 4255 /* TWI_MASTER.STATUS bit masks and bit positions */ 4256 #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ 4257 #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ 4258 4259 #define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ 4260 #define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ 4261 4262 #define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 4263 #define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ 4264 4265 #define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 4266 #define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ 4267 4268 #define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ 4269 #define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ 4270 4271 #define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ 4272 #define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ 4273 4274 #define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ 4275 #define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ 4276 #define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ 4277 #define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ 4278 #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ 4279 #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ 4280 4281 4282 /* TWI_SLAVE.CTRLA bit masks and bit positions */ 4283 #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ 4284 #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ 4285 #define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ 4286 #define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ 4287 #define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ 4288 #define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ 4289 4290 #define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ 4291 #define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ 4292 4293 #define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ 4294 #define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ 4295 4296 #define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ 4297 #define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ 4298 4299 #define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ 4300 #define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ 4301 4302 #define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ 4303 #define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ 4304 4305 #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ 4306 #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ 4307 4308 4309 /* TWI_SLAVE.CTRLB bit masks and bit positions */ 4310 #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ 4311 #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ 4312 4313 #define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ 4314 #define TWI_SLAVE_CMD_gp 0 /* Command group position. */ 4315 #define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ 4316 #define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ 4317 #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ 4318 #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ 4319 4320 4321 /* TWI_SLAVE.STATUS bit masks and bit positions */ 4322 #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ 4323 #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ 4324 4325 #define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ 4326 #define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ 4327 4328 #define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ 4329 #define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ 4330 4331 #define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ 4332 #define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ 4333 4334 #define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ 4335 #define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ 4336 4337 #define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ 4338 #define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ 4339 4340 #define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ 4341 #define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ 4342 4343 #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ 4344 #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ 4345 4346 4347 /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ 4348 #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ 4349 #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ 4350 #define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ 4351 #define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ 4352 #define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ 4353 #define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ 4354 #define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ 4355 #define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ 4356 #define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ 4357 #define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ 4358 #define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ 4359 #define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ 4360 #define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ 4361 #define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ 4362 #define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ 4363 #define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ 4364 4365 #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ 4366 #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ 4367 4368 4369 /* TWI.CTRL bit masks and bit positions */ 4370 #define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ 4371 #define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ 4372 4373 #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ 4374 #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ 4375 4376 4377 /* PORT - Port Configuration */ 4378 /* PORTCFG.VPCTRLA bit masks and bit positions */ 4379 #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ 4380 #define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ 4381 #define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ 4382 #define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ 4383 #define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ 4384 #define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ 4385 #define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ 4386 #define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ 4387 #define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ 4388 #define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ 4389 4390 #define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ 4391 #define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ 4392 #define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ 4393 #define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ 4394 #define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ 4395 #define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ 4396 #define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ 4397 #define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ 4398 #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ 4399 #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ 4400 4401 4402 /* PORTCFG.VPCTRLB bit masks and bit positions */ 4403 #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ 4404 #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ 4405 #define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ 4406 #define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ 4407 #define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ 4408 #define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ 4409 #define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ 4410 #define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ 4411 #define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ 4412 #define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ 4413 4414 #define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ 4415 #define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ 4416 #define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ 4417 #define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ 4418 #define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ 4419 #define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ 4420 #define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ 4421 #define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ 4422 #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ 4423 #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ 4424 4425 4426 /* PORTCFG.CLKEVOUT bit masks and bit positions */ 4427 #define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ 4428 #define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ 4429 #define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ 4430 #define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ 4431 #define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ 4432 #define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ 4433 4434 #define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ 4435 #define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ 4436 #define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ 4437 #define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ 4438 #define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ 4439 #define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ 4440 4441 4442 /* VPORT.INTFLAGS bit masks and bit positions */ 4443 #define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 4444 #define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 4445 4446 #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 4447 #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 4448 4449 4450 /* PORT.INTCTRL bit masks and bit positions */ 4451 #define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ 4452 #define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ 4453 #define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ 4454 #define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ 4455 #define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ 4456 #define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ 4457 4458 #define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ 4459 #define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ 4460 #define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ 4461 #define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ 4462 #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ 4463 #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ 4464 4465 4466 /* PORT.INTFLAGS bit masks and bit positions */ 4467 #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ 4468 #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ 4469 4470 #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ 4471 #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ 4472 4473 4474 /* PORT.PIN0CTRL bit masks and bit positions */ 4475 #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ 4476 #define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ 4477 4478 #define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ 4479 #define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ 4480 4481 #define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ 4482 #define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ 4483 #define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ 4484 #define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ 4485 #define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ 4486 #define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ 4487 #define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ 4488 #define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ 4489 4490 #define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ 4491 #define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ 4492 #define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ 4493 #define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ 4494 #define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ 4495 #define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ 4496 #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ 4497 #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ 4498 4499 4500 /* PORT.PIN1CTRL bit masks and bit positions */ 4501 /* PORT_SRLEN_bm Predefined. */ 4502 /* PORT_SRLEN_bp Predefined. */ 4503 4504 /* PORT_INVEN_bm Predefined. */ 4505 /* PORT_INVEN_bp Predefined. */ 4506 4507 /* PORT_OPC_gm Predefined. */ 4508 /* PORT_OPC_gp Predefined. */ 4509 /* PORT_OPC0_bm Predefined. */ 4510 /* PORT_OPC0_bp Predefined. */ 4511 /* PORT_OPC1_bm Predefined. */ 4512 /* PORT_OPC1_bp Predefined. */ 4513 /* PORT_OPC2_bm Predefined. */ 4514 /* PORT_OPC2_bp Predefined. */ 4515 4516 /* PORT_ISC_gm Predefined. */ 4517 /* PORT_ISC_gp Predefined. */ 4518 /* PORT_ISC0_bm Predefined. */ 4519 /* PORT_ISC0_bp Predefined. */ 4520 /* PORT_ISC1_bm Predefined. */ 4521 /* PORT_ISC1_bp Predefined. */ 4522 /* PORT_ISC2_bm Predefined. */ 4523 /* PORT_ISC2_bp Predefined. */ 4524 4525 4526 /* PORT.PIN2CTRL bit masks and bit positions */ 4527 /* PORT_SRLEN_bm Predefined. */ 4528 /* PORT_SRLEN_bp Predefined. */ 4529 4530 /* PORT_INVEN_bm Predefined. */ 4531 /* PORT_INVEN_bp Predefined. */ 4532 4533 /* PORT_OPC_gm Predefined. */ 4534 /* PORT_OPC_gp Predefined. */ 4535 /* PORT_OPC0_bm Predefined. */ 4536 /* PORT_OPC0_bp Predefined. */ 4537 /* PORT_OPC1_bm Predefined. */ 4538 /* PORT_OPC1_bp Predefined. */ 4539 /* PORT_OPC2_bm Predefined. */ 4540 /* PORT_OPC2_bp Predefined. */ 4541 4542 /* PORT_ISC_gm Predefined. */ 4543 /* PORT_ISC_gp Predefined. */ 4544 /* PORT_ISC0_bm Predefined. */ 4545 /* PORT_ISC0_bp Predefined. */ 4546 /* PORT_ISC1_bm Predefined. */ 4547 /* PORT_ISC1_bp Predefined. */ 4548 /* PORT_ISC2_bm Predefined. */ 4549 /* PORT_ISC2_bp Predefined. */ 4550 4551 4552 /* PORT.PIN3CTRL bit masks and bit positions */ 4553 /* PORT_SRLEN_bm Predefined. */ 4554 /* PORT_SRLEN_bp Predefined. */ 4555 4556 /* PORT_INVEN_bm Predefined. */ 4557 /* PORT_INVEN_bp Predefined. */ 4558 4559 /* PORT_OPC_gm Predefined. */ 4560 /* PORT_OPC_gp Predefined. */ 4561 /* PORT_OPC0_bm Predefined. */ 4562 /* PORT_OPC0_bp Predefined. */ 4563 /* PORT_OPC1_bm Predefined. */ 4564 /* PORT_OPC1_bp Predefined. */ 4565 /* PORT_OPC2_bm Predefined. */ 4566 /* PORT_OPC2_bp Predefined. */ 4567 4568 /* PORT_ISC_gm Predefined. */ 4569 /* PORT_ISC_gp Predefined. */ 4570 /* PORT_ISC0_bm Predefined. */ 4571 /* PORT_ISC0_bp Predefined. */ 4572 /* PORT_ISC1_bm Predefined. */ 4573 /* PORT_ISC1_bp Predefined. */ 4574 /* PORT_ISC2_bm Predefined. */ 4575 /* PORT_ISC2_bp Predefined. */ 4576 4577 4578 /* PORT.PIN4CTRL bit masks and bit positions */ 4579 /* PORT_SRLEN_bm Predefined. */ 4580 /* PORT_SRLEN_bp Predefined. */ 4581 4582 /* PORT_INVEN_bm Predefined. */ 4583 /* PORT_INVEN_bp Predefined. */ 4584 4585 /* PORT_OPC_gm Predefined. */ 4586 /* PORT_OPC_gp Predefined. */ 4587 /* PORT_OPC0_bm Predefined. */ 4588 /* PORT_OPC0_bp Predefined. */ 4589 /* PORT_OPC1_bm Predefined. */ 4590 /* PORT_OPC1_bp Predefined. */ 4591 /* PORT_OPC2_bm Predefined. */ 4592 /* PORT_OPC2_bp Predefined. */ 4593 4594 /* PORT_ISC_gm Predefined. */ 4595 /* PORT_ISC_gp Predefined. */ 4596 /* PORT_ISC0_bm Predefined. */ 4597 /* PORT_ISC0_bp Predefined. */ 4598 /* PORT_ISC1_bm Predefined. */ 4599 /* PORT_ISC1_bp Predefined. */ 4600 /* PORT_ISC2_bm Predefined. */ 4601 /* PORT_ISC2_bp Predefined. */ 4602 4603 4604 /* PORT.PIN5CTRL bit masks and bit positions */ 4605 /* PORT_SRLEN_bm Predefined. */ 4606 /* PORT_SRLEN_bp Predefined. */ 4607 4608 /* PORT_INVEN_bm Predefined. */ 4609 /* PORT_INVEN_bp Predefined. */ 4610 4611 /* PORT_OPC_gm Predefined. */ 4612 /* PORT_OPC_gp Predefined. */ 4613 /* PORT_OPC0_bm Predefined. */ 4614 /* PORT_OPC0_bp Predefined. */ 4615 /* PORT_OPC1_bm Predefined. */ 4616 /* PORT_OPC1_bp Predefined. */ 4617 /* PORT_OPC2_bm Predefined. */ 4618 /* PORT_OPC2_bp Predefined. */ 4619 4620 /* PORT_ISC_gm Predefined. */ 4621 /* PORT_ISC_gp Predefined. */ 4622 /* PORT_ISC0_bm Predefined. */ 4623 /* PORT_ISC0_bp Predefined. */ 4624 /* PORT_ISC1_bm Predefined. */ 4625 /* PORT_ISC1_bp Predefined. */ 4626 /* PORT_ISC2_bm Predefined. */ 4627 /* PORT_ISC2_bp Predefined. */ 4628 4629 4630 /* PORT.PIN6CTRL bit masks and bit positions */ 4631 /* PORT_SRLEN_bm Predefined. */ 4632 /* PORT_SRLEN_bp Predefined. */ 4633 4634 /* PORT_INVEN_bm Predefined. */ 4635 /* PORT_INVEN_bp Predefined. */ 4636 4637 /* PORT_OPC_gm Predefined. */ 4638 /* PORT_OPC_gp Predefined. */ 4639 /* PORT_OPC0_bm Predefined. */ 4640 /* PORT_OPC0_bp Predefined. */ 4641 /* PORT_OPC1_bm Predefined. */ 4642 /* PORT_OPC1_bp Predefined. */ 4643 /* PORT_OPC2_bm Predefined. */ 4644 /* PORT_OPC2_bp Predefined. */ 4645 4646 /* PORT_ISC_gm Predefined. */ 4647 /* PORT_ISC_gp Predefined. */ 4648 /* PORT_ISC0_bm Predefined. */ 4649 /* PORT_ISC0_bp Predefined. */ 4650 /* PORT_ISC1_bm Predefined. */ 4651 /* PORT_ISC1_bp Predefined. */ 4652 /* PORT_ISC2_bm Predefined. */ 4653 /* PORT_ISC2_bp Predefined. */ 4654 4655 4656 /* PORT.PIN7CTRL bit masks and bit positions */ 4657 /* PORT_SRLEN_bm Predefined. */ 4658 /* PORT_SRLEN_bp Predefined. */ 4659 4660 /* PORT_INVEN_bm Predefined. */ 4661 /* PORT_INVEN_bp Predefined. */ 4662 4663 /* PORT_OPC_gm Predefined. */ 4664 /* PORT_OPC_gp Predefined. */ 4665 /* PORT_OPC0_bm Predefined. */ 4666 /* PORT_OPC0_bp Predefined. */ 4667 /* PORT_OPC1_bm Predefined. */ 4668 /* PORT_OPC1_bp Predefined. */ 4669 /* PORT_OPC2_bm Predefined. */ 4670 /* PORT_OPC2_bp Predefined. */ 4671 4672 /* PORT_ISC_gm Predefined. */ 4673 /* PORT_ISC_gp Predefined. */ 4674 /* PORT_ISC0_bm Predefined. */ 4675 /* PORT_ISC0_bp Predefined. */ 4676 /* PORT_ISC1_bm Predefined. */ 4677 /* PORT_ISC1_bp Predefined. */ 4678 /* PORT_ISC2_bm Predefined. */ 4679 /* PORT_ISC2_bp Predefined. */ 4680 4681 4682 /* TC - 16-bit Timer/Counter With PWM */ 4683 /* TC0.CTRLA bit masks and bit positions */ 4684 #define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 4685 #define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ 4686 #define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 4687 #define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 4688 #define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 4689 #define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 4690 #define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 4691 #define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 4692 #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 4693 #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 4694 4695 4696 /* TC0.CTRLB bit masks and bit positions */ 4697 #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ 4698 #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ 4699 4700 #define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ 4701 #define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ 4702 4703 #define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 4704 #define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 4705 4706 #define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 4707 #define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 4708 4709 #define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 4710 #define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ 4711 #define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 4712 #define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 4713 #define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 4714 #define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 4715 #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 4716 #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 4717 4718 4719 /* TC0.CTRLC bit masks and bit positions */ 4720 #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ 4721 #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ 4722 4723 #define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ 4724 #define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ 4725 4726 #define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 4727 #define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ 4728 4729 #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 4730 #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ 4731 4732 4733 /* TC0.CTRLD bit masks and bit positions */ 4734 #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ 4735 #define TC0_EVACT_gp 5 /* Event Action group position. */ 4736 #define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 4737 #define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ 4738 #define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 4739 #define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ 4740 #define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 4741 #define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ 4742 4743 #define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ 4744 #define TC0_EVDLY_bp 4 /* Event Delay bit position. */ 4745 4746 #define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ 4747 #define TC0_EVSEL_gp 0 /* Event Source Select group position. */ 4748 #define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 4749 #define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 4750 #define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 4751 #define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 4752 #define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 4753 #define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 4754 #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 4755 #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 4756 4757 4758 /* TC0.CTRLE bit masks and bit positions */ 4759 #define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ 4760 #define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ 4761 4762 #define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ 4763 #define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ 4764 4765 4766 /* TC0.INTCTRLA bit masks and bit positions */ 4767 #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 4768 #define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 4769 #define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 4770 #define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 4771 #define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 4772 #define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 4773 4774 #define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 4775 #define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 4776 #define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 4777 #define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 4778 #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 4779 #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 4780 4781 4782 /* TC0.INTCTRLB bit masks and bit positions */ 4783 #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ 4784 #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ 4785 #define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ 4786 #define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ 4787 #define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ 4788 #define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ 4789 4790 #define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ 4791 #define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ 4792 #define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ 4793 #define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ 4794 #define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ 4795 #define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ 4796 4797 #define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 4798 #define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 4799 #define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 4800 #define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 4801 #define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 4802 #define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 4803 4804 #define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 4805 #define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 4806 #define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 4807 #define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 4808 #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 4809 #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 4810 4811 4812 /* TC0.CTRLFCLR bit masks and bit positions */ 4813 #define TC0_CMD_gm 0x0C /* Command group mask. */ 4814 #define TC0_CMD_gp 2 /* Command group position. */ 4815 #define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ 4816 #define TC0_CMD0_bp 2 /* Command bit 0 position. */ 4817 #define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ 4818 #define TC0_CMD1_bp 3 /* Command bit 1 position. */ 4819 4820 #define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ 4821 #define TC0_LUPD_bp 1 /* Lock Update bit position. */ 4822 4823 #define TC0_DIR_bm 0x01 /* Direction bit mask. */ 4824 #define TC0_DIR_bp 0 /* Direction bit position. */ 4825 4826 4827 /* TC0.CTRLFSET bit masks and bit positions */ 4828 /* TC0_CMD_gm Predefined. */ 4829 /* TC0_CMD_gp Predefined. */ 4830 /* TC0_CMD0_bm Predefined. */ 4831 /* TC0_CMD0_bp Predefined. */ 4832 /* TC0_CMD1_bm Predefined. */ 4833 /* TC0_CMD1_bp Predefined. */ 4834 4835 /* TC0_LUPD_bm Predefined. */ 4836 /* TC0_LUPD_bp Predefined. */ 4837 4838 /* TC0_DIR_bm Predefined. */ 4839 /* TC0_DIR_bp Predefined. */ 4840 4841 4842 /* TC0.CTRLGCLR bit masks and bit positions */ 4843 #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ 4844 #define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ 4845 4846 #define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ 4847 #define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ 4848 4849 #define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 4850 #define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 4851 4852 #define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 4853 #define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 4854 4855 #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 4856 #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ 4857 4858 4859 /* TC0.CTRLGSET bit masks and bit positions */ 4860 /* TC0_CCDBV_bm Predefined. */ 4861 /* TC0_CCDBV_bp Predefined. */ 4862 4863 /* TC0_CCCBV_bm Predefined. */ 4864 /* TC0_CCCBV_bp Predefined. */ 4865 4866 /* TC0_CCBBV_bm Predefined. */ 4867 /* TC0_CCBBV_bp Predefined. */ 4868 4869 /* TC0_CCABV_bm Predefined. */ 4870 /* TC0_CCABV_bp Predefined. */ 4871 4872 /* TC0_PERBV_bm Predefined. */ 4873 /* TC0_PERBV_bp Predefined. */ 4874 4875 4876 /* TC0.INTFLAGS bit masks and bit positions */ 4877 #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ 4878 #define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ 4879 4880 #define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ 4881 #define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ 4882 4883 #define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 4884 #define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 4885 4886 #define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 4887 #define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 4888 4889 #define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 4890 #define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 4891 4892 #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 4893 #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 4894 4895 4896 /* TC1.CTRLA bit masks and bit positions */ 4897 #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ 4898 #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ 4899 #define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ 4900 #define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ 4901 #define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ 4902 #define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ 4903 #define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ 4904 #define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ 4905 #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ 4906 #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ 4907 4908 4909 /* TC1.CTRLB bit masks and bit positions */ 4910 #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ 4911 #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ 4912 4913 #define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ 4914 #define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ 4915 4916 #define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ 4917 #define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ 4918 #define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ 4919 #define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ 4920 #define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ 4921 #define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ 4922 #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ 4923 #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ 4924 4925 4926 /* TC1.CTRLC bit masks and bit positions */ 4927 #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ 4928 #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ 4929 4930 #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ 4931 #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ 4932 4933 4934 /* TC1.CTRLD bit masks and bit positions */ 4935 #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ 4936 #define TC1_EVACT_gp 5 /* Event Action group position. */ 4937 #define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ 4938 #define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ 4939 #define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ 4940 #define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ 4941 #define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ 4942 #define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ 4943 4944 #define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ 4945 #define TC1_EVDLY_bp 4 /* Event Delay bit position. */ 4946 4947 #define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ 4948 #define TC1_EVSEL_gp 0 /* Event Source Select group position. */ 4949 #define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ 4950 #define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ 4951 #define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ 4952 #define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ 4953 #define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ 4954 #define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ 4955 #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ 4956 #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ 4957 4958 4959 /* TC1.CTRLE bit masks and bit positions */ 4960 #define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ 4961 #define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ 4962 4963 #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ 4964 #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ 4965 4966 4967 /* TC1.INTCTRLA bit masks and bit positions */ 4968 #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ 4969 #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ 4970 #define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ 4971 #define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ 4972 #define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ 4973 #define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ 4974 4975 #define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ 4976 #define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ 4977 #define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ 4978 #define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ 4979 #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ 4980 #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ 4981 4982 4983 /* TC1.INTCTRLB bit masks and bit positions */ 4984 #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ 4985 #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ 4986 #define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ 4987 #define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ 4988 #define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ 4989 #define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ 4990 4991 #define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ 4992 #define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ 4993 #define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ 4994 #define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ 4995 #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ 4996 #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ 4997 4998 4999 /* TC1.CTRLFCLR bit masks and bit positions */ 5000 #define TC1_CMD_gm 0x0C /* Command group mask. */ 5001 #define TC1_CMD_gp 2 /* Command group position. */ 5002 #define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ 5003 #define TC1_CMD0_bp 2 /* Command bit 0 position. */ 5004 #define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ 5005 #define TC1_CMD1_bp 3 /* Command bit 1 position. */ 5006 5007 #define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ 5008 #define TC1_LUPD_bp 1 /* Lock Update bit position. */ 5009 5010 #define TC1_DIR_bm 0x01 /* Direction bit mask. */ 5011 #define TC1_DIR_bp 0 /* Direction bit position. */ 5012 5013 5014 /* TC1.CTRLFSET bit masks and bit positions */ 5015 /* TC1_CMD_gm Predefined. */ 5016 /* TC1_CMD_gp Predefined. */ 5017 /* TC1_CMD0_bm Predefined. */ 5018 /* TC1_CMD0_bp Predefined. */ 5019 /* TC1_CMD1_bm Predefined. */ 5020 /* TC1_CMD1_bp Predefined. */ 5021 5022 /* TC1_LUPD_bm Predefined. */ 5023 /* TC1_LUPD_bp Predefined. */ 5024 5025 /* TC1_DIR_bm Predefined. */ 5026 /* TC1_DIR_bp Predefined. */ 5027 5028 5029 /* TC1.CTRLGCLR bit masks and bit positions */ 5030 #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ 5031 #define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ 5032 5033 #define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ 5034 #define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ 5035 5036 #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ 5037 #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ 5038 5039 5040 /* TC1.CTRLGSET bit masks and bit positions */ 5041 /* TC1_CCBBV_bm Predefined. */ 5042 /* TC1_CCBBV_bp Predefined. */ 5043 5044 /* TC1_CCABV_bm Predefined. */ 5045 /* TC1_CCABV_bp Predefined. */ 5046 5047 /* TC1_PERBV_bm Predefined. */ 5048 /* TC1_PERBV_bp Predefined. */ 5049 5050 5051 /* TC1.INTFLAGS bit masks and bit positions */ 5052 #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ 5053 #define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ 5054 5055 #define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ 5056 #define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ 5057 5058 #define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ 5059 #define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ 5060 5061 #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ 5062 #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ 5063 5064 5065 /* AWEX.CTRL bit masks and bit positions */ 5066 #define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ 5067 #define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ 5068 5069 #define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ 5070 #define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ 5071 5072 #define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ 5073 #define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ 5074 5075 #define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ 5076 #define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ 5077 5078 #define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ 5079 #define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ 5080 5081 #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ 5082 #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ 5083 5084 5085 /* AWEX.FDCTRL bit masks and bit positions */ 5086 #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ 5087 #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ 5088 5089 #define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ 5090 #define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ 5091 5092 #define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ 5093 #define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ 5094 #define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ 5095 #define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ 5096 #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ 5097 #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ 5098 5099 5100 /* AWEX.STATUS bit masks and bit positions */ 5101 #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ 5102 #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ 5103 5104 #define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ 5105 #define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ 5106 5107 #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ 5108 #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ 5109 5110 5111 /* HIRES.CTRL bit masks and bit positions */ 5112 #define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ 5113 #define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ 5114 #define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ 5115 #define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ 5116 #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ 5117 #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ 5118 5119 5120 /* USART - Universal Asynchronous Receiver-Transmitter */ 5121 /* USART.STATUS bit masks and bit positions */ 5122 #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ 5123 #define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ 5124 5125 #define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ 5126 #define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ 5127 5128 #define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ 5129 #define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ 5130 5131 #define USART_FERR_bm 0x10 /* Frame Error bit mask. */ 5132 #define USART_FERR_bp 4 /* Frame Error bit position. */ 5133 5134 #define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ 5135 #define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ 5136 5137 #define USART_PERR_bm 0x04 /* Parity Error bit mask. */ 5138 #define USART_PERR_bp 2 /* Parity Error bit position. */ 5139 5140 #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ 5141 #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ 5142 5143 5144 /* USART.CTRLA bit masks and bit positions */ 5145 #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ 5146 #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ 5147 #define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ 5148 #define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ 5149 #define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ 5150 #define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ 5151 5152 #define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ 5153 #define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ 5154 #define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ 5155 #define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ 5156 #define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ 5157 #define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ 5158 5159 #define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ 5160 #define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ 5161 #define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ 5162 #define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ 5163 #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ 5164 #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ 5165 5166 5167 /* USART.CTRLB bit masks and bit positions */ 5168 #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ 5169 #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ 5170 5171 #define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ 5172 #define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ 5173 5174 #define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ 5175 #define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ 5176 5177 #define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ 5178 #define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ 5179 5180 #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ 5181 #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ 5182 5183 5184 /* USART.CTRLC bit masks and bit positions */ 5185 #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ 5186 #define USART_CMODE_gp 6 /* Communication Mode group position. */ 5187 #define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ 5188 #define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ 5189 #define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ 5190 #define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ 5191 5192 #define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ 5193 #define USART_PMODE_gp 4 /* Parity Mode group position. */ 5194 #define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ 5195 #define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ 5196 #define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ 5197 #define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ 5198 5199 #define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ 5200 #define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ 5201 5202 #define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ 5203 #define USART_CHSIZE_gp 0 /* Character Size group position. */ 5204 #define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ 5205 #define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ 5206 #define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ 5207 #define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ 5208 #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ 5209 #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ 5210 5211 5212 /* USART.BAUDCTRLA bit masks and bit positions */ 5213 #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ 5214 #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ 5215 #define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ 5216 #define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ 5217 #define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ 5218 #define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ 5219 #define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ 5220 #define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ 5221 #define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ 5222 #define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ 5223 #define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ 5224 #define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ 5225 #define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ 5226 #define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ 5227 #define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ 5228 #define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ 5229 #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ 5230 #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ 5231 5232 5233 /* USART.BAUDCTRLB bit masks and bit positions */ 5234 #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ 5235 #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ 5236 #define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ 5237 #define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ 5238 #define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ 5239 #define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ 5240 #define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ 5241 #define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ 5242 #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ 5243 #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ 5244 5245 /* USART_BSEL_gm Predefined. */ 5246 /* USART_BSEL_gp Predefined. */ 5247 /* USART_BSEL0_bm Predefined. */ 5248 /* USART_BSEL0_bp Predefined. */ 5249 /* USART_BSEL1_bm Predefined. */ 5250 /* USART_BSEL1_bp Predefined. */ 5251 /* USART_BSEL2_bm Predefined. */ 5252 /* USART_BSEL2_bp Predefined. */ 5253 /* USART_BSEL3_bm Predefined. */ 5254 /* USART_BSEL3_bp Predefined. */ 5255 5256 5257 /* SPI - Serial Peripheral Interface */ 5258 /* SPI.CTRL bit masks and bit positions */ 5259 #define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ 5260 #define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ 5261 5262 #define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ 5263 #define SPI_ENABLE_bp 6 /* Enable Module bit position. */ 5264 5265 #define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ 5266 #define SPI_DORD_bp 5 /* Data Order Setting bit position. */ 5267 5268 #define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ 5269 #define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ 5270 5271 #define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ 5272 #define SPI_MODE_gp 2 /* SPI Mode group position. */ 5273 #define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ 5274 #define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ 5275 #define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ 5276 #define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ 5277 5278 #define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ 5279 #define SPI_PRESCALER_gp 0 /* Prescaler group position. */ 5280 #define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ 5281 #define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ 5282 #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ 5283 #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ 5284 5285 5286 /* SPI.INTCTRL bit masks and bit positions */ 5287 #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ 5288 #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ 5289 #define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ 5290 #define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ 5291 #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ 5292 #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ 5293 5294 5295 /* SPI.STATUS bit masks and bit positions */ 5296 #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ 5297 #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ 5298 5299 #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ 5300 #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ 5301 5302 5303 /* IRCOM - IR Communication Module */ 5304 /* IRCOM.CTRL bit masks and bit positions */ 5305 #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ 5306 #define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ 5307 #define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ 5308 #define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ 5309 #define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ 5310 #define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ 5311 #define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ 5312 #define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ 5313 #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ 5314 #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ 5315 5316 5317 5318 // Generic Port Pins 5319 5320 #define PIN0_bm 0x01 5321 #define PIN0_bp 0 5322 #define PIN1_bm 0x02 5323 #define PIN1_bp 1 5324 #define PIN2_bm 0x04 5325 #define PIN2_bp 2 5326 #define PIN3_bm 0x08 5327 #define PIN3_bp 3 5328 #define PIN4_bm 0x10 5329 #define PIN4_bp 4 5330 #define PIN5_bm 0x20 5331 #define PIN5_bp 5 5332 #define PIN6_bm 0x40 5333 #define PIN6_bp 6 5334 #define PIN7_bm 0x80 5335 #define PIN7_bp 7 5336 5337 5338 /* ========== Interrupt Vector Definitions ========== */ 5339 /* Vector 0 is the reset vector */ 5340 5341 /* OSC interrupt vectors */ 5342 #define OSC_XOSCF_vect_num 1 5343 #define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ 5344 5345 /* PORTC interrupt vectors */ 5346 #define PORTC_INT0_vect_num 2 5347 #define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ 5348 #define PORTC_INT1_vect_num 3 5349 #define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ 5350 5351 /* PORTR interrupt vectors */ 5352 #define PORTR_INT0_vect_num 4 5353 #define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ 5354 #define PORTR_INT1_vect_num 5 5355 #define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ 5356 5357 /* RTC interrupt vectors */ 5358 #define RTC_OVF_vect_num 10 5359 #define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ 5360 #define RTC_COMP_vect_num 11 5361 #define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ 5362 5363 /* TWIC interrupt vectors */ 5364 #define TWIC_TWIS_vect_num 12 5365 #define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ 5366 #define TWIC_TWIM_vect_num 13 5367 #define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ 5368 5369 /* TCC0 interrupt vectors */ 5370 #define TCC0_OVF_vect_num 14 5371 #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ 5372 #define TCC0_ERR_vect_num 15 5373 #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ 5374 #define TCC0_CCA_vect_num 16 5375 #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ 5376 #define TCC0_CCB_vect_num 17 5377 #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ 5378 #define TCC0_CCC_vect_num 18 5379 #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ 5380 #define TCC0_CCD_vect_num 19 5381 #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ 5382 5383 /* TCC1 interrupt vectors */ 5384 #define TCC1_OVF_vect_num 20 5385 #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ 5386 #define TCC1_ERR_vect_num 21 5387 #define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ 5388 #define TCC1_CCA_vect_num 22 5389 #define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ 5390 #define TCC1_CCB_vect_num 23 5391 #define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ 5392 5393 /* SPIC interrupt vectors */ 5394 #define SPIC_INT_vect_num 24 5395 #define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ 5396 5397 /* USARTC0 interrupt vectors */ 5398 #define USARTC0_RXC_vect_num 25 5399 #define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ 5400 #define USARTC0_DRE_vect_num 26 5401 #define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ 5402 #define USARTC0_TXC_vect_num 27 5403 #define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ 5404 5405 /* NVM interrupt vectors */ 5406 #define NVM_EE_vect_num 32 5407 #define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ 5408 #define NVM_SPM_vect_num 33 5409 #define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ 5410 5411 /* PORTB interrupt vectors */ 5412 #define PORTB_INT0_vect_num 34 5413 #define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ 5414 #define PORTB_INT1_vect_num 35 5415 #define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ 5416 5417 /* PORTE interrupt vectors */ 5418 #define PORTE_INT0_vect_num 43 5419 #define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ 5420 #define PORTE_INT1_vect_num 44 5421 #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ 5422 5423 /* TWIE interrupt vectors */ 5424 #define TWIE_TWIS_vect_num 45 5425 #define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ 5426 #define TWIE_TWIM_vect_num 46 5427 #define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ 5428 5429 /* TCE0 interrupt vectors */ 5430 #define TCE0_OVF_vect_num 47 5431 #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ 5432 #define TCE0_ERR_vect_num 48 5433 #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ 5434 #define TCE0_CCA_vect_num 49 5435 #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ 5436 #define TCE0_CCB_vect_num 50 5437 #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ 5438 #define TCE0_CCC_vect_num 51 5439 #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ 5440 #define TCE0_CCD_vect_num 52 5441 #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ 5442 5443 /* PORTD interrupt vectors */ 5444 #define PORTD_INT0_vect_num 64 5445 #define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ 5446 #define PORTD_INT1_vect_num 65 5447 #define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ 5448 5449 /* PORTA interrupt vectors */ 5450 #define PORTA_INT0_vect_num 66 5451 #define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ 5452 #define PORTA_INT1_vect_num 67 5453 #define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ 5454 5455 /* ACA interrupt vectors */ 5456 #define ACA_AC0_vect_num 68 5457 #define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ 5458 #define ACA_AC1_vect_num 69 5459 #define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ 5460 #define ACA_ACW_vect_num 70 5461 #define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ 5462 5463 /* ADCA interrupt vectors */ 5464 #define ADCA_CH0_vect_num 71 5465 #define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ 5466 5467 /* TCD0 interrupt vectors */ 5468 #define TCD0_OVF_vect_num 77 5469 #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ 5470 #define TCD0_ERR_vect_num 78 5471 #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ 5472 #define TCD0_CCA_vect_num 79 5473 #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ 5474 #define TCD0_CCB_vect_num 80 5475 #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ 5476 #define TCD0_CCC_vect_num 81 5477 #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ 5478 #define TCD0_CCD_vect_num 82 5479 #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ 5480 5481 /* SPID interrupt vectors */ 5482 #define SPID_INT_vect_num 87 5483 #define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ 5484 5485 /* USARTD0 interrupt vectors */ 5486 #define USARTD0_RXC_vect_num 88 5487 #define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ 5488 #define USARTD0_DRE_vect_num 89 5489 #define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ 5490 #define USARTD0_TXC_vect_num 90 5491 #define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ 5492 5493 5494 #define _VECTOR_SIZE 4 /* Size of individual vector. */ 5495 #define _VECTORS_SIZE (91 * _VECTOR_SIZE) 5496 5497 5498 /* ========== Constants ========== */ 5499 5500 #define PROGMEM_START (0x0000) 5501 #define PROGMEM_SIZE (36864) 5502 #define PROGMEM_PAGE_SIZE (256) 5503 #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) 5504 5505 #define APP_SECTION_START (0x0000) 5506 #define APP_SECTION_SIZE (32768) 5507 #define APP_SECTION_PAGE_SIZE (256) 5508 #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) 5509 5510 #define APPTABLE_SECTION_START (0x7000) 5511 #define APPTABLE_SECTION_SIZE (4096) 5512 #define APPTABLE_SECTION_PAGE_SIZE (256) 5513 #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) 5514 5515 #define BOOT_SECTION_START (0x8000) 5516 #define BOOT_SECTION_SIZE (4096) 5517 #define BOOT_SECTION_PAGE_SIZE (256) 5518 #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) 5519 5520 #define DATAMEM_START (0x0000) 5521 #define DATAMEM_SIZE (12288) 5522 #define DATAMEM_PAGE_SIZE (0) 5523 #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) 5524 5525 #define IO_START (0x0000) 5526 #define IO_SIZE (4096) 5527 #define IO_PAGE_SIZE (0) 5528 #define IO_END (IO_START + IO_SIZE - 1) 5529 5530 #define MAPPED_EEPROM_START (0x1000) 5531 #define MAPPED_EEPROM_SIZE (1024) 5532 #define MAPPED_EEPROM_PAGE_SIZE (0) 5533 #define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) 5534 5535 #define INTERNAL_SRAM_START (0x2000) 5536 #define INTERNAL_SRAM_SIZE (4096) 5537 #define INTERNAL_SRAM_PAGE_SIZE (0) 5538 #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) 5539 5540 #define EEPROM_START (0x0000) 5541 #define EEPROM_SIZE (1024) 5542 #define EEPROM_PAGE_SIZE (32) 5543 #define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) 5544 5545 #define FUSE_START (0x0000) 5546 #define FUSE_SIZE (6) 5547 #define FUSE_PAGE_SIZE (0) 5548 #define FUSE_END (FUSE_START + FUSE_SIZE - 1) 5549 5550 #define LOCKBIT_START (0x0000) 5551 #define LOCKBIT_SIZE (1) 5552 #define LOCKBIT_PAGE_SIZE (0) 5553 #define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) 5554 5555 #define SIGNATURES_START (0x0000) 5556 #define SIGNATURES_SIZE (3) 5557 #define SIGNATURES_PAGE_SIZE (0) 5558 #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) 5559 5560 #define USER_SIGNATURES_START (0x0000) 5561 #define USER_SIGNATURES_SIZE (256) 5562 #define USER_SIGNATURES_PAGE_SIZE (0) 5563 #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) 5564 5565 #define PROD_SIGNATURES_START (0x0000) 5566 #define PROD_SIGNATURES_SIZE (52) 5567 #define PROD_SIGNATURES_PAGE_SIZE (0) 5568 #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) 5569 5570 #define FLASHEND PROGMEM_END 5571 #define SPM_PAGESIZE PROGMEM_PAGE_SIZE 5572 #define RAMSTART INTERNAL_SRAM_START 5573 #define RAMSIZE INTERNAL_SRAM_SIZE 5574 #define RAMEND INTERNAL_SRAM_END 5575 #define XRAMSTART EXTERNAL_SRAM_START 5576 #define XRAMSIZE EXTERNAL_SRAM_SIZE 5577 #define XRAMEND INTERNAL_SRAM_END 5578 #define E2END EEPROM_END 5579 #define E2PAGESIZE EEPROM_PAGE_SIZE 5580 5581 5582 /* ========== Fuses ========== */ 5583 #define FUSE_MEMORY_SIZE 6 5584 5585 /* Fuse Byte 0 */ 5586 #define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ 5587 #define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ 5588 #define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ 5589 #define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ 5590 #define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ 5591 #define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ 5592 #define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ 5593 #define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ 5594 #define FUSE0_DEFAULT (0xFF) 5595 5596 /* Fuse Byte 1 */ 5597 #define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ 5598 #define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ 5599 #define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ 5600 #define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ 5601 #define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ 5602 #define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ 5603 #define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ 5604 #define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ 5605 #define FUSE1_DEFAULT (0xFF) 5606 5607 /* Fuse Byte 2 */ 5608 #define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ 5609 #define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ 5610 #define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ 5611 #define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ 5612 #define FUSE2_DEFAULT (0xFF) 5613 5614 /* Fuse Byte 3 Reserved */ 5615 5616 /* Fuse Byte 4 */ 5617 #define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ 5618 #define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ 5619 #define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ 5620 #define FUSE4_DEFAULT (0xFF) 5621 5622 /* Fuse Byte 5 */ 5623 #define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ 5624 #define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ 5625 #define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ 5626 #define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ 5627 #define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ 5628 #define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ 5629 #define FUSE5_DEFAULT (0xFF) 5630 5631 5632 /* ========== Lock Bits ========== */ 5633 #define __LOCK_BITS_EXIST 5634 #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST 5635 #define __BOOT_LOCK_APPLICATION_BITS_EXIST 5636 #define __BOOT_LOCK_BOOT_BITS_EXIST 5637 5638 5639 /* ========== Signature ========== */ 5640 #define SIGNATURE_0 0x1E 5641 #define SIGNATURE_1 0x95 5642 #define SIGNATURE_2 0x42 5643 5644 /* ========== Power Reduction Condition Definitions ========== */ 5645 5646 /* PR.PRGEN */ 5647 #define __AVR_HAVE_PRGEN (PR_RTC_bm|PR_EVSYS_bm) 5648 #define __AVR_HAVE_PRGEN_RTC 5649 #define __AVR_HAVE_PRGEN_EVSYS 5650 5651 /* PR.PRPA */ 5652 #define __AVR_HAVE_PRPA (PR_ADC_bm|PR_AC_bm) 5653 #define __AVR_HAVE_PRPA_ADC 5654 #define __AVR_HAVE_PRPA_AC 5655 5656 /* PR.PRPC */ 5657 #define __AVR_HAVE_PRPC (PR_TWI_bm|PR_USART0_bm|PR_SPI_bm|PR_HIRES_bm|PR_TC1_bm|PR_TC0_bm) 5658 #define __AVR_HAVE_PRPC_TWI 5659 #define __AVR_HAVE_PRPC_USART0 5660 #define __AVR_HAVE_PRPC_SPI 5661 #define __AVR_HAVE_PRPC_HIRES 5662 #define __AVR_HAVE_PRPC_TC1 5663 #define __AVR_HAVE_PRPC_TC0 5664 5665 /* PR.PRPD */ 5666 #define __AVR_HAVE_PRPD (PR_USART0_bm|PR_SPI_bm|PR_TC0_bm) 5667 #define __AVR_HAVE_PRPD_USART0 5668 #define __AVR_HAVE_PRPD_SPI 5669 #define __AVR_HAVE_PRPD_TC0 5670 5671 /* PR.PRPE */ 5672 #define __AVR_HAVE_PRPE (PR_TWI_bm|PR_USART0_bm|PR_TC0_bm) 5673 #define __AVR_HAVE_PRPE_TWI 5674 #define __AVR_HAVE_PRPE_USART0 5675 #define __AVR_HAVE_PRPE_TC0 5676 5677 /* PR.PRPF */ 5678 #define __AVR_HAVE_PRPF (PR_USART0_bm|PR_TC0_bm) 5679 #define __AVR_HAVE_PRPF_USART0 5680 #define __AVR_HAVE_PRPF_TC0 5681 5682 5683 #endif /* _AVR_ATxmega32D4_H_ */ 5684 5685