1 /*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #ifndef _DRM_DP_HELPER_H_
24 #define _DRM_DP_HELPER_H_
25
26 #include <linux/delay.h>
27 #include <linux/i2c.h>
28
29 #include <drm/display/drm_dp.h>
30 #include <drm/drm_connector.h>
31
32 struct drm_device;
33 struct drm_dp_aux;
34 struct drm_panel;
35
36 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
37 int lane_count);
38 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
39 int lane_count);
40 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
41 int lane);
42 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
43 int lane);
44 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
45 int lane);
46
47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
48 enum drm_dp_phy dp_phy, bool uhbr);
49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
50 enum drm_dp_phy dp_phy, bool uhbr);
51
52 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
54 void drm_dp_lttpr_link_train_clock_recovery_delay(void);
55 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
57 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
58 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
59
60 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
61 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
62 int lane_count);
63 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
64 int lane_count);
65 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
66 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
67 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);
68
69 u8 drm_dp_link_rate_to_bw_code(int link_rate);
70 int drm_dp_bw_code_to_link_rate(u8 link_bw);
71
72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
73
74 /**
75 * struct drm_dp_vsc_sdp - drm DP VSC SDP
76 *
77 * This structure represents a DP VSC SDP of drm
78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
79 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
80 *
81 * @sdp_type: secondary-data packet type
82 * @revision: revision number
83 * @length: number of valid data bytes
84 * @pixelformat: pixel encoding format
85 * @colorimetry: colorimetry format
86 * @bpc: bit per color
87 * @dynamic_range: dynamic range information
88 * @content_type: CTA-861-G defines content types and expected processing by a sink device
89 */
90 struct drm_dp_vsc_sdp {
91 unsigned char sdp_type;
92 unsigned char revision;
93 unsigned char length;
94 enum dp_pixelformat pixelformat;
95 enum dp_colorimetry colorimetry;
96 int bpc;
97 enum dp_dynamic_range dynamic_range;
98 enum dp_content_type content_type;
99 };
100
101 /**
102 * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP
103 *
104 * This structure represents a DP AS SDP of drm
105 * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and
106 * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8]
107 *
108 * @sdp_type: Secondary-data packet type
109 * @revision: Revision Number
110 * @length: Number of valid data bytes
111 * @vtotal: Minimum Vertical Vtotal
112 * @target_rr: Target Refresh
113 * @duration_incr_ms: Successive frame duration increase
114 * @duration_decr_ms: Successive frame duration decrease
115 * @operation_mode: Adaptive Sync Operation Mode
116 */
117 struct drm_dp_as_sdp {
118 unsigned char sdp_type;
119 unsigned char revision;
120 unsigned char length;
121 int vtotal;
122 int target_rr;
123 int duration_incr_ms;
124 int duration_decr_ms;
125 enum operation_mode mode;
126 };
127
128 void drm_dp_as_sdp_log(struct drm_printer *p,
129 const struct drm_dp_as_sdp *as_sdp);
130 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc);
131
132 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
133 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
134
135 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
136
137 static inline int
drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])138 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
139 {
140 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
141 }
142
143 static inline u8
drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])144 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
145 {
146 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
147 }
148
149 static inline bool
drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])150 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
151 {
152 return dpcd[DP_DPCD_REV] >= 0x11 &&
153 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
154 }
155
156 static inline bool
drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])157 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
158 {
159 return dpcd[DP_DPCD_REV] >= 0x11 &&
160 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
161 }
162
163 static inline bool
drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])164 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
165 {
166 return dpcd[DP_DPCD_REV] >= 0x12 &&
167 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
168 }
169
170 static inline bool
drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])171 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
172 {
173 return dpcd[DP_DPCD_REV] >= 0x11 ||
174 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5;
175 }
176
177 static inline bool
drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])178 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
179 {
180 return dpcd[DP_DPCD_REV] >= 0x14 &&
181 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
182 }
183
184 static inline u8
drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])185 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
186 {
187 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
188 DP_TRAINING_PATTERN_MASK;
189 }
190
191 static inline bool
drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])192 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
193 {
194 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
195 }
196
197 /* DP/eDP DSC support */
198 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
199 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
200 bool is_edp);
201 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
202 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
203 u8 dsc_bpc[3]);
204
205 static inline bool
drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])206 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
207 {
208 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
209 DP_DSC_DECOMPRESSION_IS_SUPPORTED;
210 }
211
212 static inline u16
drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])213 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
214 {
215 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
216 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
217 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8);
218 }
219
220 static inline u32
drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])221 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
222 {
223 /* Max Slicewidth = Number of Pixels * 320 */
224 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
225 DP_DSC_SLICE_WIDTH_MULTIPLIER;
226 }
227
228 /**
229 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format
230 * @dsc_dpcd : DSC-capability DPCDs of the sink
231 * @output_format: output_format which is to be checked
232 *
233 * Returns true if the sink supports DSC with the given output_format, false otherwise.
234 */
235 static inline bool
drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],u8 output_format)236 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format)
237 {
238 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format;
239 }
240
241 /* Forward Error Correction Support on DP 1.4 */
242 static inline bool
drm_dp_sink_supports_fec(const u8 fec_capable)243 drm_dp_sink_supports_fec(const u8 fec_capable)
244 {
245 return fec_capable & DP_FEC_CAPABLE;
246 }
247
248 static inline bool
drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])249 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
250 {
251 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
252 }
253
254 static inline bool
drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])255 drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
256 {
257 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B;
258 }
259
260 static inline bool
drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])261 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
262 {
263 return dpcd[DP_EDP_CONFIGURATION_CAP] &
264 DP_ALTERNATE_SCRAMBLER_RESET_CAP;
265 }
266
267 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
268 static inline bool
drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])269 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
270 {
271 return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
272 DP_MSA_TIMING_PAR_IGNORED;
273 }
274
275 /**
276 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
277 * @edp_dpcd: The DPCD to check
278 *
279 * Note that currently this function will return %false for panels which support various DPCD
280 * backlight features but which require the brightness be set through PWM, and don't support setting
281 * the brightness level via the DPCD.
282 *
283 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
284 * otherwise
285 */
286 static inline bool
drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])287 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
288 {
289 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
290 }
291
292 /**
293 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR
294 * @link_rate: link rate in 10kbits/s units
295 *
296 * Determine if the provided link rate is an UHBR rate.
297 *
298 * Returns: %True if @link_rate is an UHBR rate.
299 */
drm_dp_is_uhbr_rate(int link_rate)300 static inline bool drm_dp_is_uhbr_rate(int link_rate)
301 {
302 return link_rate >= 1000000;
303 }
304
305 /*
306 * DisplayPort AUX channel
307 */
308
309 /**
310 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
311 * @address: address of the (first) register to access
312 * @request: contains the type of transaction (see DP_AUX_* macros)
313 * @reply: upon completion, contains the reply type of the transaction
314 * @buffer: pointer to a transmission or reception buffer
315 * @size: size of @buffer
316 */
317 struct drm_dp_aux_msg {
318 unsigned int address;
319 u8 request;
320 u8 reply;
321 void *buffer;
322 size_t size;
323 };
324
325 struct cec_adapter;
326 struct drm_connector;
327 struct drm_edid;
328
329 /**
330 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
331 * @lock: mutex protecting this struct
332 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
333 * @connector: the connector this CEC adapter is associated with
334 * @unregister_work: unregister the CEC adapter
335 */
336 struct drm_dp_aux_cec {
337 struct mutex lock;
338 struct cec_adapter *adap;
339 struct drm_connector *connector;
340 struct delayed_work unregister_work;
341 };
342
343 /**
344 * struct drm_dp_aux - DisplayPort AUX channel
345 *
346 * An AUX channel can also be used to transport I2C messages to a sink. A
347 * typical application of that is to access an EDID that's present in the sink
348 * device. The @transfer() function can also be used to execute such
349 * transactions. The drm_dp_aux_register() function registers an I2C adapter
350 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
351 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
352 * transfers by default; if a partial response is received, the adapter will
353 * drop down to the size given by the partial response for this transaction
354 * only.
355 */
356 struct drm_dp_aux {
357 /**
358 * @name: user-visible name of this AUX channel and the
359 * I2C-over-AUX adapter.
360 *
361 * It's also used to specify the name of the I2C adapter. If set
362 * to %NULL, dev_name() of @dev will be used.
363 */
364 const char *name;
365
366 /**
367 * @ddc: I2C adapter that can be used for I2C-over-AUX
368 * communication
369 */
370 struct i2c_adapter ddc;
371
372 /**
373 * @dev: pointer to struct device that is the parent for this
374 * AUX channel.
375 */
376 struct device *dev;
377
378 /**
379 * @drm_dev: pointer to the &drm_device that owns this AUX channel.
380 * Beware, this may be %NULL before drm_dp_aux_register() has been
381 * called.
382 *
383 * It should be set to the &drm_device that will be using this AUX
384 * channel as early as possible. For many graphics drivers this should
385 * happen before drm_dp_aux_init(), however it's perfectly fine to set
386 * this field later so long as it's assigned before calling
387 * drm_dp_aux_register().
388 */
389 struct drm_device *drm_dev;
390
391 /**
392 * @crtc: backpointer to the crtc that is currently using this
393 * AUX channel
394 */
395 struct drm_crtc *crtc;
396
397 /**
398 * @hw_mutex: internal mutex used for locking transfers.
399 *
400 * Note that if the underlying hardware is shared among multiple
401 * channels, the driver needs to do additional locking to
402 * prevent concurrent access.
403 */
404 struct mutex hw_mutex;
405
406 /**
407 * @crc_work: worker that captures CRCs for each frame
408 */
409 struct work_struct crc_work;
410
411 /**
412 * @crc_count: counter of captured frame CRCs
413 */
414 u8 crc_count;
415
416 /**
417 * @transfer: transfers a message representing a single AUX
418 * transaction.
419 *
420 * This is a hardware-specific implementation of how
421 * transactions are executed that the drivers must provide.
422 *
423 * A pointer to a &drm_dp_aux_msg structure describing the
424 * transaction is passed into this function. Upon success, the
425 * implementation should return the number of payload bytes that
426 * were transferred, or a negative error-code on failure.
427 *
428 * Helpers will propagate these errors, with the exception of
429 * the %-EBUSY error, which causes a transaction to be retried.
430 * On a short, helpers will return %-EPROTO to make it simpler
431 * to check for failure.
432 *
433 * The @transfer() function must only modify the reply field of
434 * the &drm_dp_aux_msg structure. The retry logic and i2c
435 * helpers assume this is the case.
436 *
437 * Also note that this callback can be called no matter the
438 * state @dev is in and also no matter what state the panel is
439 * in. It's expected:
440 *
441 * - If the @dev providing the AUX bus is currently unpowered then
442 * it will power itself up for the transfer.
443 *
444 * - If we're on eDP (using a drm_panel) and the panel is not in a
445 * state where it can respond (it's not powered or it's in a
446 * low power state) then this function may return an error, but
447 * not crash. It's up to the caller of this code to make sure that
448 * the panel is powered on if getting an error back is not OK. If a
449 * drm_panel driver is initiating a DP AUX transfer it may power
450 * itself up however it wants. All other code should ensure that
451 * the pre_enable() bridge chain (which eventually calls the
452 * drm_panel prepare function) has powered the panel.
453 */
454 ssize_t (*transfer)(struct drm_dp_aux *aux,
455 struct drm_dp_aux_msg *msg);
456
457 /**
458 * @wait_hpd_asserted: wait for HPD to be asserted
459 *
460 * This is mainly useful for eDP panels drivers to wait for an eDP
461 * panel to finish powering on. It is optional for DP AUX controllers
462 * to implement this function. It is required for DP AUX endpoints
463 * (panel drivers) to call this function after powering up but before
464 * doing AUX transfers unless the DP AUX endpoint driver knows that
465 * we're not using the AUX controller's HPD. One example of the panel
466 * driver not needing to call this is if HPD is hooked up to a GPIO
467 * that the panel driver can read directly.
468 *
469 * If a DP AUX controller does not implement this function then it
470 * may still support eDP panels that use the AUX controller's built-in
471 * HPD signal by implementing a long wait for HPD in the transfer()
472 * callback, though this is deprecated.
473 *
474 * This function will efficiently wait for the HPD signal to be
475 * asserted. The `wait_us` parameter that is passed in says that we
476 * know that the HPD signal is expected to be asserted within `wait_us`
477 * microseconds. This function could wait for longer than `wait_us` if
478 * the logic in the DP controller has a long debouncing time. The
479 * important thing is that if this function returns success that the
480 * DP controller is ready to send AUX transactions.
481 *
482 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time
483 * expired and HPD wasn't asserted. This function should not print
484 * timeout errors to the log.
485 *
486 * The semantics of this function are designed to match the
487 * readx_poll_timeout() function. That means a `wait_us` of 0 means
488 * to wait forever. Like readx_poll_timeout(), this function may sleep.
489 *
490 * NOTE: this function specifically reports the state of the HPD pin
491 * that's associated with the DP AUX channel. This is different from
492 * the HPD concept in much of the rest of DRM which is more about
493 * physical presence of a display. For eDP, for instance, a display is
494 * assumed always present even if the HPD pin is deasserted.
495 */
496 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us);
497
498 /**
499 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
500 */
501 unsigned i2c_nack_count;
502 /**
503 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
504 */
505 unsigned i2c_defer_count;
506 /**
507 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
508 */
509 struct drm_dp_aux_cec cec;
510 /**
511 * @is_remote: Is this AUX CH actually using sideband messaging.
512 */
513 bool is_remote;
514
515 /**
516 * @powered_down: If true then the remote endpoint is powered down.
517 */
518 bool powered_down;
519 };
520
521 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset);
522 void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered);
523 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
524 void *buffer, size_t size);
525 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
526 void *buffer, size_t size);
527
528 /**
529 * drm_dp_dpcd_readb() - read a single byte from the DPCD
530 * @aux: DisplayPort AUX channel
531 * @offset: address of the register to read
532 * @valuep: location where the value of the register will be stored
533 *
534 * Returns the number of bytes transferred (1) on success, or a negative
535 * error code on failure.
536 */
drm_dp_dpcd_readb(struct drm_dp_aux * aux,unsigned int offset,u8 * valuep)537 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
538 unsigned int offset, u8 *valuep)
539 {
540 return drm_dp_dpcd_read(aux, offset, valuep, 1);
541 }
542
543 /**
544 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
545 * @aux: DisplayPort AUX channel
546 * @offset: address of the register to write
547 * @value: value to write to the register
548 *
549 * Returns the number of bytes transferred (1) on success, or a negative
550 * error code on failure.
551 */
drm_dp_dpcd_writeb(struct drm_dp_aux * aux,unsigned int offset,u8 value)552 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
553 unsigned int offset, u8 value)
554 {
555 return drm_dp_dpcd_write(aux, offset, &value, 1);
556 }
557
558 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
559 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
560
561 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
562 u8 status[DP_LINK_STATUS_SIZE]);
563
564 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
565 enum drm_dp_phy dp_phy,
566 u8 link_status[DP_LINK_STATUS_SIZE]);
567
568 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
569 u8 real_edid_checksum);
570
571 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
572 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
573 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
574 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
575 const u8 port_cap[4], u8 type);
576 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
577 const u8 port_cap[4],
578 const struct drm_edid *drm_edid);
579 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
580 const u8 port_cap[4]);
581 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
582 const u8 port_cap[4],
583 const struct drm_edid *drm_edid);
584 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
585 const u8 port_cap[4],
586 const struct drm_edid *drm_edid);
587 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
588 const u8 port_cap[4],
589 const struct drm_edid *drm_edid);
590 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
591 const u8 port_cap[4]);
592 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
593 const u8 port_cap[4]);
594 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
595 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
596 const u8 port_cap[4]);
597 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
598 void drm_dp_downstream_debug(struct seq_file *m,
599 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
600 const u8 port_cap[4],
601 const struct drm_edid *drm_edid,
602 struct drm_dp_aux *aux);
603 enum drm_mode_subconnector
604 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
605 const u8 port_cap[4]);
606 void drm_dp_set_subconnector_property(struct drm_connector *connector,
607 enum drm_connector_status status,
608 const u8 *dpcd,
609 const u8 port_cap[4]);
610
611 struct drm_dp_desc;
612 bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
613 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
614 const struct drm_dp_desc *desc);
615 int drm_dp_read_sink_count(struct drm_dp_aux *aux);
616
617 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
618 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
619 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
620 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
621 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
622 enum drm_dp_phy dp_phy,
623 u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
624 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
625 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
626 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
627 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
628 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
629
630 void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
631 void drm_dp_aux_init(struct drm_dp_aux *aux);
632 int drm_dp_aux_register(struct drm_dp_aux *aux);
633 void drm_dp_aux_unregister(struct drm_dp_aux *aux);
634
635 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
636 int drm_dp_stop_crc(struct drm_dp_aux *aux);
637
638 struct drm_dp_dpcd_ident {
639 u8 oui[3];
640 u8 device_id[6];
641 u8 hw_rev;
642 u8 sw_major_rev;
643 u8 sw_minor_rev;
644 } __packed;
645
646 /**
647 * struct drm_dp_desc - DP branch/sink device descriptor
648 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
649 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
650 */
651 struct drm_dp_desc {
652 struct drm_dp_dpcd_ident ident;
653 u32 quirks;
654 };
655
656 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
657 bool is_branch);
658
659 /**
660 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
661 *
662 * Display Port sink and branch devices in the wild have a variety of bugs, try
663 * to collect them here. The quirks are shared, but it's up to the drivers to
664 * implement workarounds for them.
665 */
666 enum drm_dp_quirk {
667 /**
668 * @DP_DPCD_QUIRK_CONSTANT_N:
669 *
670 * The device requires main link attributes Mvid and Nvid to be limited
671 * to 16 bits. So will give a constant value (0x8000) for compatability.
672 */
673 DP_DPCD_QUIRK_CONSTANT_N,
674 /**
675 * @DP_DPCD_QUIRK_NO_PSR:
676 *
677 * The device does not support PSR even if reports that it supports or
678 * driver still need to implement proper handling for such device.
679 */
680 DP_DPCD_QUIRK_NO_PSR,
681 /**
682 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
683 *
684 * The device does not set SINK_COUNT to a non-zero value.
685 * The driver should ignore SINK_COUNT during detection. Note that
686 * drm_dp_read_sink_count_cap() automatically checks for this quirk.
687 */
688 DP_DPCD_QUIRK_NO_SINK_COUNT,
689 /**
690 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
691 *
692 * The device supports MST DSC despite not supporting Virtual DPCD.
693 * The DSC caps can be read from the physical aux instead.
694 */
695 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
696 /**
697 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
698 *
699 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
700 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
701 */
702 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
703 /**
704 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC:
705 *
706 * The device applies HBLANK expansion for some modes, but this
707 * requires enabling DSC.
708 */
709 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
710 };
711
712 /**
713 * drm_dp_has_quirk() - does the DP device have a specific quirk
714 * @desc: Device descriptor filled by drm_dp_read_desc()
715 * @quirk: Quirk to query for
716 *
717 * Return true if DP device identified by @desc has @quirk.
718 */
719 static inline bool
drm_dp_has_quirk(const struct drm_dp_desc * desc,enum drm_dp_quirk quirk)720 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
721 {
722 return desc->quirks & BIT(quirk);
723 }
724
725 /**
726 * struct drm_edp_backlight_info - Probed eDP backlight info struct
727 * @pwmgen_bit_count: The pwmgen bit count
728 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
729 * @max: The maximum backlight level that may be set
730 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
731 * @aux_enable: Does the panel support the AUX enable cap?
732 * @aux_set: Does the panel support setting the brightness through AUX?
733 *
734 * This structure contains various data about an eDP backlight, which can be populated by using
735 * drm_edp_backlight_init().
736 */
737 struct drm_edp_backlight_info {
738 u8 pwmgen_bit_count;
739 u8 pwm_freq_pre_divider;
740 u16 max;
741
742 bool lsb_reg_used : 1;
743 bool aux_enable : 1;
744 bool aux_set : 1;
745 };
746
747 int
748 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
749 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
750 u16 *current_level, u8 *current_mode);
751 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
752 u16 level);
753 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
754 u16 level);
755 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
756
757 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
758 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)))
759
760 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux);
761
762 #else
763
drm_panel_dp_aux_backlight(struct drm_panel * panel,struct drm_dp_aux * aux)764 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel,
765 struct drm_dp_aux *aux)
766 {
767 return 0;
768 }
769
770 #endif
771
772 #ifdef CONFIG_DRM_DISPLAY_DP_AUX_CEC
773 void drm_dp_cec_irq(struct drm_dp_aux *aux);
774 void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
775 struct drm_connector *connector);
776 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
777 void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address);
778 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
779 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
780 #else
drm_dp_cec_irq(struct drm_dp_aux * aux)781 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
782 {
783 }
784
785 static inline void
drm_dp_cec_register_connector(struct drm_dp_aux * aux,struct drm_connector * connector)786 drm_dp_cec_register_connector(struct drm_dp_aux *aux,
787 struct drm_connector *connector)
788 {
789 }
790
drm_dp_cec_unregister_connector(struct drm_dp_aux * aux)791 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
792 {
793 }
794
drm_dp_cec_attach(struct drm_dp_aux * aux,u16 source_physical_address)795 static inline void drm_dp_cec_attach(struct drm_dp_aux *aux,
796 u16 source_physical_address)
797 {
798 }
799
drm_dp_cec_set_edid(struct drm_dp_aux * aux,const struct edid * edid)800 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
801 const struct edid *edid)
802 {
803 }
804
drm_dp_cec_unset_edid(struct drm_dp_aux * aux)805 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
806 {
807 }
808
809 #endif
810
811 /**
812 * struct drm_dp_phy_test_params - DP Phy Compliance parameters
813 * @link_rate: Requested Link rate from DPCD 0x219
814 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
815 * @phy_pattern: DP Phy test pattern from DPCD 0x248
816 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
817 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
818 * @enhanced_frame_cap: flag for enhanced frame capability.
819 */
820 struct drm_dp_phy_test_params {
821 int link_rate;
822 u8 num_lanes;
823 u8 phy_pattern;
824 u8 hbr2_reset[2];
825 u8 custom80[10];
826 bool enhanced_frame_cap;
827 };
828
829 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
830 struct drm_dp_phy_test_params *data);
831 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
832 struct drm_dp_phy_test_params *data, u8 dp_rev);
833 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
834 const u8 port_cap[4]);
835 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
836 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
837 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
838 u8 frl_mode);
839 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
840 u8 frl_type);
841 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
842 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
843
844 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
845 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
846 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
847 struct drm_connector *connector);
848 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
849 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
850 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
851 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
852 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
853 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
854 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
855 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
856 const u8 port_cap[4], u8 color_spc);
857 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
858
859 #define DRM_DP_BW_OVERHEAD_MST BIT(0)
860 #define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
861 #define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
862 #define DRM_DP_BW_OVERHEAD_FEC BIT(3)
863 #define DRM_DP_BW_OVERHEAD_DSC BIT(4)
864
865 int drm_dp_bw_overhead(int lane_count, int hactive,
866 int dsc_slice_count,
867 int bpp_x16, unsigned long flags);
868 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
869 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes);
870
871 ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp);
872
873 #endif /* _DRM_DP_HELPER_H_ */
874