xref: /qemu/include/hw/rx/rx62n.h (revision 2e0b925a)
1 /*
2  * RX62N MCU Object
3  *
4  * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
5  *            (Rev.1.40 R01UH0033EJ0140)
6  *
7  * Copyright (c) 2019 Yoshinori Sato
8  *
9  * SPDX-License-Identifier: GPL-2.0-or-later
10  *
11  * This program is free software; you can redistribute it and/or modify it
12  * under the terms and conditions of the GNU General Public License,
13  * version 2 or later, as published by the Free Software Foundation.
14  *
15  * This program is distributed in the hope it will be useful, but WITHOUT
16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18  * more details.
19  *
20  * You should have received a copy of the GNU General Public License along with
21  * this program.  If not, see <http://www.gnu.org/licenses/>.
22  */
23 
24 #ifndef HW_RX_RX62N_H
25 #define HW_RX_RX62N_H
26 
27 #include "target/rx/cpu.h"
28 #include "hw/intc/rx_icu.h"
29 #include "hw/timer/renesas_tmr.h"
30 #include "hw/timer/renesas_cmt.h"
31 #include "hw/char/renesas_sci.h"
32 #include "qom/object.h"
33 
34 #define TYPE_RX62N_MCU "rx62n-mcu"
35 typedef struct RX62NState RX62NState;
36 DECLARE_INSTANCE_CHECKER(RX62NState, RX62N_MCU,
37                          TYPE_RX62N_MCU)
38 
39 #define TYPE_R5F562N7_MCU "r5f562n7-mcu"
40 #define TYPE_R5F562N8_MCU "r5f562n8-mcu"
41 
42 #define EXT_CS_BASE         0x01000000
43 #define VECTOR_TABLE_BASE   0xffffff80
44 #define RX62N_CFLASH_BASE   0xfff80000
45 
46 #define RX62N_NR_TMR    2
47 #define RX62N_NR_CMT    2
48 #define RX62N_NR_SCI    6
49 
50 struct RX62NState {
51     /*< private >*/
52     DeviceState parent_obj;
53     /*< public >*/
54 
55     RXCPU cpu;
56     RXICUState icu;
57     RTMRState tmr[RX62N_NR_TMR];
58     RCMTState cmt[RX62N_NR_CMT];
59     RSCIState sci[RX62N_NR_SCI];
60 
61     MemoryRegion *sysmem;
62     bool kernel;
63 
64     MemoryRegion iram;
65     MemoryRegion iomem1;
66     MemoryRegion d_flash;
67     MemoryRegion iomem2;
68     MemoryRegion iomem3;
69     MemoryRegion c_flash;
70 
71     /* Input Clock (XTAL) frequency */
72     uint32_t xtal_freq_hz;
73     /* Peripheral Module Clock frequency */
74     uint32_t pclk_freq_hz;
75 };
76 
77 #endif
78