1 /* Copyright (c) 2013 Atmel Corporation 2 All rights reserved. 3 4 Redistribution and use in source and binary forms, with or without 5 modification, are permitted provided that the following conditions are met: 6 7 * Redistributions of source code must retain the above copyright 8 notice, this list of conditions and the following disclaimer. 9 10 * Redistributions in binary form must reproduce the above copyright 11 notice, this list of conditions and the following disclaimer in 12 the documentation and/or other materials provided with the 13 distribution. 14 15 * Neither the name of the copyright holders nor the names of 16 contributors may be used to endorse or promote products derived 17 from this software without specific prior written permission. 18 19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 POSSIBILITY OF SUCH DAMAGE. */ 30 31 /* $Id: iom128rfr2.h 2460 2014-12-03 05:39:25Z pitchumani $ */ 32 33 /* avr/iom128rfr2.h - definitions for ATmega128RFR2 */ 34 35 #ifndef _AVR_IOM128RFR2_H_ 36 #define _AVR_IOM128RFR2_H_ 1 37 38 /* This file should only be included from <avr/io.h>, never directly. */ 39 40 #ifndef _AVR_IO_H_ 41 # error "Include <avr/io.h> instead of this file." 42 #endif 43 44 #ifndef _AVR_IOXXX_H_ 45 # define _AVR_IOXXX_H_ "iom128rfr2.h" 46 #else 47 # error "Attempt to include more than one <avr/ioXXX.h> file." 48 #endif 49 50 #include <avr/sfr_defs.h> 51 52 #ifndef __ASSEMBLER__ 53 # define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) 54 # define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) 55 # define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) 56 #endif /* __ASSEMBLER__ */ 57 58 /* 59 * USAGE: 60 * 61 * simple register assignment: 62 * TIFR1 = 0x17 63 * subregister assignment: 64 * TIFR1_struct.ocf1a = 1 65 * (subregister names are converted to small letters) 66 */ 67 68 69 /* Port A Input Pins Address */ 70 #define PINA _SFR_IO8(0x00) 71 72 /* PINA */ 73 74 #define PINA0 0 75 #define PINA1 1 76 #define PINA2 2 77 #define PINA3 3 78 #define PINA4 4 79 #define PINA5 5 80 #define PINA6 6 81 #define PINA7 7 82 83 /* Port A Data Direction Register */ 84 #define DDRA _SFR_IO8(0x01) 85 86 /* DDRA */ 87 88 #define DDA0 0 89 #define DDA1 1 90 #define DDA2 2 91 #define DDA3 3 92 #define DDA4 4 93 #define DDA5 5 94 #define DDA6 6 95 #define DDA7 7 96 97 /* Port A Data Register */ 98 #define PORTA _SFR_IO8(0x02) 99 100 /* PORTA */ 101 102 #define PORTA0 0 103 #define PA0 0 104 #define PORTA1 1 105 #define PA1 1 106 #define PORTA2 2 107 #define PA2 2 108 #define PORTA3 3 109 #define PA3 3 110 #define PORTA4 4 111 #define PA4 4 112 #define PORTA5 5 113 #define PA5 5 114 #define PORTA6 6 115 #define PA6 6 116 #define PORTA7 7 117 #define PA7 7 118 119 /* Port B Input Pins Address */ 120 #define PINB _SFR_IO8(0x03) 121 122 /* PINB */ 123 124 #define PINB0 0 125 #define PINB1 1 126 #define PINB2 2 127 #define PINB3 3 128 #define PINB4 4 129 #define PINB5 5 130 #define PINB6 6 131 #define PINB7 7 132 133 /* Port B Data Direction Register */ 134 #define DDRB _SFR_IO8(0x04) 135 136 /* DDRB */ 137 138 #define DDB0 0 139 #define DDB1 1 140 #define DDB2 2 141 #define DDB3 3 142 #define DDB4 4 143 #define DDB5 5 144 #define DDB6 6 145 #define DDB7 7 146 147 /* Port B Data Register */ 148 #define PORTB _SFR_IO8(0x05) 149 150 /* PORTB */ 151 152 #define PORTB0 0 153 #define PB0 0 154 #define PORTB1 1 155 #define PB1 1 156 #define PORTB2 2 157 #define PB2 2 158 #define PORTB3 3 159 #define PB3 3 160 #define PORTB4 4 161 #define PB4 4 162 #define PORTB5 5 163 #define PB5 5 164 #define PORTB6 6 165 #define PB6 6 166 #define PORTB7 7 167 #define PB7 7 168 169 /* Port C Input Pins Address */ 170 #define PINC _SFR_IO8(0x06) 171 172 /* PINC */ 173 174 #define PINC0 0 175 #define PINC1 1 176 #define PINC2 2 177 #define PINC3 3 178 #define PINC4 4 179 #define PINC5 5 180 #define PINC6 6 181 #define PINC7 7 182 183 /* Port C Data Direction Register */ 184 #define DDRC _SFR_IO8(0x07) 185 186 /* DDRC */ 187 188 #define DDC0 0 189 #define DDC1 1 190 #define DDC2 2 191 #define DDC3 3 192 #define DDC4 4 193 #define DDC5 5 194 #define DDC6 6 195 #define DDC7 7 196 197 /* Port C Data Register */ 198 #define PORTC _SFR_IO8(0x08) 199 200 /* PORTC */ 201 202 #define PORTC0 0 203 #define PC0 0 204 #define PORTC1 1 205 #define PC1 1 206 #define PORTC2 2 207 #define PC2 2 208 #define PORTC3 3 209 #define PC3 3 210 #define PORTC4 4 211 #define PC4 4 212 #define PORTC5 5 213 #define PC5 5 214 #define PORTC6 6 215 #define PC6 6 216 #define PORTC7 7 217 #define PC7 7 218 219 /* Port D Input Pins Address */ 220 #define PIND _SFR_IO8(0x09) 221 222 /* PIND */ 223 224 #define PIND0 0 225 #define PIND1 1 226 #define PIND2 2 227 #define PIND3 3 228 #define PIND4 4 229 #define PIND5 5 230 #define PIND6 6 231 #define PIND7 7 232 233 /* Port D Data Direction Register */ 234 #define DDRD _SFR_IO8(0x0A) 235 236 /* DDRD */ 237 238 #define DDD0 0 239 #define DDD1 1 240 #define DDD2 2 241 #define DDD3 3 242 #define DDD4 4 243 #define DDD5 5 244 #define DDD6 6 245 #define DDD7 7 246 247 /* Port D Data Register */ 248 #define PORTD _SFR_IO8(0x0B) 249 250 /* PORTD */ 251 252 #define PORTD0 0 253 #define PD0 0 254 #define PORTD1 1 255 #define PD1 1 256 #define PORTD2 2 257 #define PD2 2 258 #define PORTD3 3 259 #define PD3 3 260 #define PORTD4 4 261 #define PD4 4 262 #define PORTD5 5 263 #define PD5 5 264 #define PORTD6 6 265 #define PD6 6 266 #define PORTD7 7 267 #define PD7 7 268 269 /* Port E Input Pins Address */ 270 #define PINE _SFR_IO8(0x0C) 271 272 /* PINE */ 273 274 #define PINE0 0 275 #define PINE1 1 276 #define PINE2 2 277 #define PINE3 3 278 #define PINE4 4 279 #define PINE5 5 280 #define PINE6 6 281 #define PINE7 7 282 283 /* Port E Data Direction Register */ 284 #define DDRE _SFR_IO8(0x0D) 285 286 /* DDRE */ 287 288 #define DDE0 0 289 #define DDE1 1 290 #define DDE2 2 291 #define DDE3 3 292 #define DDE4 4 293 #define DDE5 5 294 #define DDE6 6 295 #define DDE7 7 296 297 /* Port E Data Register */ 298 #define PORTE _SFR_IO8(0x0E) 299 300 /* PORTE */ 301 302 #define PORTE0 0 303 #define PE0 0 304 #define PORTE1 1 305 #define PE1 1 306 #define PORTE2 2 307 #define PE2 2 308 #define PORTE3 3 309 #define PE3 3 310 #define PORTE4 4 311 #define PE4 4 312 #define PORTE5 5 313 #define PE5 5 314 #define PORTE6 6 315 #define PE6 6 316 #define PORTE7 7 317 #define PE7 7 318 319 /* Port F Input Pins Address */ 320 #define PINF _SFR_IO8(0x0F) 321 322 /* PINF */ 323 324 #define PINF0 0 325 #define PINF1 1 326 #define PINF2 2 327 #define PINF3 3 328 #define PINF4 4 329 #define PINF5 5 330 #define PINF6 6 331 #define PINF7 7 332 333 /* Port F Data Direction Register */ 334 #define DDRF _SFR_IO8(0x10) 335 336 /* DDRF */ 337 338 #define DDF0 0 339 #define DDF1 1 340 #define DDF2 2 341 #define DDF3 3 342 #define DDF4 4 343 #define DDF5 5 344 #define DDF6 6 345 #define DDF7 7 346 347 /* Port F Data Register */ 348 #define PORTF _SFR_IO8(0x11) 349 350 /* PORTF */ 351 352 #define PORTF0 0 353 #define PF0 0 354 #define PORTF1 1 355 #define PF1 1 356 #define PORTF2 2 357 #define PF2 2 358 #define PORTF3 3 359 #define PF3 3 360 #define PORTF4 4 361 #define PF4 4 362 #define PORTF5 5 363 #define PF5 5 364 #define PORTF6 6 365 #define PF6 6 366 #define PORTF7 7 367 #define PF7 7 368 369 /* Port G Input Pins Address */ 370 #define PING _SFR_IO8(0x12) 371 372 /* PING */ 373 374 #define PING0 0 375 #define PING1 1 376 #define PING2 2 377 #define PING3 3 378 #define PING4 4 379 #define PING5 5 380 381 /* Port G Data Direction Register */ 382 #define DDRG _SFR_IO8(0x13) 383 384 /* DDRG */ 385 386 #define DDG0 0 387 #define DDG1 1 388 #define DDG2 2 389 #define DDG3 3 390 #define DDG4 4 391 #define DDG5 5 392 393 /* Port G Data Register */ 394 #define PORTG _SFR_IO8(0x14) 395 396 /* PORTG */ 397 398 #define PORTG0 0 399 #define PG0 0 400 #define PORTG1 1 401 #define PG1 1 402 #define PORTG2 2 403 #define PG2 2 404 #define PORTG3 3 405 #define PG3 3 406 #define PORTG4 4 407 #define PG4 4 408 #define PORTG5 5 409 #define PG5 5 410 411 /* Timer/Counter0 Interrupt Flag Register */ 412 #define TIFR0 _SFR_IO8(0x15) 413 414 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 415 416 struct __reg_TIFR0 { 417 unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ 418 unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ 419 unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ 420 unsigned int : 5; 421 }; 422 423 #define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) 424 425 #endif /* __ASSEMBLER__ */ 426 427 /* TIFR0 */ 428 429 #define TOV0 0 430 #define OCF0A 1 431 #define OCF0B 2 432 433 /* Timer/Counter1 Interrupt Flag Register */ 434 #define TIFR1 _SFR_IO8(0x16) 435 436 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 437 438 struct __reg_TIFR1 { 439 unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ 440 unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ 441 unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ 442 unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ 443 unsigned int : 1; 444 unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ 445 unsigned int : 2; 446 }; 447 448 #define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) 449 450 #endif /* __ASSEMBLER__ */ 451 452 /* TIFR1 */ 453 454 #define TOV1 0 455 #define OCF1A 1 456 #define OCF1B 2 457 #define OCF1C 3 458 #define ICF1 5 459 460 /* Timer/Counter Interrupt Flag Register */ 461 #define TIFR2 _SFR_IO8(0x17) 462 463 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 464 465 struct __reg_TIFR2 { 466 unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ 467 unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ 468 unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ 469 unsigned int : 5; 470 }; 471 472 #define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) 473 474 #endif /* __ASSEMBLER__ */ 475 476 /* TIFR2 */ 477 478 #define TOV2 0 479 #define OCF2A 1 480 #define OCF2B 2 481 482 /* Timer/Counter3 Interrupt Flag Register */ 483 #define TIFR3 _SFR_IO8(0x18) 484 485 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 486 487 struct __reg_TIFR3 { 488 unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ 489 unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ 490 unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ 491 unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ 492 unsigned int : 1; 493 unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ 494 unsigned int : 2; 495 }; 496 497 #define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) 498 499 #endif /* __ASSEMBLER__ */ 500 501 /* TIFR3 */ 502 503 #define TOV3 0 504 #define OCF3A 1 505 #define OCF3B 2 506 #define OCF3C 3 507 #define ICF3 5 508 509 /* Timer/Counter4 Interrupt Flag Register */ 510 #define TIFR4 _SFR_IO8(0x19) 511 512 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 513 514 struct __reg_TIFR4 { 515 unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ 516 unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ 517 unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ 518 unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ 519 unsigned int : 1; 520 unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ 521 unsigned int : 2; 522 }; 523 524 #define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) 525 526 #endif /* __ASSEMBLER__ */ 527 528 /* TIFR4 */ 529 530 #define TOV4 0 531 #define OCF4A 1 532 #define OCF4B 2 533 #define OCF4C 3 534 #define ICF4 5 535 536 /* Timer/Counter5 Interrupt Flag Register */ 537 #define TIFR5 _SFR_IO8(0x1A) 538 539 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 540 541 struct __reg_TIFR5 { 542 unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ 543 unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ 544 unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ 545 unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ 546 unsigned int : 1; 547 unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ 548 unsigned int : 2; 549 }; 550 551 #define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) 552 553 #endif /* __ASSEMBLER__ */ 554 555 /* TIFR5 */ 556 557 #define TOV5 0 558 #define OCF5A 1 559 #define OCF5B 2 560 #define OCF5C 3 561 #define ICF5 5 562 563 /* Pin Change Interrupt Flag Register */ 564 #define PCIFR _SFR_IO8(0x1B) 565 566 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 567 568 struct __reg_PCIFR { 569 unsigned int pcif : 3; /* Pin Change Interrupt Flags */ 570 unsigned int : 5; 571 }; 572 573 #define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) 574 575 #endif /* __ASSEMBLER__ */ 576 577 /* PCIFR */ 578 579 #define PCIF0 0 580 #define PCIF1 1 581 #define PCIF2 2 582 583 /* External Interrupt Flag Register */ 584 #define EIFR _SFR_IO8(0x1C) 585 586 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 587 588 struct __reg_EIFR { 589 unsigned int intf : 8; /* External Interrupt Flag */ 590 }; 591 592 #define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) 593 594 #endif /* __ASSEMBLER__ */ 595 596 /* EIFR */ 597 598 #define INTF0 0 599 #define INTF1 1 600 #define INTF2 2 601 #define INTF3 3 602 #define INTF4 4 603 #define INTF5 5 604 #define INTF6 6 605 #define INTF7 7 606 607 /* External Interrupt Mask Register */ 608 #define EIMSK _SFR_IO8(0x1D) 609 610 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 611 612 struct __reg_EIMSK { 613 unsigned int intm : 8; /* External Interrupt Request Enable */ 614 }; 615 616 #define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) 617 618 #endif /* __ASSEMBLER__ */ 619 620 /* EIMSK */ 621 622 #define INT0 0 623 #define INT1 1 624 #define INT2 2 625 #define INT3 3 626 #define INT4 4 627 #define INT5 5 628 #define INT6 6 629 #define INT7 7 630 631 /* General Purpose IO Register 0 */ 632 #define GPIOR0 _SFR_IO8(0x1E) 633 634 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 635 636 struct __reg_GPIOR0 { 637 unsigned int gpior00 : 1; /* General Purpose I/O Register 0 Value */ 638 unsigned int gpior01 : 1; /* General Purpose I/O Register 0 Value */ 639 unsigned int gpior02 : 1; /* General Purpose I/O Register 0 Value */ 640 unsigned int gpior03 : 1; /* General Purpose I/O Register 0 Value */ 641 unsigned int gpior04 : 1; /* General Purpose I/O Register 0 Value */ 642 unsigned int gpior05 : 1; /* General Purpose I/O Register 0 Value */ 643 unsigned int gpior06 : 1; /* General Purpose I/O Register 0 Value */ 644 unsigned int gpior07 : 1; /* General Purpose I/O Register 0 Value */ 645 }; 646 647 #define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) 648 649 #endif /* __ASSEMBLER__ */ 650 651 /* GPIOR0 */ 652 653 #define GPIOR00 0 654 #define GPIOR01 1 655 #define GPIOR02 2 656 #define GPIOR03 3 657 #define GPIOR04 4 658 #define GPIOR05 5 659 #define GPIOR06 6 660 #define GPIOR07 7 661 662 /* 6-char sequence denoting where to find the EEPROM registers in memory space. 663 Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM 664 subroutines. 665 First two letters: EECR address. 666 Second two letters: EEDR address. 667 Last two letters: EEAR address. */ 668 669 #define __EEPROM_REG_LOCATIONS__ 1F2021 670 671 /* EEPROM Control Register */ 672 #define EECR _SFR_IO8(0x1F) 673 674 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 675 676 struct __reg_EECR { 677 unsigned int eere : 1; /* EEPROM Read Enable */ 678 unsigned int eepe : 1; /* EEPROM Programming Enable */ 679 unsigned int eempe : 1; /* EEPROM Master Write Enable */ 680 unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ 681 unsigned int eepm : 2; /* EEPROM Programming Mode */ 682 unsigned int : 2; 683 }; 684 685 #define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) 686 687 #endif /* __ASSEMBLER__ */ 688 689 /* EECR */ 690 691 #define EERE 0 692 #define EEPE 1 693 #define EEMPE 2 694 #define EERIE 3 695 #define EEPM0 4 696 #define EEPM1 5 697 698 /* EEPROM Data Register */ 699 #define EEDR _SFR_IO8(0x20) 700 701 /* EEDR */ 702 703 #define EEDR0 0 704 #define EEDR1 1 705 #define EEDR2 2 706 #define EEDR3 3 707 #define EEDR4 4 708 #define EEDR5 5 709 #define EEDR6 6 710 #define EEDR7 7 711 712 /* EEPROM Address Register Bytes */ 713 #define EEAR _SFR_IO16(0x21) 714 #define EEARL _SFR_IO8(0x21) 715 #define EEARH _SFR_IO8(0x22) 716 717 /* General Timer/Counter Control Register */ 718 #define GTCCR _SFR_IO8(0x23) 719 720 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 721 722 struct __reg_GTCCR { 723 unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ 724 unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ 725 unsigned int : 5; 726 unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ 727 }; 728 729 #define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) 730 731 #endif /* __ASSEMBLER__ */ 732 733 /* GTCCR */ 734 735 #define PSRSYNC 0 736 #define PSR10 0 737 #define PSRASY 1 738 #define PSR2 1 739 #define TSM 7 740 741 /* Timer/Counter0 Control Register A */ 742 #define TCCR0A _SFR_IO8(0x24) 743 744 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 745 746 struct __reg_TCCR0A { 747 unsigned int wgm0 : 2; /* Waveform Generation Mode */ 748 unsigned int : 2; 749 unsigned int com0b : 2; /* Compare Match Output B Mode */ 750 unsigned int com0a : 2; /* Compare Match Output A Mode */ 751 }; 752 753 #define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) 754 755 #endif /* __ASSEMBLER__ */ 756 757 /* TCCR0A */ 758 759 #define WGM00 0 760 #define WGM01 1 761 #define COM0B0 4 762 #define COM0B1 5 763 #define COM0A0 6 764 #define COM0A1 7 765 766 /* Timer/Counter0 Control Register B */ 767 #define TCCR0B _SFR_IO8(0x25) 768 769 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 770 771 struct __reg_TCCR0B { 772 unsigned int cs0 : 3; /* Clock Select */ 773 unsigned int wgm02 : 1; /* Waveform Generation Mode */ 774 unsigned int : 2; 775 unsigned int foc0b : 1; /* Force Output Compare B */ 776 unsigned int foc0a : 1; /* Force Output Compare A */ 777 }; 778 779 #define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) 780 781 #endif /* __ASSEMBLER__ */ 782 783 /* TCCR0B */ 784 785 #define CS00 0 786 #define CS01 1 787 #define CS02 2 788 #define WGM02 3 789 #define FOC0B 6 790 #define FOC0A 7 791 792 /* Timer/Counter0 Register */ 793 #define TCNT0 _SFR_IO8(0x26) 794 795 /* TCNT0 */ 796 797 #define TCNT0_0 0 798 #define TCNT0_1 1 799 #define TCNT0_2 2 800 #define TCNT0_3 3 801 #define TCNT0_4 4 802 #define TCNT0_5 5 803 #define TCNT0_6 6 804 #define TCNT0_7 7 805 806 /* Timer/Counter0 Output Compare Register */ 807 #define OCR0A _SFR_IO8(0x27) 808 809 /* OCR0A */ 810 811 #define OCR0A_0 0 812 #define OCR0A_1 1 813 #define OCR0A_2 2 814 #define OCR0A_3 3 815 #define OCR0A_4 4 816 #define OCR0A_5 5 817 #define OCR0A_6 6 818 #define OCR0A_7 7 819 820 /* Timer/Counter0 Output Compare Register B */ 821 #define OCR0B _SFR_IO8(0x28) 822 823 /* OCR0B */ 824 825 #define OCR0B_0 0 826 #define OCR0B_1 1 827 #define OCR0B_2 2 828 #define OCR0B_3 3 829 #define OCR0B_4 4 830 #define OCR0B_5 5 831 #define OCR0B_6 6 832 #define OCR0B_7 7 833 834 /* General Purpose IO Register 1 */ 835 #define GPIOR1 _SFR_IO8(0x2A) 836 837 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 838 839 struct __reg_GPIOR1 { 840 unsigned int gpior : 8; /* General Purpose I/O Register 1 Value */ 841 }; 842 843 #define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) 844 845 #endif /* __ASSEMBLER__ */ 846 847 /* GPIOR1 */ 848 849 #define GPIOR10 0 850 #define GPIOR11 1 851 #define GPIOR12 2 852 #define GPIOR13 3 853 #define GPIOR14 4 854 #define GPIOR15 5 855 #define GPIOR16 6 856 #define GPIOR17 7 857 858 /* General Purpose I/O Register 2 */ 859 #define GPIOR2 _SFR_IO8(0x2B) 860 861 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 862 863 struct __reg_GPIOR2 { 864 unsigned int gpior : 8; /* General Purpose I/O Register 2 Value */ 865 }; 866 867 #define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) 868 869 #endif /* __ASSEMBLER__ */ 870 871 /* GPIOR2 */ 872 873 #define GPIOR20 0 874 #define GPIOR21 1 875 #define GPIOR22 2 876 #define GPIOR23 3 877 #define GPIOR24 4 878 #define GPIOR25 5 879 #define GPIOR26 6 880 #define GPIOR27 7 881 882 /* SPI Control Register */ 883 #define SPCR _SFR_IO8(0x2C) 884 885 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 886 887 struct __reg_SPCR { 888 unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ 889 unsigned int cpha : 1; /* Clock Phase */ 890 unsigned int cpol : 1; /* Clock polarity */ 891 unsigned int mstr : 1; /* Master/Slave Select */ 892 unsigned int dord : 1; /* Data Order */ 893 unsigned int spe : 1; /* SPI Enable */ 894 unsigned int spie : 1; /* SPI Interrupt Enable */ 895 }; 896 897 #define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) 898 899 #endif /* __ASSEMBLER__ */ 900 901 /* SPCR */ 902 903 #define SPR0 0 904 #define SPR1 1 905 #define CPHA 2 906 #define CPOL 3 907 #define MSTR 4 908 #define DORD 5 909 #define SPE 6 910 #define SPIE 7 911 912 /* SPI Status Register */ 913 #define SPSR _SFR_IO8(0x2D) 914 915 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 916 917 struct __reg_SPSR { 918 unsigned int spi2x : 1; /* Double SPI Speed Bit */ 919 unsigned int : 5; 920 unsigned int wcol : 1; /* Write Collision Flag */ 921 unsigned int spif : 1; /* SPI Interrupt Flag */ 922 }; 923 924 #define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) 925 926 #endif /* __ASSEMBLER__ */ 927 928 /* SPSR */ 929 930 #define SPI2X 0 931 #define WCOL 6 932 #define SPIF 7 933 934 /* SPI Data Register */ 935 #define SPDR _SFR_IO8(0x2E) 936 937 /* SPDR */ 938 939 #define SPDR0 0 940 #define SPDR1 1 941 #define SPDR2 2 942 #define SPDR3 3 943 #define SPDR4 4 944 #define SPDR5 5 945 #define SPDR6 6 946 #define SPDR7 7 947 948 /* Analog Comparator Control And Status Register */ 949 #define ACSR _SFR_IO8(0x30) 950 951 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 952 953 struct __reg_ACSR { 954 unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ 955 unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ 956 unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ 957 unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ 958 unsigned int aco : 1; /* Analog Compare Output */ 959 unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ 960 unsigned int acd : 1; /* Analog Comparator Disable */ 961 }; 962 963 #define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) 964 965 #endif /* __ASSEMBLER__ */ 966 967 /* ACSR */ 968 969 #define ACIS0 0 970 #define ACIS1 1 971 #define ACIC 2 972 #define ACIE 3 973 #define ACI 4 974 #define ACO 5 975 #define ACBG 6 976 #define ACD 7 977 978 /* On-Chip Debug Register */ 979 #define OCDR _SFR_IO8(0x31) 980 981 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 982 983 struct __reg_OCDR { 984 unsigned int ocdr : 8; /* On-Chip Debug Register Data */ 985 }; 986 987 #define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) 988 989 #endif /* __ASSEMBLER__ */ 990 991 /* OCDR */ 992 993 #define OCDR0 0 994 #define OCDR1 1 995 #define OCDR2 2 996 #define OCDR3 3 997 #define OCDR4 4 998 #define OCDR5 5 999 #define OCDR6 6 1000 #define OCDR7 7 1001 #define IDRD 7 1002 1003 /* Sleep Mode Control Register */ 1004 #define SMCR _SFR_IO8(0x33) 1005 1006 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1007 1008 struct __reg_SMCR { 1009 unsigned int se : 1; /* Sleep Enable */ 1010 unsigned int sm : 3; /* Sleep Mode Select bits */ 1011 unsigned int : 4; 1012 }; 1013 1014 #define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) 1015 1016 #endif /* __ASSEMBLER__ */ 1017 1018 /* SMCR */ 1019 1020 #define SE 0 1021 #define SM0 1 1022 #define SM1 2 1023 #define SM2 3 1024 1025 /* MCU Status Register */ 1026 #define MCUSR _SFR_IO8(0x34) 1027 1028 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1029 1030 struct __reg_MCUSR { 1031 unsigned int porf : 1; /* Power-on Reset Flag */ 1032 unsigned int extrf : 1; /* External Reset Flag */ 1033 unsigned int borf : 1; /* Brown-out Reset Flag */ 1034 unsigned int wdrf : 1; /* Watchdog Reset Flag */ 1035 unsigned int jtrf : 1; /* JTAG Reset Flag */ 1036 unsigned int : 3; 1037 }; 1038 1039 #define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) 1040 1041 #endif /* __ASSEMBLER__ */ 1042 1043 /* MCUSR */ 1044 1045 #define PORF 0 1046 #define EXTRF 1 1047 #define BORF 2 1048 #define WDRF 3 1049 #define JTRF 4 1050 1051 /* MCU Control Register */ 1052 #define MCUCR _SFR_IO8(0x35) 1053 1054 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1055 1056 struct __reg_MCUCR { 1057 unsigned int ivce : 1; /* Interrupt Vector Change Enable */ 1058 unsigned int ivsel : 1; /* Interrupt Vector Select */ 1059 unsigned int : 2; 1060 unsigned int pud : 1; /* Pull-up Disable */ 1061 unsigned int : 2; 1062 unsigned int jtd : 1; /* JTAG Interface Disable */ 1063 }; 1064 1065 #define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) 1066 1067 #endif /* __ASSEMBLER__ */ 1068 1069 /* MCUCR */ 1070 1071 #define IVCE 0 1072 #define IVSEL 1 1073 #define PUD 4 1074 #define JTD 7 1075 1076 /* Store Program Memory Control Register */ 1077 #define SPMCSR _SFR_IO8(0x37) 1078 1079 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1080 1081 struct __reg_SPMCSR { 1082 unsigned int spmen : 1; /* Store Program Memory Enable */ 1083 unsigned int pgers : 1; /* Page Erase */ 1084 unsigned int pgwrt : 1; /* Page Write */ 1085 unsigned int blbset : 1; /* Boot Lock Bit Set */ 1086 unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ 1087 unsigned int sigrd : 1; /* Signature Row Read */ 1088 unsigned int rwwsb : 1; /* Read While Write Section Busy */ 1089 unsigned int spmie : 1; /* SPM Interrupt Enable */ 1090 }; 1091 1092 #define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) 1093 1094 #endif /* __ASSEMBLER__ */ 1095 1096 /* SPMCSR */ 1097 1098 #define SPMEN 0 1099 #define PGERS 1 1100 #define PGWRT 2 1101 #define BLBSET 3 1102 #define RWWSRE 4 1103 #define SIGRD 5 1104 #define RWWSB 6 1105 #define SPMIE 7 1106 1107 /* Extended Z-pointer Register for ELPM/SPM */ 1108 #define RAMPZ _SFR_IO8(0x3B) 1109 1110 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1111 1112 struct __reg_RAMPZ { 1113 unsigned int rampz0 : 1; /* Extended Z-Pointer Value */ 1114 unsigned int : 7; 1115 }; 1116 1117 #define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ) 1118 1119 #endif /* __ASSEMBLER__ */ 1120 1121 /* RAMPZ */ 1122 1123 #define RAMPZ0 0 1124 1125 /* Stack Pointer */ 1126 #define SP _SFR_IO16(0x3D) 1127 #define SPL _SFR_IO8(0x3D) 1128 #define SPH _SFR_IO8(0x3E) 1129 1130 /* Status Register */ 1131 #define SREG _SFR_IO8(0x3F) 1132 1133 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1134 1135 struct __reg_SREG { 1136 unsigned int c : 1; /* Carry Flag */ 1137 unsigned int z : 1; /* Zero Flag */ 1138 unsigned int n : 1; /* Negative Flag */ 1139 unsigned int v : 1; /* Two's Complement Overflow Flag */ 1140 unsigned int s : 1; /* Sign Bit */ 1141 unsigned int h : 1; /* Half Carry Flag */ 1142 unsigned int t : 1; /* Bit Copy Storage */ 1143 unsigned int i : 1; /* Global Interrupt Enable */ 1144 }; 1145 1146 #define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) 1147 1148 #endif /* __ASSEMBLER__ */ 1149 1150 /* SREG */ 1151 1152 #define SREG_C 0 1153 #define SREG_Z 1 1154 #define SREG_N 2 1155 #define SREG_V 3 1156 #define SREG_S 4 1157 #define SREG_H 5 1158 #define SREG_T 6 1159 #define SREG_I 7 1160 1161 /* Watchdog Timer Control Register */ 1162 #define WDTCSR _SFR_MEM8(0x60) 1163 1164 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1165 1166 struct __reg_WDTCSR { 1167 unsigned int wdp : 3; /* Watchdog Timer Prescaler Bits */ 1168 unsigned int wde : 1; /* Watch Dog Enable */ 1169 unsigned int wdce : 1; /* Watchdog Change Enable */ 1170 unsigned int : 1; 1171 unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ 1172 unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ 1173 }; 1174 1175 #define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) 1176 1177 #endif /* __ASSEMBLER__ */ 1178 1179 /* WDTCSR */ 1180 1181 #define WDP0 0 1182 #define WDP1 1 1183 #define WDP2 2 1184 #define WDE 3 1185 #define WDCE 4 1186 #define WDP3 5 1187 #define WDIE 6 1188 #define WDIF 7 1189 1190 /* Clock Prescale Register */ 1191 #define CLKPR _SFR_MEM8(0x61) 1192 1193 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1194 1195 struct __reg_CLKPR { 1196 unsigned int clkps : 4; /* Clock Prescaler Select Bits */ 1197 unsigned int : 3; 1198 unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ 1199 }; 1200 1201 #define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) 1202 1203 #endif /* __ASSEMBLER__ */ 1204 1205 /* CLKPR */ 1206 1207 #define CLKPS0 0 1208 #define CLKPS1 1 1209 #define CLKPS2 2 1210 #define CLKPS3 3 1211 #define CLKPCE 7 1212 1213 /* Power Reduction Register 2 */ 1214 #define PRR2 _SFR_MEM8(0x63) 1215 1216 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1217 1218 struct __reg_PRR2 { 1219 unsigned int prram : 4; /* Power Reduction SRAMs */ 1220 unsigned int : 4; 1221 }; 1222 1223 #define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) 1224 1225 #endif /* __ASSEMBLER__ */ 1226 1227 /* PRR2 */ 1228 1229 #define PRRAM0 0 1230 #define PRRAM1 1 1231 #define PRRAM2 2 1232 #define PRRAM3 3 1233 1234 #define __AVR_HAVE_PRR2 ((1<<PRRAM0)|(1<<PRRAM1)|(1<<PRRAM2)|(1<<PRRAM3)) 1235 #define __AVR_HAVE_PRR2_PRRAM0 1236 #define __AVR_HAVE_PRR2_PRRAM1 1237 #define __AVR_HAVE_PRR2_PRRAM2 1238 #define __AVR_HAVE_PRR2_PRRAM3 1239 1240 /* Power Reduction Register0 */ 1241 #define PRR0 _SFR_MEM8(0x64) 1242 1243 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1244 1245 struct __reg_PRR0 { 1246 unsigned int pradc : 1; /* Power Reduction ADC */ 1247 unsigned int prusart0 : 1; /* Power Reduction USART */ 1248 unsigned int prspi : 1; /* Power Reduction Serial Peripheral Interface */ 1249 unsigned int prtim1 : 1; /* Power Reduction Timer/Counter1 */ 1250 unsigned int prpga : 1; /* Power Reduction PGA */ 1251 unsigned int prtim0 : 1; /* Power Reduction Timer/Counter0 */ 1252 unsigned int prtim2 : 1; /* Power Reduction Timer/Counter2 */ 1253 unsigned int prtwi : 1; /* Power Reduction TWI */ 1254 }; 1255 1256 #define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0) 1257 1258 #endif /* __ASSEMBLER__ */ 1259 1260 /* PRR0 */ 1261 1262 #define PRADC 0 1263 #define PRUSART0 1 1264 #define PRSPI 2 1265 #define PRTIM1 3 1266 #define PRPGA 4 1267 #define PRTIM0 5 1268 #define PRTIM2 6 1269 #define PRTWI 7 1270 1271 #define __AVR_HAVE_PRR0 ((1<<PRADC)|(1<<PRUSART0)|(1<<PRSPI)|(1<<PRTIM1)|(1<<PRPGA)|(1<<PRTIM0)|(1<<PRTIM2)|(1<<PRTWI)) 1272 #define __AVR_HAVE_PRR0_PRADC 1273 #define __AVR_HAVE_PRR0_PRUSART0 1274 #define __AVR_HAVE_PRR0_PRSPI 1275 #define __AVR_HAVE_PRR0_PRTIM1 1276 #define __AVR_HAVE_PRR0_PRPGA 1277 #define __AVR_HAVE_PRR0_PRTIM0 1278 #define __AVR_HAVE_PRR0_PRTIM2 1279 #define __AVR_HAVE_PRR0_PRTWI 1280 1281 /* Power Reduction Register 1 */ 1282 #define PRR1 _SFR_MEM8(0x65) 1283 1284 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1285 1286 struct __reg_PRR1 { 1287 unsigned int prusart1 : 1; /* Power Reduction USART1 */ 1288 unsigned int : 2; 1289 unsigned int prtim3 : 1; /* Power Reduction Timer/Counter3 */ 1290 unsigned int prtim4 : 1; /* Power Reduction Timer/Counter4 */ 1291 unsigned int prtim5 : 1; /* Power Reduction Timer/Counter5 */ 1292 unsigned int prtrx24 : 1; /* Power Reduction Transceiver */ 1293 unsigned int : 1; 1294 }; 1295 1296 #define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1) 1297 1298 #endif /* __ASSEMBLER__ */ 1299 1300 /* PRR1 */ 1301 1302 #define PRUSART1 0 1303 #define PRTIM3 3 1304 #define PRTIM4 4 1305 #define PRTIM5 5 1306 #define PRTRX24 6 1307 1308 #define __AVR_HAVE_PRR1 ((1<<PRUSART1)|(1<<PRTIM3)|(1<<PRTIM4)|(1<<PRTIM5)|(1<<PRTRX24)) 1309 #define __AVR_HAVE_PRR1_PRUSART1 1310 #define __AVR_HAVE_PRR1_PRTIM3 1311 #define __AVR_HAVE_PRR1_PRTIM4 1312 #define __AVR_HAVE_PRR1_PRTIM5 1313 #define __AVR_HAVE_PRR1_PRTRX24 1314 1315 /* Oscillator Calibration Value */ 1316 #define OSCCAL _SFR_MEM8(0x66) 1317 1318 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1319 1320 struct __reg_OSCCAL { 1321 unsigned int cal : 8; /* Oscillator Calibration Tuning Value */ 1322 }; 1323 1324 #define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL) 1325 1326 #endif /* __ASSEMBLER__ */ 1327 1328 /* OSCCAL */ 1329 1330 #define CAL0 0 1331 #define CAL1 1 1332 #define CAL2 2 1333 #define CAL3 3 1334 #define CAL4 4 1335 #define CAL5 5 1336 #define CAL6 6 1337 #define CAL7 7 1338 1339 /* Reference Voltage Calibration Register */ 1340 #define BGCR _SFR_MEM8(0x67) 1341 1342 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1343 1344 struct __reg_BGCR { 1345 unsigned int bgcal : 3; /* Coarse Calibration Bits */ 1346 unsigned int bgcal_fine : 4; /* Fine Calibration Bits */ 1347 unsigned int : 1; 1348 }; 1349 1350 #define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR) 1351 1352 #endif /* __ASSEMBLER__ */ 1353 1354 /* BGCR */ 1355 1356 #define BGCAL0 0 1357 #define BGCAL1 1 1358 #define BGCAL2 2 1359 #define BGCAL_FINE0 3 1360 #define BGCAL_FINE1 4 1361 #define BGCAL_FINE2 5 1362 #define BGCAL_FINE3 6 1363 1364 /* Pin Change Interrupt Control Register */ 1365 #define PCICR _SFR_MEM8(0x68) 1366 1367 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1368 1369 struct __reg_PCICR { 1370 unsigned int pcie : 3; /* Pin Change Interrupt Enables */ 1371 unsigned int : 5; 1372 }; 1373 1374 #define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR) 1375 1376 #endif /* __ASSEMBLER__ */ 1377 1378 /* PCICR */ 1379 1380 #define PCIE0 0 1381 #define PCIE1 1 1382 #define PCIE2 2 1383 1384 /* External Interrupt Control Register A */ 1385 #define EICRA _SFR_MEM8(0x69) 1386 1387 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1388 1389 struct __reg_EICRA { 1390 unsigned int isc0 : 2; /* External Interrupt 0 Sense Control Bit */ 1391 unsigned int isc1 : 2; /* External Interrupt 1 Sense Control Bit */ 1392 unsigned int isc2 : 2; /* External Interrupt 2 Sense Control Bit */ 1393 unsigned int isc3 : 2; /* External Interrupt 3 Sense Control Bit */ 1394 }; 1395 1396 #define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA) 1397 1398 #endif /* __ASSEMBLER__ */ 1399 1400 /* EICRA */ 1401 1402 #define ISC00 0 1403 #define ISC01 1 1404 #define ISC10 2 1405 #define ISC11 3 1406 #define ISC20 4 1407 #define ISC21 5 1408 #define ISC30 6 1409 #define ISC31 7 1410 1411 /* External Interrupt Control Register B */ 1412 #define EICRB _SFR_MEM8(0x6A) 1413 1414 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1415 1416 struct __reg_EICRB { 1417 unsigned int isc4 : 2; /* External Interrupt 4 Sense Control Bit */ 1418 unsigned int isc5 : 2; /* External Interrupt 5 Sense Control Bit */ 1419 unsigned int isc6 : 2; /* External Interrupt 6 Sense Control Bit */ 1420 unsigned int isc7 : 2; /* External Interrupt 7 Sense Control Bit */ 1421 }; 1422 1423 #define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB) 1424 1425 #endif /* __ASSEMBLER__ */ 1426 1427 /* EICRB */ 1428 1429 #define ISC40 0 1430 #define ISC41 1 1431 #define ISC50 2 1432 #define ISC51 3 1433 #define ISC60 4 1434 #define ISC61 5 1435 #define ISC70 6 1436 #define ISC71 7 1437 1438 /* Pin Change Mask Register 0 */ 1439 #define PCMSK0 _SFR_MEM8(0x6B) 1440 1441 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1442 1443 struct __reg_PCMSK0 { 1444 unsigned int pcint : 8; /* Pin Change Enable Mask */ 1445 }; 1446 1447 #define PCMSK0_struct _SFR_MEM8_STRUCT(0x6b, struct __reg_PCMSK0) 1448 1449 #endif /* __ASSEMBLER__ */ 1450 1451 /* PCMSK0 */ 1452 1453 #define PCINT0 0 1454 #define PCINT1 1 1455 #define PCINT2 2 1456 #define PCINT3 3 1457 #define PCINT4 4 1458 #define PCINT5 5 1459 #define PCINT6 6 1460 #define PCINT7 7 1461 1462 /* Pin Change Mask Register 1 */ 1463 #define PCMSK1 _SFR_MEM8(0x6C) 1464 1465 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1466 1467 struct __reg_PCMSK1 { 1468 unsigned int pcint : 8; /* Pin Change Enable Mask */ 1469 }; 1470 1471 #define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1) 1472 1473 #endif /* __ASSEMBLER__ */ 1474 1475 /* PCMSK1 */ 1476 1477 #define PCINT8 0 1478 #define PCINT9 1 1479 #define PCINT10 2 1480 #define PCINT11 3 1481 #define PCINT12 4 1482 #define PCINT13 5 1483 #define PCINT14 6 1484 #define PCINT15 7 1485 1486 /* Pin Change Mask Register 2 */ 1487 #define PCMSK2 _SFR_MEM8(0x6D) 1488 1489 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1490 1491 struct __reg_PCMSK2 { 1492 unsigned int pcint : 8; /* Pin Change Enable Mask */ 1493 }; 1494 1495 #define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2) 1496 1497 #endif /* __ASSEMBLER__ */ 1498 1499 /* PCMSK2 */ 1500 1501 #define PCINT16 0 1502 #define PCINT17 1 1503 #define PCINT18 2 1504 #define PCINT19 3 1505 #define PCINT20 4 1506 #define PCINT21 5 1507 #define PCINT22 6 1508 #define PCINT23 7 1509 1510 /* Timer/Counter0 Interrupt Mask Register */ 1511 #define TIMSK0 _SFR_MEM8(0x6E) 1512 1513 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1514 1515 struct __reg_TIMSK0 { 1516 unsigned int toie0 : 1; /* Timer/Counter0 Overflow Interrupt Enable */ 1517 unsigned int ocie0a : 1; /* Timer/Counter0 Output Compare Match A Interrupt Enable */ 1518 unsigned int ocie0b : 1; /* Timer/Counter0 Output Compare Match B Interrupt Enable */ 1519 unsigned int : 5; 1520 }; 1521 1522 #define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0) 1523 1524 #endif /* __ASSEMBLER__ */ 1525 1526 /* TIMSK0 */ 1527 1528 #define TOIE0 0 1529 #define OCIE0A 1 1530 #define OCIE0B 2 1531 1532 /* Timer/Counter1 Interrupt Mask Register */ 1533 #define TIMSK1 _SFR_MEM8(0x6F) 1534 1535 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1536 1537 struct __reg_TIMSK1 { 1538 unsigned int toie1 : 1; /* Timer/Counter1 Overflow Interrupt Enable */ 1539 unsigned int ocie1a : 1; /* Timer/Counter1 Output Compare A Match Interrupt Enable */ 1540 unsigned int ocie1b : 1; /* Timer/Counter1 Output Compare B Match Interrupt Enable */ 1541 unsigned int ocie1c : 1; /* Timer/Counter1 Output Compare C Match Interrupt Enable */ 1542 unsigned int : 1; 1543 unsigned int icie1 : 1; /* Timer/Counter1 Input Capture Interrupt Enable */ 1544 unsigned int : 2; 1545 }; 1546 1547 #define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1) 1548 1549 #endif /* __ASSEMBLER__ */ 1550 1551 /* TIMSK1 */ 1552 1553 #define TOIE1 0 1554 #define OCIE1A 1 1555 #define OCIE1B 2 1556 #define OCIE1C 3 1557 #define ICIE1 5 1558 1559 /* Timer/Counter Interrupt Mask register */ 1560 #define TIMSK2 _SFR_MEM8(0x70) 1561 1562 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1563 1564 struct __reg_TIMSK2 { 1565 unsigned int toie2 : 1; /* Timer/Counter2 Overflow Interrupt Enable */ 1566 unsigned int ocie2a : 1; /* Timer/Counter2 Output Compare Match A Interrupt Enable */ 1567 unsigned int ocie2b : 1; /* Timer/Counter2 Output Compare Match B Interrupt Enable */ 1568 unsigned int : 5; 1569 }; 1570 1571 #define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2) 1572 1573 #endif /* __ASSEMBLER__ */ 1574 1575 /* TIMSK2 */ 1576 1577 #define TOIE2 0 1578 #define TOIE2A 0 1579 #define OCIE2A 1 1580 #define OCIE2B 2 1581 1582 /* Timer/Counter3 Interrupt Mask Register */ 1583 #define TIMSK3 _SFR_MEM8(0x71) 1584 1585 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1586 1587 struct __reg_TIMSK3 { 1588 unsigned int toie3 : 1; /* Timer/Counter3 Overflow Interrupt Enable */ 1589 unsigned int ocie3a : 1; /* Timer/Counter3 Output Compare A Match Interrupt Enable */ 1590 unsigned int ocie3b : 1; /* Timer/Counter3 Output Compare B Match Interrupt Enable */ 1591 unsigned int ocie3c : 1; /* Timer/Counter3 Output Compare C Match Interrupt Enable */ 1592 unsigned int : 1; 1593 unsigned int icie3 : 1; /* Timer/Counter3 Input Capture Interrupt Enable */ 1594 unsigned int : 2; 1595 }; 1596 1597 #define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3) 1598 1599 #endif /* __ASSEMBLER__ */ 1600 1601 /* TIMSK3 */ 1602 1603 #define TOIE3 0 1604 #define OCIE3A 1 1605 #define OCIE3B 2 1606 #define OCIE3C 3 1607 #define ICIE3 5 1608 1609 /* Timer/Counter4 Interrupt Mask Register */ 1610 #define TIMSK4 _SFR_MEM8(0x72) 1611 1612 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1613 1614 struct __reg_TIMSK4 { 1615 unsigned int toie4 : 1; /* Timer/Counter4 Overflow Interrupt Enable */ 1616 unsigned int ocie4a : 1; /* Timer/Counter4 Output Compare A Match Interrupt Enable */ 1617 unsigned int ocie4b : 1; /* Timer/Counter4 Output Compare B Match Interrupt Enable */ 1618 unsigned int ocie4c : 1; /* Timer/Counter4 Output Compare C Match Interrupt Enable */ 1619 unsigned int : 1; 1620 unsigned int icie4 : 1; /* Timer/Counter4 Input Capture Interrupt Enable */ 1621 unsigned int : 2; 1622 }; 1623 1624 #define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4) 1625 1626 #endif /* __ASSEMBLER__ */ 1627 1628 /* TIMSK4 */ 1629 1630 #define TOIE4 0 1631 #define OCIE4A 1 1632 #define OCIE4B 2 1633 #define OCIE4C 3 1634 #define ICIE4 5 1635 1636 /* Timer/Counter5 Interrupt Mask Register */ 1637 #define TIMSK5 _SFR_MEM8(0x73) 1638 1639 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1640 1641 struct __reg_TIMSK5 { 1642 unsigned int toie5 : 1; /* Timer/Counter5 Overflow Interrupt Enable */ 1643 unsigned int ocie5a : 1; /* Timer/Counter5 Output Compare A Match Interrupt Enable */ 1644 unsigned int ocie5b : 1; /* Timer/Counter5 Output Compare B Match Interrupt Enable */ 1645 unsigned int ocie5c : 1; /* Timer/Counter5 Output Compare C Match Interrupt Enable */ 1646 unsigned int : 1; 1647 unsigned int icie5 : 1; /* Timer/Counter5 Input Capture Interrupt Enable */ 1648 unsigned int : 2; 1649 }; 1650 1651 #define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5) 1652 1653 #endif /* __ASSEMBLER__ */ 1654 1655 /* TIMSK5 */ 1656 1657 #define TOIE5 0 1658 #define OCIE5A 1 1659 #define OCIE5B 2 1660 #define OCIE5C 3 1661 #define ICIE5 5 1662 1663 /* Flash Extended-Mode Control-Register */ 1664 #define NEMCR _SFR_MEM8(0x75) 1665 1666 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1667 1668 struct __reg_NEMCR { 1669 unsigned int : 4; 1670 unsigned int aeam : 2; /* Address for Extended Address Mode of Extra Rows */ 1671 unsigned int eneam : 1; /* Enable Extended Address Mode for Extra Rows */ 1672 unsigned int : 1; 1673 }; 1674 1675 #define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR) 1676 1677 #endif /* __ASSEMBLER__ */ 1678 1679 /* NEMCR */ 1680 1681 #define AEAM0 4 1682 #define AEAM1 5 1683 #define ENEAM 6 1684 1685 /* The ADC Control and Status Register C */ 1686 #define ADCSRC _SFR_MEM8(0x77) 1687 1688 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1689 1690 struct __reg_ADCSRC { 1691 unsigned int adsut : 5; /* ADC Start-up Time */ 1692 unsigned int res0 : 1; /* Reserved */ 1693 unsigned int adtht : 2; /* ADC Track-and-Hold Time */ 1694 }; 1695 1696 #define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC) 1697 1698 #endif /* __ASSEMBLER__ */ 1699 1700 /* ADCSRC */ 1701 1702 #define ADSUT0 0 1703 #define ADSUT1 1 1704 #define ADSUT2 2 1705 #define ADSUT3 3 1706 #define ADSUT4 4 1707 #define ADTHT0 6 1708 #define ADTHT1 7 1709 1710 /* ADC Data Register Bytes */ 1711 #ifndef __ASSEMBLER__ 1712 #define ADC _SFR_MEM16(0x78) 1713 #define ADCL _SFR_MEM8(0x78) 1714 #define ADCH _SFR_MEM8(0x79) 1715 #endif /* __ASSEMBLER__ */ 1716 #define ADCW _SFR_MEM16(0x78) 1717 #define ADCWL _SFR_MEM8(0x78) 1718 #define ADCWH _SFR_MEM8(0x79) 1719 1720 /* The ADC Control and Status Register A */ 1721 #define ADCSRA _SFR_MEM8(0x7A) 1722 1723 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1724 1725 struct __reg_ADCSRA { 1726 unsigned int adps : 3; /* ADC Prescaler Select Bits */ 1727 unsigned int adie : 1; /* ADC Interrupt Enable */ 1728 unsigned int adif : 1; /* ADC Interrupt Flag */ 1729 unsigned int adate : 1; /* ADC Auto Trigger Enable */ 1730 unsigned int adsc : 1; /* ADC Start Conversion */ 1731 unsigned int aden : 1; /* ADC Enable */ 1732 }; 1733 1734 #define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA) 1735 1736 #endif /* __ASSEMBLER__ */ 1737 1738 /* ADCSRA */ 1739 1740 #define ADPS0 0 1741 #define ADPS1 1 1742 #define ADPS2 2 1743 #define ADIE 3 1744 #define ADIF 4 1745 #define ADATE 5 1746 #define ADSC 6 1747 #define ADEN 7 1748 1749 /* ADC Control and Status Register B */ 1750 #define ADCSRB _SFR_MEM8(0x7B) 1751 1752 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1753 1754 struct __reg_ADCSRB { 1755 unsigned int adts : 3; /* ADC Auto Trigger Source */ 1756 unsigned int mux5 : 1; /* Analog Channel and Gain Selection Bits */ 1757 unsigned int acch : 1; /* Analog Channel Change */ 1758 unsigned int refok : 1; /* Reference Voltage OK */ 1759 unsigned int acme : 1; /* Analog Comparator Multiplexer Enable */ 1760 unsigned int avddok : 1; /* AVDD Supply Voltage OK */ 1761 }; 1762 1763 #define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB) 1764 1765 #endif /* __ASSEMBLER__ */ 1766 1767 /* ADCSRB */ 1768 1769 #define ADTS0 0 1770 #define ADTS1 1 1771 #define ADTS2 2 1772 #define MUX5 3 1773 #define ACCH 4 1774 #define REFOK 5 1775 #define ACME 6 1776 #define AVDDOK 7 1777 1778 /* The ADC Multiplexer Selection Register */ 1779 #define ADMUX _SFR_MEM8(0x7C) 1780 1781 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1782 1783 struct __reg_ADMUX { 1784 unsigned int mux : 5; /* Analog Channel and Gain Selection Bits */ 1785 unsigned int adlar : 1; /* ADC Left Adjust Result */ 1786 unsigned int refs : 2; /* Reference Selection Bits */ 1787 }; 1788 1789 #define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX) 1790 1791 #endif /* __ASSEMBLER__ */ 1792 1793 /* ADMUX */ 1794 1795 #define MUX0 0 1796 #define MUX1 1 1797 #define MUX2 2 1798 #define MUX3 3 1799 #define MUX4 4 1800 #define ADLAR 5 1801 #define REFS0 6 1802 #define REFS1 7 1803 1804 /* Digital Input Disable Register 2 */ 1805 #define DIDR2 _SFR_MEM8(0x7D) 1806 1807 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1808 1809 struct __reg_DIDR2 { 1810 unsigned int adc8d : 1; /* Reserved Bits */ 1811 unsigned int adc9d : 1; /* Reserved Bits */ 1812 unsigned int adc10d : 1; /* Reserved Bits */ 1813 unsigned int adc11d : 1; /* Reserved Bits */ 1814 unsigned int adc12d : 1; /* Reserved Bits */ 1815 unsigned int adc13d : 1; /* Reserved Bits */ 1816 unsigned int adc14d : 1; /* Reserved Bits */ 1817 unsigned int adc15d : 1; /* Reserved Bits */ 1818 }; 1819 1820 #define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2) 1821 1822 #endif /* __ASSEMBLER__ */ 1823 1824 /* DIDR2 */ 1825 1826 #define ADC8D 0 1827 #define ADC9D 1 1828 #define ADC10D 2 1829 #define ADC11D 3 1830 #define ADC12D 4 1831 #define ADC13D 5 1832 #define ADC14D 6 1833 #define ADC15D 7 1834 1835 /* Digital Input Disable Register 0 */ 1836 #define DIDR0 _SFR_MEM8(0x7E) 1837 1838 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1839 1840 struct __reg_DIDR0 { 1841 unsigned int adc0d : 1; /* Disable ADC7:0 Digital Input */ 1842 unsigned int adc1d : 1; /* Disable ADC7:0 Digital Input */ 1843 unsigned int adc2d : 1; /* Disable ADC7:0 Digital Input */ 1844 unsigned int adc3d : 1; /* Disable ADC7:0 Digital Input */ 1845 unsigned int adc4d : 1; /* Disable ADC7:0 Digital Input */ 1846 unsigned int adc5d : 1; /* Disable ADC7:0 Digital Input */ 1847 unsigned int adc6d : 1; /* Disable ADC7:0 Digital Input */ 1848 unsigned int adc7d : 1; /* Disable ADC7:0 Digital Input */ 1849 }; 1850 1851 #define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0) 1852 1853 #endif /* __ASSEMBLER__ */ 1854 1855 /* DIDR0 */ 1856 1857 #define ADC0D 0 1858 #define ADC1D 1 1859 #define ADC2D 2 1860 #define ADC3D 3 1861 #define ADC4D 4 1862 #define ADC5D 5 1863 #define ADC6D 6 1864 #define ADC7D 7 1865 1866 /* Digital Input Disable Register 1 */ 1867 #define DIDR1 _SFR_MEM8(0x7F) 1868 1869 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1870 1871 struct __reg_DIDR1 { 1872 unsigned int ain0d : 1; /* AIN0 Digital Input Disable */ 1873 unsigned int ain1d : 1; /* AIN1 Digital Input Disable */ 1874 unsigned int : 6; 1875 }; 1876 1877 #define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1) 1878 1879 #endif /* __ASSEMBLER__ */ 1880 1881 /* DIDR1 */ 1882 1883 #define AIN0D 0 1884 #define AIN1D 1 1885 1886 /* Timer/Counter1 Control Register A */ 1887 #define TCCR1A _SFR_MEM8(0x80) 1888 1889 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1890 1891 struct __reg_TCCR1A { 1892 unsigned int wgm1 : 2; /* Waveform Generation Mode */ 1893 unsigned int com1c : 2; /* Compare Output Mode for Channel C */ 1894 unsigned int com1b : 2; /* Compare Output Mode for Channel B */ 1895 unsigned int com1a : 2; /* Compare Output Mode for Channel A */ 1896 }; 1897 1898 #define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A) 1899 1900 #endif /* __ASSEMBLER__ */ 1901 1902 /* TCCR1A */ 1903 1904 #define WGM10 0 1905 #define WGM11 1 1906 #define COM1C0 2 1907 #define COM1C1 3 1908 #define COM1B0 4 1909 #define COM1B1 5 1910 #define COM1A0 6 1911 #define COM1A1 7 1912 1913 /* Timer/Counter1 Control Register B */ 1914 #define TCCR1B _SFR_MEM8(0x81) 1915 1916 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1917 1918 struct __reg_TCCR1B { 1919 unsigned int cs1 : 3; /* Clock Select */ 1920 unsigned int wgm1 : 2; /* Waveform Generation Mode */ 1921 unsigned int : 1; 1922 unsigned int ices1 : 1; /* Input Capture 1 Edge Select */ 1923 unsigned int icnc1 : 1; /* Input Capture 1 Noise Canceller */ 1924 }; 1925 1926 #define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B) 1927 1928 #endif /* __ASSEMBLER__ */ 1929 1930 /* TCCR1B */ 1931 1932 #define CS10 0 1933 #define CS11 1 1934 #define CS12 2 1935 #define WGM12 3 1936 #define WGM13 4 1937 #define ICES1 6 1938 #define ICNC1 7 1939 1940 /* Timer/Counter1 Control Register C */ 1941 #define TCCR1C _SFR_MEM8(0x82) 1942 1943 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1944 1945 struct __reg_TCCR1C { 1946 unsigned int : 5; 1947 unsigned int foc1c : 1; /* Force Output Compare for Channel C */ 1948 unsigned int foc1b : 1; /* Force Output Compare for Channel B */ 1949 unsigned int foc1a : 1; /* Force Output Compare for Channel A */ 1950 }; 1951 1952 #define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C) 1953 1954 #endif /* __ASSEMBLER__ */ 1955 1956 /* TCCR1C */ 1957 1958 #define FOC1C 5 1959 #define FOC1B 6 1960 #define FOC1A 7 1961 1962 /* Timer/Counter1 Bytes */ 1963 #define TCNT1 _SFR_MEM16(0x84) 1964 #define TCNT1L _SFR_MEM8(0x84) 1965 #define TCNT1H _SFR_MEM8(0x85) 1966 1967 /* Timer/Counter1 Input Capture Register Bytes */ 1968 #define ICR1 _SFR_MEM16(0x86) 1969 #define ICR1L _SFR_MEM8(0x86) 1970 #define ICR1H _SFR_MEM8(0x87) 1971 1972 /* Timer/Counter1 Output Compare Register A Bytes */ 1973 #define OCR1A _SFR_MEM16(0x88) 1974 #define OCR1AL _SFR_MEM8(0x88) 1975 #define OCR1AH _SFR_MEM8(0x89) 1976 1977 /* Timer/Counter1 Output Compare Register B Bytes */ 1978 #define OCR1B _SFR_MEM16(0x8A) 1979 #define OCR1BL _SFR_MEM8(0x8A) 1980 #define OCR1BH _SFR_MEM8(0x8B) 1981 1982 /* Timer/Counter1 Output Compare Register C Bytes */ 1983 #define OCR1C _SFR_MEM16(0x8C) 1984 #define OCR1CL _SFR_MEM8(0x8C) 1985 #define OCR1CH _SFR_MEM8(0x8D) 1986 1987 /* Timer/Counter3 Control Register A */ 1988 #define TCCR3A _SFR_MEM8(0x90) 1989 1990 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 1991 1992 struct __reg_TCCR3A { 1993 unsigned int wgm3 : 2; /* Waveform Generation Mode */ 1994 unsigned int com3c : 2; /* Compare Output Mode for Channel C */ 1995 unsigned int com3b : 2; /* Compare Output Mode for Channel B */ 1996 unsigned int com3a : 2; /* Compare Output Mode for Channel A */ 1997 }; 1998 1999 #define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A) 2000 2001 #endif /* __ASSEMBLER__ */ 2002 2003 /* TCCR3A */ 2004 2005 #define WGM30 0 2006 #define WGM31 1 2007 #define COM3C0 2 2008 #define COM3C1 3 2009 #define COM3B0 4 2010 #define COM3B1 5 2011 #define COM3A0 6 2012 #define COM3A1 7 2013 2014 /* Timer/Counter3 Control Register B */ 2015 #define TCCR3B _SFR_MEM8(0x91) 2016 2017 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2018 2019 struct __reg_TCCR3B { 2020 unsigned int cs3 : 3; /* Clock Select */ 2021 unsigned int wgm3 : 2; /* Waveform Generation Mode */ 2022 unsigned int : 1; 2023 unsigned int ices3 : 1; /* Input Capture 3 Edge Select */ 2024 unsigned int icnc3 : 1; /* Input Capture 3 Noise Canceller */ 2025 }; 2026 2027 #define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B) 2028 2029 #endif /* __ASSEMBLER__ */ 2030 2031 /* TCCR3B */ 2032 2033 #define CS30 0 2034 #define CS31 1 2035 #define CS32 2 2036 #define WGM32 3 2037 #define WGM33 4 2038 #define ICES3 6 2039 #define ICNC3 7 2040 2041 /* Timer/Counter3 Control Register C */ 2042 #define TCCR3C _SFR_MEM8(0x92) 2043 2044 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2045 2046 struct __reg_TCCR3C { 2047 unsigned int : 5; 2048 unsigned int foc3c : 1; /* Force Output Compare for Channel C */ 2049 unsigned int foc3b : 1; /* Force Output Compare for Channel B */ 2050 unsigned int foc3a : 1; /* Force Output Compare for Channel A */ 2051 }; 2052 2053 #define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C) 2054 2055 #endif /* __ASSEMBLER__ */ 2056 2057 /* TCCR3C */ 2058 2059 #define FOC3C 5 2060 #define FOC3B 6 2061 #define FOC3A 7 2062 2063 /* Timer/Counter3 Bytes */ 2064 #define TCNT3 _SFR_MEM16(0x94) 2065 #define TCNT3L _SFR_MEM8(0x94) 2066 #define TCNT3H _SFR_MEM8(0x95) 2067 2068 /* Timer/Counter3 Input Capture Register Bytes */ 2069 #define ICR3 _SFR_MEM16(0x96) 2070 #define ICR3L _SFR_MEM8(0x96) 2071 #define ICR3H _SFR_MEM8(0x97) 2072 2073 /* Timer/Counter3 Output Compare Register A Bytes */ 2074 #define OCR3A _SFR_MEM16(0x98) 2075 #define OCR3AL _SFR_MEM8(0x98) 2076 #define OCR3AH _SFR_MEM8(0x99) 2077 2078 /* Timer/Counter3 Output Compare Register B Bytes */ 2079 #define OCR3B _SFR_MEM16(0x9A) 2080 #define OCR3BL _SFR_MEM8(0x9A) 2081 #define OCR3BH _SFR_MEM8(0x9B) 2082 2083 /* Timer/Counter3 Output Compare Register C Bytes */ 2084 #define OCR3C _SFR_MEM16(0x9C) 2085 #define OCR3CL _SFR_MEM8(0x9C) 2086 #define OCR3CH _SFR_MEM8(0x9D) 2087 2088 /* Timer/Counter4 Control Register A */ 2089 #define TCCR4A _SFR_MEM8(0xA0) 2090 2091 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2092 2093 struct __reg_TCCR4A { 2094 unsigned int wgm4 : 2; /* Waveform Generation Mode */ 2095 unsigned int com4c : 2; /* Compare Output Mode for Channel C */ 2096 unsigned int com4b : 2; /* Compare Output Mode for Channel B */ 2097 unsigned int com4a : 2; /* Compare Output Mode for Channel A */ 2098 }; 2099 2100 #define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A) 2101 2102 #endif /* __ASSEMBLER__ */ 2103 2104 /* TCCR4A */ 2105 2106 #define WGM40 0 2107 #define WGM41 1 2108 #define COM4C0 2 2109 #define COM4C1 3 2110 #define COM4B0 4 2111 #define COM4B1 5 2112 #define COM4A0 6 2113 #define COM4A1 7 2114 2115 /* Timer/Counter4 Control Register B */ 2116 #define TCCR4B _SFR_MEM8(0xA1) 2117 2118 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2119 2120 struct __reg_TCCR4B { 2121 unsigned int cs4 : 3; /* Clock Select */ 2122 unsigned int wgm4 : 2; /* Waveform Generation Mode */ 2123 unsigned int : 1; 2124 unsigned int ices4 : 1; /* Input Capture 4 Edge Select */ 2125 unsigned int icnc4 : 1; /* Input Capture 4 Noise Canceller */ 2126 }; 2127 2128 #define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B) 2129 2130 #endif /* __ASSEMBLER__ */ 2131 2132 /* TCCR4B */ 2133 2134 #define CS40 0 2135 #define CS41 1 2136 #define CS42 2 2137 #define WGM42 3 2138 #define WGM43 4 2139 #define ICES4 6 2140 #define ICNC4 7 2141 2142 /* Timer/Counter4 Control Register C */ 2143 #define TCCR4C _SFR_MEM8(0xA2) 2144 2145 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2146 2147 struct __reg_TCCR4C { 2148 unsigned int : 5; 2149 unsigned int foc4c : 1; /* Force Output Compare for Channel C */ 2150 unsigned int foc4b : 1; /* Force Output Compare for Channel B */ 2151 unsigned int foc4a : 1; /* Force Output Compare for Channel A */ 2152 }; 2153 2154 #define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C) 2155 2156 #endif /* __ASSEMBLER__ */ 2157 2158 /* TCCR4C */ 2159 2160 #define FOC4C 5 2161 #define FOC4B 6 2162 #define FOC4A 7 2163 2164 /* Timer/Counter4 Bytes */ 2165 #define TCNT4 _SFR_MEM16(0xA4) 2166 #define TCNT4L _SFR_MEM8(0xA4) 2167 #define TCNT4H _SFR_MEM8(0xA5) 2168 2169 /* Timer/Counter4 Input Capture Register Bytes */ 2170 #define ICR4 _SFR_MEM16(0xA6) 2171 #define ICR4L _SFR_MEM8(0xA6) 2172 #define ICR4H _SFR_MEM8(0xA7) 2173 2174 /* Timer/Counter4 Output Compare Register A Bytes */ 2175 #define OCR4A _SFR_MEM16(0xA8) 2176 #define OCR4AL _SFR_MEM8(0xA8) 2177 #define OCR4AH _SFR_MEM8(0xA9) 2178 2179 /* Timer/Counter4 Output Compare Register B Bytes */ 2180 #define OCR4B _SFR_MEM16(0xAA) 2181 #define OCR4BL _SFR_MEM8(0xAA) 2182 #define OCR4BH _SFR_MEM8(0xAB) 2183 2184 /* Timer/Counter4 Output Compare Register C Bytes */ 2185 #define OCR4C _SFR_MEM16(0xAC) 2186 #define OCR4CL _SFR_MEM8(0xAC) 2187 #define OCR4CH _SFR_MEM8(0xAD) 2188 2189 /* Timer/Counter2 Control Register A */ 2190 #define TCCR2A _SFR_MEM8(0xB0) 2191 2192 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2193 2194 struct __reg_TCCR2A { 2195 unsigned int wgm2 : 2; /* Waveform Generation Mode */ 2196 unsigned int : 2; 2197 unsigned int com2b : 2; /* Compare Match Output B Mode */ 2198 unsigned int com2a : 2; /* Compare Match Output A Mode */ 2199 }; 2200 2201 #define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A) 2202 2203 #endif /* __ASSEMBLER__ */ 2204 2205 /* TCCR2A */ 2206 2207 #define WGM20 0 2208 #define WGM21 1 2209 #define COM2B0 4 2210 #define COM2B1 5 2211 #define COM2A0 6 2212 #define COM2A1 7 2213 2214 /* Timer/Counter2 Control Register B */ 2215 #define TCCR2B _SFR_MEM8(0xB1) 2216 2217 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2218 2219 struct __reg_TCCR2B { 2220 unsigned int cs2 : 3; /* Clock Select */ 2221 unsigned int wgm22 : 1; /* Waveform Generation Mode */ 2222 unsigned int : 2; 2223 unsigned int foc2b : 1; /* Force Output Compare B */ 2224 unsigned int foc2a : 1; /* Force Output Compare A */ 2225 }; 2226 2227 #define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B) 2228 2229 #endif /* __ASSEMBLER__ */ 2230 2231 /* TCCR2B */ 2232 2233 #define CS20 0 2234 #define CS21 1 2235 #define CS22 2 2236 #define WGM22 3 2237 #define FOC2B 6 2238 #define FOC2A 7 2239 2240 /* Timer/Counter2 */ 2241 #define TCNT2 _SFR_MEM8(0xB2) 2242 2243 /* TCNT2 */ 2244 2245 #define TCNT20 0 2246 #define TCNT21 1 2247 #define TCNT22 2 2248 #define TCNT23 3 2249 #define TCNT24 4 2250 #define TCNT25 5 2251 #define TCNT26 6 2252 #define TCNT27 7 2253 2254 /* Timer/Counter2 Output Compare Register A */ 2255 #define OCR2A _SFR_MEM8(0xB3) 2256 2257 /* OCR2A */ 2258 2259 #define OCR2A0 0 2260 #define OCR2A1 1 2261 #define OCR2A2 2 2262 #define OCR2A3 3 2263 #define OCR2A4 4 2264 #define OCR2A5 5 2265 #define OCR2A6 6 2266 #define OCR2A7 7 2267 2268 /* Timer/Counter2 Output Compare Register B */ 2269 #define OCR2B _SFR_MEM8(0xB4) 2270 2271 /* OCR2B */ 2272 2273 #define OCR2B0 0 2274 #define OCR2B1 1 2275 #define OCR2B2 2 2276 #define OCR2B3 3 2277 #define OCR2B4 4 2278 #define OCR2B5 5 2279 #define OCR2B6 6 2280 #define OCR2B7 7 2281 2282 /* Asynchronous Status Register */ 2283 #define ASSR _SFR_MEM8(0xB6) 2284 2285 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2286 2287 struct __reg_ASSR { 2288 unsigned int tcr2bub : 1; /* Timer/Counter2 Control Register B Update Busy */ 2289 unsigned int tcr2aub : 1; /* Timer/Counter2 Control Register A Update Busy */ 2290 unsigned int ocr2bub : 1; /* Timer/Counter2 Output Compare Register B Update Busy */ 2291 unsigned int ocr2aub : 1; /* Timer/Counter2 Output Compare Register A Update Busy */ 2292 unsigned int tcn2ub : 1; /* Timer/Counter2 Update Busy */ 2293 unsigned int as2 : 1; /* Timer/Counter2 Asynchronous Mode */ 2294 unsigned int exclk : 1; /* Enable External Clock Input */ 2295 unsigned int exclkamr : 1; /* Enable External Clock Input for AMR */ 2296 }; 2297 2298 #define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR) 2299 2300 #endif /* __ASSEMBLER__ */ 2301 2302 /* ASSR */ 2303 2304 #define TCR2BUB 0 2305 #define TCR2AUB 1 2306 #define OCR2BUB 2 2307 #define OCR2AUB 3 2308 #define TCN2UB 4 2309 #define AS2 5 2310 #define EXCLK 6 2311 #define EXCLKAMR 7 2312 2313 /* TWI Bit Rate Register */ 2314 #define TWBR _SFR_MEM8(0xB8) 2315 2316 /* TWBR */ 2317 2318 #define TWBR0 0 2319 #define TWBR1 1 2320 #define TWBR2 2 2321 #define TWBR3 3 2322 #define TWBR4 4 2323 #define TWBR5 5 2324 #define TWBR6 6 2325 #define TWBR7 7 2326 2327 /* TWI Status Register */ 2328 #define TWSR _SFR_MEM8(0xB9) 2329 2330 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2331 2332 struct __reg_TWSR { 2333 unsigned int twps : 2; /* TWI Prescaler Bits */ 2334 unsigned int : 1; 2335 unsigned int tws : 5; /* TWI Status */ 2336 }; 2337 2338 #define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR) 2339 2340 #endif /* __ASSEMBLER__ */ 2341 2342 /* TWSR */ 2343 2344 #define TWPS0 0 2345 #define TWPS1 1 2346 #define TWS3 3 2347 #define TWS4 4 2348 #define TWS5 5 2349 #define TWS6 6 2350 #define TWS7 7 2351 2352 /* TWI (Slave) Address Register */ 2353 #define TWAR _SFR_MEM8(0xBA) 2354 2355 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2356 2357 struct __reg_TWAR { 2358 unsigned int twgce : 1; /* TWI General Call Recognition Enable Bit */ 2359 unsigned int twa : 7; /* TWI (Slave) Address */ 2360 }; 2361 2362 #define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR) 2363 2364 #endif /* __ASSEMBLER__ */ 2365 2366 /* TWAR */ 2367 2368 #define TWGCE 0 2369 #define TWA0 1 2370 #define TWA1 2 2371 #define TWA2 3 2372 #define TWA3 4 2373 #define TWA4 5 2374 #define TWA5 6 2375 #define TWA6 7 2376 2377 /* TWI Data Register */ 2378 #define TWDR _SFR_MEM8(0xBB) 2379 2380 /* TWDR */ 2381 2382 #define TWD0 0 2383 #define TWD1 1 2384 #define TWD2 2 2385 #define TWD3 3 2386 #define TWD4 4 2387 #define TWD5 5 2388 #define TWD6 6 2389 #define TWD7 7 2390 2391 /* TWI Control Register */ 2392 #define TWCR _SFR_MEM8(0xBC) 2393 2394 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2395 2396 struct __reg_TWCR { 2397 unsigned int twie : 1; /* TWI Interrupt Enable */ 2398 unsigned int : 1; 2399 unsigned int twen : 1; /* TWI Enable Bit */ 2400 unsigned int twwc : 1; /* TWI Write Collision Flag */ 2401 unsigned int twsto : 1; /* TWI STOP Condition Bit */ 2402 unsigned int twsta : 1; /* TWI START Condition Bit */ 2403 unsigned int twea : 1; /* TWI Enable Acknowledge Bit */ 2404 unsigned int twint : 1; /* TWI Interrupt Flag */ 2405 }; 2406 2407 #define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR) 2408 2409 #endif /* __ASSEMBLER__ */ 2410 2411 /* TWCR */ 2412 2413 #define TWIE 0 2414 #define TWEN 2 2415 #define TWWC 3 2416 #define TWSTO 4 2417 #define TWSTA 5 2418 #define TWEA 6 2419 #define TWINT 7 2420 2421 /* TWI (Slave) Address Mask Register */ 2422 #define TWAMR _SFR_MEM8(0xBD) 2423 2424 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2425 2426 struct __reg_TWAMR { 2427 unsigned int : 1; 2428 unsigned int twam : 7; /* TWI Address Mask */ 2429 }; 2430 2431 #define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR) 2432 2433 #endif /* __ASSEMBLER__ */ 2434 2435 /* TWAMR */ 2436 2437 #define TWAM0 1 2438 #define TWAMR0 1 2439 #define TWAM1 2 2440 #define TWAMR1 2 2441 #define TWAM2 3 2442 #define TWAMR2 3 2443 #define TWAM3 4 2444 #define TWAMR3 4 2445 #define TWAM4 5 2446 #define TWAMR4 5 2447 #define TWAM5 6 2448 #define TWAMR5 6 2449 #define TWAM6 7 2450 #define TWAMR6 7 2451 2452 /* Transceiver Interrupt Enable Register 1 */ 2453 #define IRQ_MASK1 _SFR_MEM8(0xBE) 2454 2455 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2456 2457 struct __reg_IRQ_MASK1 { 2458 unsigned int tx_start_en : 1; /* Transmit Start Interrupt enable */ 2459 unsigned int maf_0_ami_en : 1; /* Address Match Interrupt enable Address filter 0 */ 2460 unsigned int maf_1_ami_en : 1; /* Address Match Interrupt enable Address filter 1 */ 2461 unsigned int maf_2_ami_en : 1; /* Address Match Interrupt enable Address filter 2 */ 2462 unsigned int maf_3_ami_en : 1; /* Address Match Interrupt enable Address filter 3 */ 2463 unsigned int : 3; 2464 }; 2465 2466 #define IRQ_MASK1_struct _SFR_MEM8_STRUCT(0xbe, struct __reg_IRQ_MASK1) 2467 2468 #endif /* __ASSEMBLER__ */ 2469 2470 /* IRQ_MASK1 */ 2471 2472 #define TX_START_EN 0 2473 #define MAF_0_AMI_EN 1 2474 #define MAF_1_AMI_EN 2 2475 #define MAF_2_AMI_EN 3 2476 #define MAF_3_AMI_EN 4 2477 2478 /* Transceiver Interrupt Status Register 1 */ 2479 #define IRQ_STATUS1 _SFR_MEM8(0xBF) 2480 2481 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2482 2483 struct __reg_IRQ_STATUS1 { 2484 unsigned int tx_start : 1; /* Transmit Start Interrupt Status */ 2485 unsigned int maf_0_ami : 1; /* Address Match Interrupt Status Address filter 0 */ 2486 unsigned int maf_1_ami : 1; /* Address Match Interrupt Status Address filter 1 */ 2487 unsigned int maf_2_ami : 1; /* Address Match Interrupt Status Address filter 2 */ 2488 unsigned int maf_3_ami : 1; /* Address Match Interrupt Status Address filter 3 */ 2489 unsigned int : 3; 2490 }; 2491 2492 #define IRQ_STATUS1_struct _SFR_MEM8_STRUCT(0xbf, struct __reg_IRQ_STATUS1) 2493 2494 #endif /* __ASSEMBLER__ */ 2495 2496 /* IRQ_STATUS1 */ 2497 2498 #define TX_START 0 2499 #define MAF_0_AMI 1 2500 #define MAF_1_AMI 2 2501 #define MAF_2_AMI 3 2502 #define MAF_3_AMI 4 2503 2504 /* USART0 Control and Status Register A */ 2505 #define UCSR0A _SFR_MEM8(0xC0) 2506 2507 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2508 2509 struct __reg_UCSR0A { 2510 unsigned int mpcm0 : 1; /* Multi-processor Communication Mode */ 2511 unsigned int u2x0 : 1; /* Double the USART Transmission Speed */ 2512 unsigned int upe0 : 1; /* USART Parity Error */ 2513 unsigned int dor0 : 1; /* Data OverRun */ 2514 unsigned int fe0 : 1; /* Frame Error */ 2515 unsigned int udre0 : 1; /* USART Data Register Empty */ 2516 unsigned int txc0 : 1; /* USART Transmit Complete */ 2517 unsigned int rxc0 : 1; /* USART Receive Complete */ 2518 }; 2519 2520 #define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A) 2521 2522 #endif /* __ASSEMBLER__ */ 2523 2524 /* UCSR0A */ 2525 2526 #define MPCM0 0 2527 #define U2X0 1 2528 #define UPE0 2 2529 #define DOR0 3 2530 #define FE0 4 2531 #define UDRE0 5 2532 #define TXC0 6 2533 #define RXC0 7 2534 2535 /* USART0 Control and Status Register B */ 2536 #define UCSR0B _SFR_MEM8(0xC1) 2537 2538 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2539 2540 struct __reg_UCSR0B { 2541 unsigned int txb80 : 1; /* Transmit Data Bit 8 */ 2542 unsigned int rxb80 : 1; /* Receive Data Bit 8 */ 2543 unsigned int ucsz02 : 1; /* Character Size */ 2544 unsigned int txen0 : 1; /* Transmitter Enable */ 2545 unsigned int rxen0 : 1; /* Receiver Enable */ 2546 unsigned int udrie0 : 1; /* USART Data Register Empty Interrupt Enable */ 2547 unsigned int txcie0 : 1; /* TX Complete Interrupt Enable */ 2548 unsigned int rxcie0 : 1; /* RX Complete Interrupt Enable */ 2549 }; 2550 2551 #define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B) 2552 2553 #endif /* __ASSEMBLER__ */ 2554 2555 /* UCSR0B */ 2556 2557 #define TXB80 0 2558 #define RXB80 1 2559 #define UCSZ02 2 2560 #define TXEN0 3 2561 #define RXEN0 4 2562 #define UDRIE0 5 2563 #define TXCIE0 6 2564 #define RXCIE0 7 2565 2566 /* USART0 Control and Status Register C */ 2567 #define UCSR0C _SFR_MEM8(0xC2) 2568 2569 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2570 2571 struct __reg_UCSR0C { 2572 unsigned int ucpol0 : 1; /* Clock Polarity */ 2573 unsigned int ucsz0 : 2; /* Character Size */ 2574 unsigned int ucpha0 : 1; /* Clock Phase */ 2575 unsigned int udord0 : 1; /* Data Order */ 2576 unsigned int usbs0 : 1; /* Stop Bit Select */ 2577 unsigned int upm0 : 2; /* Parity Mode */ 2578 unsigned int umsel0 : 2; /* USART Mode Select */ 2579 }; 2580 2581 #define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C) 2582 2583 #endif /* __ASSEMBLER__ */ 2584 2585 /* UCSR0C */ 2586 2587 #define UCPOL0 0 2588 #define UCPHA0 1 2589 #define UCPHA0 1 2590 #define UCSZ00 1 2591 #define UDORD0 2 2592 #define UDORD0 2 2593 #define UCSZ01 2 2594 #define USBS0 3 2595 #define UPM00 4 2596 #define UPM01 5 2597 #define UMSEL00 6 2598 #define UMSEL0 6 2599 #define UMSEL01 7 2600 #define UMSEL1 7 2601 2602 /* USART0 Baud Rate Register Bytes */ 2603 #define UBRR0 _SFR_MEM16(0xC4) 2604 #define UBRR0L _SFR_MEM8(0xC4) 2605 #define UBRR0H _SFR_MEM8(0xC5) 2606 2607 /* USART0 I/O Data Register */ 2608 #define UDR0 _SFR_MEM8(0xC6) 2609 2610 /* UDR0 */ 2611 2612 #define UDR00 0 2613 #define UDR01 1 2614 #define UDR02 2 2615 #define UDR03 3 2616 #define UDR04 4 2617 #define UDR05 5 2618 #define UDR06 6 2619 #define UDR07 7 2620 2621 /* USART1 Control and Status Register A */ 2622 #define UCSR1A _SFR_MEM8(0xC8) 2623 2624 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2625 2626 struct __reg_UCSR1A { 2627 unsigned int mpcm1 : 1; /* Multi-processor Communication Mode */ 2628 unsigned int u2x1 : 1; /* Double the USART Transmission Speed */ 2629 unsigned int upe1 : 1; /* USART Parity Error */ 2630 unsigned int dor1 : 1; /* Data OverRun */ 2631 unsigned int fe1 : 1; /* Frame Error */ 2632 unsigned int udre1 : 1; /* USART Data Register Empty */ 2633 unsigned int txc1 : 1; /* USART Transmit Complete */ 2634 unsigned int rxc1 : 1; /* USART Receive Complete */ 2635 }; 2636 2637 #define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A) 2638 2639 #endif /* __ASSEMBLER__ */ 2640 2641 /* UCSR1A */ 2642 2643 #define MPCM1 0 2644 #define U2X1 1 2645 #define UPE1 2 2646 #define DOR1 3 2647 #define FE1 4 2648 #define UDRE1 5 2649 #define TXC1 6 2650 #define RXC1 7 2651 2652 /* USART1 Control and Status Register B */ 2653 #define UCSR1B _SFR_MEM8(0xC9) 2654 2655 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2656 2657 struct __reg_UCSR1B { 2658 unsigned int txb81 : 1; /* Transmit Data Bit 8 */ 2659 unsigned int rxb81 : 1; /* Receive Data Bit 8 */ 2660 unsigned int ucsz12 : 1; /* Character Size */ 2661 unsigned int txen1 : 1; /* Transmitter Enable */ 2662 unsigned int rxen1 : 1; /* Receiver Enable */ 2663 unsigned int udrie1 : 1; /* USART Data Register Empty Interrupt Enable */ 2664 unsigned int txcie1 : 1; /* TX Complete Interrupt Enable */ 2665 unsigned int rxcie1 : 1; /* RX Complete Interrupt Enable */ 2666 }; 2667 2668 #define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B) 2669 2670 #endif /* __ASSEMBLER__ */ 2671 2672 /* UCSR1B */ 2673 2674 #define TXB81 0 2675 #define RXB81 1 2676 #define UCSZ12 2 2677 #define TXEN1 3 2678 #define RXEN1 4 2679 #define UDRIE1 5 2680 #define TXCIE1 6 2681 #define RXCIE1 7 2682 2683 /* USART1 Control and Status Register C */ 2684 #define UCSR1C _SFR_MEM8(0xCA) 2685 2686 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2687 2688 struct __reg_UCSR1C { 2689 unsigned int ucpol1 : 1; /* Clock Polarity */ 2690 unsigned int ucsz1 : 2; /* Character Size */ 2691 unsigned int ucpha1 : 1; /* Clock Phase */ 2692 unsigned int udord1 : 1; /* Data Order */ 2693 unsigned int usbs1 : 1; /* Stop Bit Select */ 2694 unsigned int upm1 : 2; /* Parity Mode */ 2695 unsigned int umsel1 : 2; /* USART Mode Select */ 2696 }; 2697 2698 #define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C) 2699 2700 #endif /* __ASSEMBLER__ */ 2701 2702 /* UCSR1C */ 2703 2704 #define UCPOL1 0 2705 #define UCPHA1 1 2706 #define UCPHA1 1 2707 #define UCSZ10 1 2708 #define UDORD1 2 2709 #define UDORD1 2 2710 #define UCSZ11 2 2711 #define USBS1 3 2712 #define UPM10 4 2713 #define UPM11 5 2714 #define UMSEL10 6 2715 #define UMSEL11 7 2716 2717 /* USART1 Baud Rate Register Bytes */ 2718 #define UBRR1 _SFR_MEM16(0xCC) 2719 #define UBRR1L _SFR_MEM8(0xCC) 2720 #define UBRR1H _SFR_MEM8(0xCD) 2721 2722 /* USART1 I/O Data Register */ 2723 #define UDR1 _SFR_MEM8(0xCE) 2724 2725 /* UDR1 */ 2726 2727 #define UDR10 0 2728 #define UDR11 1 2729 #define UDR12 2 2730 #define UDR13 3 2731 #define UDR14 4 2732 #define UDR15 5 2733 #define UDR16 6 2734 #define UDR17 7 2735 2736 /* Symbol Counter Received Frame Timestamp Register LL-Byte */ 2737 #define SCRSTRLL _SFR_MEM8(0xD7) 2738 2739 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2740 2741 struct __reg_SCRSTRLL { 2742 unsigned int scrstrll : 8; /* Symbol Counter Received Frame Timestamp Register LL-Byte */ 2743 }; 2744 2745 #define SCRSTRLL_struct _SFR_MEM8_STRUCT(0xd7, struct __reg_SCRSTRLL) 2746 2747 #endif /* __ASSEMBLER__ */ 2748 2749 /* SCRSTRLL */ 2750 2751 #define SCRSTRLL0 0 2752 #define SCRSTRLL1 1 2753 #define SCRSTRLL2 2 2754 #define SCRSTRLL3 3 2755 #define SCRSTRLL4 4 2756 #define SCRSTRLL5 5 2757 #define SCRSTRLL6 6 2758 #define SCRSTRLL7 7 2759 2760 /* Symbol Counter Received Frame Timestamp Register LH-Byte */ 2761 #define SCRSTRLH _SFR_MEM8(0xD8) 2762 2763 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2764 2765 struct __reg_SCRSTRLH { 2766 unsigned int scrstrlh : 8; /* Symbol Counter Received Frame Timestamp Register LH-Byte */ 2767 }; 2768 2769 #define SCRSTRLH_struct _SFR_MEM8_STRUCT(0xd8, struct __reg_SCRSTRLH) 2770 2771 #endif /* __ASSEMBLER__ */ 2772 2773 /* SCRSTRLH */ 2774 2775 #define SCRSTRLH0 0 2776 #define SCRSTRLH1 1 2777 #define SCRSTRLH2 2 2778 #define SCRSTRLH3 3 2779 #define SCRSTRLH4 4 2780 #define SCRSTRLH5 5 2781 #define SCRSTRLH6 6 2782 #define SCRSTRLH7 7 2783 2784 /* Symbol Counter Received Frame Timestamp Register HL-Byte */ 2785 #define SCRSTRHL _SFR_MEM8(0xD9) 2786 2787 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2788 2789 struct __reg_SCRSTRHL { 2790 unsigned int scrstrhl : 8; /* Symbol Counter Received Frame Timestamp Register HL-Byte */ 2791 }; 2792 2793 #define SCRSTRHL_struct _SFR_MEM8_STRUCT(0xd9, struct __reg_SCRSTRHL) 2794 2795 #endif /* __ASSEMBLER__ */ 2796 2797 /* SCRSTRHL */ 2798 2799 #define SCRSTRHL0 0 2800 #define SCRSTRHL1 1 2801 #define SCRSTRHL2 2 2802 #define SCRSTRHL3 3 2803 #define SCRSTRHL4 4 2804 #define SCRSTRHL5 5 2805 #define SCRSTRHL6 6 2806 #define SCRSTRHL7 7 2807 2808 /* Symbol Counter Received Frame Timestamp Register HH-Byte */ 2809 #define SCRSTRHH _SFR_MEM8(0xDA) 2810 2811 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2812 2813 struct __reg_SCRSTRHH { 2814 unsigned int scrstrhh : 8; /* Symbol Counter Received Frame Timestamp Register HH-Byte */ 2815 }; 2816 2817 #define SCRSTRHH_struct _SFR_MEM8_STRUCT(0xda, struct __reg_SCRSTRHH) 2818 2819 #endif /* __ASSEMBLER__ */ 2820 2821 /* SCRSTRHH */ 2822 2823 #define SCRSTRHH0 0 2824 #define SCRSTRHH1 1 2825 #define SCRSTRHH2 2 2826 #define SCRSTRHH3 3 2827 #define SCRSTRHH4 4 2828 #define SCRSTRHH5 5 2829 #define SCRSTRHH6 6 2830 #define SCRSTRHH7 7 2831 2832 /* Symbol Counter Compare Source Register */ 2833 #define SCCSR _SFR_MEM8(0xDB) 2834 2835 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2836 2837 struct __reg_SCCSR { 2838 unsigned int sccs1 : 2; /* Symbol Counter Compare Source select register for Compare Units */ 2839 unsigned int sccs2 : 2; /* Symbol Counter Compare Source select register for Compare Unit 2 */ 2840 unsigned int sccs3 : 2; /* Symbol Counter Compare Source select register for Compare Unit 3 */ 2841 unsigned int : 2; 2842 }; 2843 2844 #define SCCSR_struct _SFR_MEM8_STRUCT(0xdb, struct __reg_SCCSR) 2845 2846 #endif /* __ASSEMBLER__ */ 2847 2848 /* SCCSR */ 2849 2850 #define SCCS10 0 2851 #define SCCS11 1 2852 #define SCCS20 2 2853 #define SCCS21 3 2854 #define SCCS30 4 2855 #define SCCS31 5 2856 2857 /* Symbol Counter Control Register 0 */ 2858 #define SCCR0 _SFR_MEM8(0xDC) 2859 2860 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2861 2862 struct __reg_SCCR0 { 2863 unsigned int sccmp : 3; /* Symbol Counter Compare Unit 3 Mode select */ 2864 unsigned int sctse : 1; /* Symbol Counter Automatic Timestamping enable */ 2865 unsigned int sccksel : 1; /* Symbol Counter Clock Source select */ 2866 unsigned int scen : 1; /* Symbol Counter enable */ 2867 unsigned int scmbts : 1; /* Manual Beacon Timestamp */ 2868 unsigned int scres : 1; /* Symbol Counter Synchronization */ 2869 }; 2870 2871 #define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0) 2872 2873 #endif /* __ASSEMBLER__ */ 2874 2875 /* SCCR0 */ 2876 2877 #define SCCMP1 0 2878 #define SCCMP2 1 2879 #define SCCMP3 2 2880 #define SCTSE 3 2881 #define SCCKSEL 4 2882 #define SCEN 5 2883 #define SCMBTS 6 2884 #define SCRES 7 2885 2886 /* Symbol Counter Control Register 1 */ 2887 #define SCCR1 _SFR_MEM8(0xDD) 2888 2889 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2890 2891 struct __reg_SCCR1 { 2892 unsigned int scenbo : 1; /* Backoff Slot Counter enable */ 2893 unsigned int sceeclk : 1; /* Enable External Clock Source on PG2 */ 2894 unsigned int scckdiv : 3; /* Clock divider for synchronous clock source (16MHz Transceiver Clock) */ 2895 unsigned int scbtsm : 1; /* Symbol Counter Beacon Timestamp Mask Register */ 2896 unsigned int : 2; 2897 }; 2898 2899 #define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1) 2900 2901 #endif /* __ASSEMBLER__ */ 2902 2903 /* SCCR1 */ 2904 2905 #define SCENBO 0 2906 #define SCEECLK 1 2907 #define SCCKDIV0 2 2908 #define SCCKDIV1 3 2909 #define SCCKDIV2 4 2910 #define SCBTSM 5 2911 2912 /* Symbol Counter Status Register */ 2913 #define SCSR _SFR_MEM8(0xDE) 2914 2915 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2916 2917 struct __reg_SCSR { 2918 unsigned int scbsy : 1; /* Symbol Counter busy */ 2919 unsigned int : 7; 2920 }; 2921 2922 #define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR) 2923 2924 #endif /* __ASSEMBLER__ */ 2925 2926 /* SCSR */ 2927 2928 #define SCBSY 0 2929 2930 /* Symbol Counter Interrupt Mask Register */ 2931 #define SCIRQM _SFR_MEM8(0xDF) 2932 2933 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2934 2935 struct __reg_SCIRQM { 2936 unsigned int irqmcp : 3; /* Symbol Counter Compare Match 3 IRQ enable */ 2937 unsigned int irqmof : 1; /* Symbol Counter Overflow IRQ enable */ 2938 unsigned int irqmbo : 1; /* Backoff Slot Counter IRQ enable */ 2939 unsigned int : 3; 2940 }; 2941 2942 #define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM) 2943 2944 #endif /* __ASSEMBLER__ */ 2945 2946 /* SCIRQM */ 2947 2948 #define IRQMCP1 0 2949 #define IRQMCP2 1 2950 #define IRQMCP3 2 2951 #define IRQMOF 3 2952 #define IRQMBO 4 2953 2954 /* Symbol Counter Interrupt Status Register */ 2955 #define SCIRQS _SFR_MEM8(0xE0) 2956 2957 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2958 2959 struct __reg_SCIRQS { 2960 unsigned int irqscp : 3; /* Compare Unit 3 Compare Match IRQ */ 2961 unsigned int irqsof : 1; /* Symbol Counter Overflow IRQ */ 2962 unsigned int irqsbo : 1; /* Backoff Slot Counter IRQ */ 2963 unsigned int : 3; 2964 }; 2965 2966 #define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS) 2967 2968 #endif /* __ASSEMBLER__ */ 2969 2970 /* SCIRQS */ 2971 2972 #define IRQSCP1 0 2973 #define IRQSCP2 1 2974 #define IRQSCP3 2 2975 #define IRQSOF 3 2976 #define IRQSBO 4 2977 2978 /* Symbol Counter Register LL-Byte */ 2979 #define SCCNTLL _SFR_MEM8(0xE1) 2980 2981 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 2982 2983 struct __reg_SCCNTLL { 2984 unsigned int sccntll : 8; /* Symbol Counter Register LL-Byte */ 2985 }; 2986 2987 #define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL) 2988 2989 #endif /* __ASSEMBLER__ */ 2990 2991 /* SCCNTLL */ 2992 2993 #define SCCNTLL0 0 2994 #define SCCNTLL1 1 2995 #define SCCNTLL2 2 2996 #define SCCNTLL3 3 2997 #define SCCNTLL4 4 2998 #define SCCNTLL5 5 2999 #define SCCNTLL6 6 3000 #define SCCNTLL7 7 3001 3002 /* Symbol Counter Register LH-Byte */ 3003 #define SCCNTLH _SFR_MEM8(0xE2) 3004 3005 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3006 3007 struct __reg_SCCNTLH { 3008 unsigned int sccntlh : 8; /* Symbol Counter Register LH-Byte */ 3009 }; 3010 3011 #define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH) 3012 3013 #endif /* __ASSEMBLER__ */ 3014 3015 /* SCCNTLH */ 3016 3017 #define SCCNTLH0 0 3018 #define SCCNTLH1 1 3019 #define SCCNTLH2 2 3020 #define SCCNTLH3 3 3021 #define SCCNTLH4 4 3022 #define SCCNTLH5 5 3023 #define SCCNTLH6 6 3024 #define SCCNTLH7 7 3025 3026 /* Symbol Counter Register HL-Byte */ 3027 #define SCCNTHL _SFR_MEM8(0xE3) 3028 3029 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3030 3031 struct __reg_SCCNTHL { 3032 unsigned int sccnthl : 8; /* Symbol Counter Register HL-Byte */ 3033 }; 3034 3035 #define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL) 3036 3037 #endif /* __ASSEMBLER__ */ 3038 3039 /* SCCNTHL */ 3040 3041 #define SCCNTHL0 0 3042 #define SCCNTHL1 1 3043 #define SCCNTHL2 2 3044 #define SCCNTHL3 3 3045 #define SCCNTHL4 4 3046 #define SCCNTHL5 5 3047 #define SCCNTHL6 6 3048 #define SCCNTHL7 7 3049 3050 /* Symbol Counter Register HH-Byte */ 3051 #define SCCNTHH _SFR_MEM8(0xE4) 3052 3053 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3054 3055 struct __reg_SCCNTHH { 3056 unsigned int sccnthh : 8; /* Symbol Counter Register HH-Byte */ 3057 }; 3058 3059 #define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH) 3060 3061 #endif /* __ASSEMBLER__ */ 3062 3063 /* SCCNTHH */ 3064 3065 #define SCCNTHH0 0 3066 #define SCCNTHH1 1 3067 #define SCCNTHH2 2 3068 #define SCCNTHH3 3 3069 #define SCCNTHH4 4 3070 #define SCCNTHH5 5 3071 #define SCCNTHH6 6 3072 #define SCCNTHH7 7 3073 3074 /* Symbol Counter Beacon Timestamp Register LL-Byte */ 3075 #define SCBTSRLL _SFR_MEM8(0xE5) 3076 3077 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3078 3079 struct __reg_SCBTSRLL { 3080 unsigned int scbtsrll : 8; /* Symbol Counter Beacon Timestamp Register LL-Byte */ 3081 }; 3082 3083 #define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL) 3084 3085 #endif /* __ASSEMBLER__ */ 3086 3087 /* SCBTSRLL */ 3088 3089 #define SCBTSRLL0 0 3090 #define SCBTSRLL1 1 3091 #define SCBTSRLL2 2 3092 #define SCBTSRLL3 3 3093 #define SCBTSRLL4 4 3094 #define SCBTSRLL5 5 3095 #define SCBTSRLL6 6 3096 #define SCBTSRLL7 7 3097 3098 /* Symbol Counter Beacon Timestamp Register LH-Byte */ 3099 #define SCBTSRLH _SFR_MEM8(0xE6) 3100 3101 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3102 3103 struct __reg_SCBTSRLH { 3104 unsigned int scbtsrlh : 8; /* Symbol Counter Beacon Timestamp Register LH-Byte */ 3105 }; 3106 3107 #define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH) 3108 3109 #endif /* __ASSEMBLER__ */ 3110 3111 /* SCBTSRLH */ 3112 3113 #define SCBTSRLH0 0 3114 #define SCBTSRLH1 1 3115 #define SCBTSRLH2 2 3116 #define SCBTSRLH3 3 3117 #define SCBTSRLH4 4 3118 #define SCBTSRLH5 5 3119 #define SCBTSRLH6 6 3120 #define SCBTSRLH7 7 3121 3122 /* Symbol Counter Beacon Timestamp Register HL-Byte */ 3123 #define SCBTSRHL _SFR_MEM8(0xE7) 3124 3125 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3126 3127 struct __reg_SCBTSRHL { 3128 unsigned int scbtsrhl : 8; /* Symbol Counter Beacon Timestamp Register HL-Byte */ 3129 }; 3130 3131 #define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL) 3132 3133 #endif /* __ASSEMBLER__ */ 3134 3135 /* SCBTSRHL */ 3136 3137 #define SCBTSRHL0 0 3138 #define SCBTSRHL1 1 3139 #define SCBTSRHL2 2 3140 #define SCBTSRHL3 3 3141 #define SCBTSRHL4 4 3142 #define SCBTSRHL5 5 3143 #define SCBTSRHL6 6 3144 #define SCBTSRHL7 7 3145 3146 /* Symbol Counter Beacon Timestamp Register HH-Byte */ 3147 #define SCBTSRHH _SFR_MEM8(0xE8) 3148 3149 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3150 3151 struct __reg_SCBTSRHH { 3152 unsigned int scbtsrhh : 8; /* Symbol Counter Beacon Timestamp Register HH-Byte */ 3153 }; 3154 3155 #define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH) 3156 3157 #endif /* __ASSEMBLER__ */ 3158 3159 /* SCBTSRHH */ 3160 3161 #define SCBTSRHH0 0 3162 #define SCBTSRHH1 1 3163 #define SCBTSRHH2 2 3164 #define SCBTSRHH3 3 3165 #define SCBTSRHH4 4 3166 #define SCBTSRHH5 5 3167 #define SCBTSRHH6 6 3168 #define SCBTSRHH7 7 3169 3170 /* Symbol Counter Frame Timestamp Register LL-Byte */ 3171 #define SCTSRLL _SFR_MEM8(0xE9) 3172 3173 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3174 3175 struct __reg_SCTSRLL { 3176 unsigned int sctsrll : 8; /* Symbol Counter Frame Timestamp Register LL-Byte */ 3177 }; 3178 3179 #define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL) 3180 3181 #endif /* __ASSEMBLER__ */ 3182 3183 /* SCTSRLL */ 3184 3185 #define SCTSRLL0 0 3186 #define SCTSRLL1 1 3187 #define SCTSRLL2 2 3188 #define SCTSRLL3 3 3189 #define SCTSRLL4 4 3190 #define SCTSRLL5 5 3191 #define SCTSRLL6 6 3192 #define SCTSRLL7 7 3193 3194 /* Symbol Counter Frame Timestamp Register LH-Byte */ 3195 #define SCTSRLH _SFR_MEM8(0xEA) 3196 3197 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3198 3199 struct __reg_SCTSRLH { 3200 unsigned int sctsrlh : 8; /* Symbol Counter Frame Timestamp Register LH-Byte */ 3201 }; 3202 3203 #define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH) 3204 3205 #endif /* __ASSEMBLER__ */ 3206 3207 /* SCTSRLH */ 3208 3209 #define SCTSRLH0 0 3210 #define SCTSRLH1 1 3211 #define SCTSRLH2 2 3212 #define SCTSRLH3 3 3213 #define SCTSRLH4 4 3214 #define SCTSRLH5 5 3215 #define SCTSRLH6 6 3216 #define SCTSRLH7 7 3217 3218 /* Symbol Counter Frame Timestamp Register HL-Byte */ 3219 #define SCTSRHL _SFR_MEM8(0xEB) 3220 3221 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3222 3223 struct __reg_SCTSRHL { 3224 unsigned int sctsrhl : 8; /* Symbol Counter Frame Timestamp Register HL-Byte */ 3225 }; 3226 3227 #define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL) 3228 3229 #endif /* __ASSEMBLER__ */ 3230 3231 /* SCTSRHL */ 3232 3233 #define SCTSRHL0 0 3234 #define SCTSRHL1 1 3235 #define SCTSRHL2 2 3236 #define SCTSRHL3 3 3237 #define SCTSRHL4 4 3238 #define SCTSRHL5 5 3239 #define SCTSRHL6 6 3240 #define SCTSRHL7 7 3241 3242 /* Symbol Counter Frame Timestamp Register HH-Byte */ 3243 #define SCTSRHH _SFR_MEM8(0xEC) 3244 3245 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3246 3247 struct __reg_SCTSRHH { 3248 unsigned int sctsrhh : 8; /* Symbol Counter Frame Timestamp Register HH-Byte */ 3249 }; 3250 3251 #define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH) 3252 3253 #endif /* __ASSEMBLER__ */ 3254 3255 /* SCTSRHH */ 3256 3257 #define SCTSRHH0 0 3258 #define SCTSRHH1 1 3259 #define SCTSRHH2 2 3260 #define SCTSRHH3 3 3261 #define SCTSRHH4 4 3262 #define SCTSRHH5 5 3263 #define SCTSRHH6 6 3264 #define SCTSRHH7 7 3265 3266 /* Symbol Counter Output Compare Register 3 LL-Byte */ 3267 #define SCOCR3LL _SFR_MEM8(0xED) 3268 3269 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3270 3271 struct __reg_SCOCR3LL { 3272 unsigned int scocr3ll : 8; /* Symbol Counter Output Compare Register 3 LL-Byte */ 3273 }; 3274 3275 #define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL) 3276 3277 #endif /* __ASSEMBLER__ */ 3278 3279 /* SCOCR3LL */ 3280 3281 #define SCOCR3LL0 0 3282 #define SCOCR3LL1 1 3283 #define SCOCR3LL2 2 3284 #define SCOCR3LL3 3 3285 #define SCOCR3LL4 4 3286 #define SCOCR3LL5 5 3287 #define SCOCR3LL6 6 3288 #define SCOCR3LL7 7 3289 3290 /* Symbol Counter Output Compare Register 3 LH-Byte */ 3291 #define SCOCR3LH _SFR_MEM8(0xEE) 3292 3293 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3294 3295 struct __reg_SCOCR3LH { 3296 unsigned int scocr3lh : 8; /* Symbol Counter Output Compare Register 3 LH-Byte */ 3297 }; 3298 3299 #define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH) 3300 3301 #endif /* __ASSEMBLER__ */ 3302 3303 /* SCOCR3LH */ 3304 3305 #define SCOCR3LH0 0 3306 #define SCOCR3LH1 1 3307 #define SCOCR3LH2 2 3308 #define SCOCR3LH3 3 3309 #define SCOCR3LH4 4 3310 #define SCOCR3LH5 5 3311 #define SCOCR3LH6 6 3312 #define SCOCR3LH7 7 3313 3314 /* Symbol Counter Output Compare Register 3 HL-Byte */ 3315 #define SCOCR3HL _SFR_MEM8(0xEF) 3316 3317 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3318 3319 struct __reg_SCOCR3HL { 3320 unsigned int scocr3hl : 8; /* Symbol Counter Output Compare Register 3 HL-Byte */ 3321 }; 3322 3323 #define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL) 3324 3325 #endif /* __ASSEMBLER__ */ 3326 3327 /* SCOCR3HL */ 3328 3329 #define SCOCR3HL0 0 3330 #define SCOCR3HL1 1 3331 #define SCOCR3HL2 2 3332 #define SCOCR3HL3 3 3333 #define SCOCR3HL4 4 3334 #define SCOCR3HL5 5 3335 #define SCOCR3HL6 6 3336 #define SCOCR3HL7 7 3337 3338 /* Symbol Counter Output Compare Register 3 HH-Byte */ 3339 #define SCOCR3HH _SFR_MEM8(0xF0) 3340 3341 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3342 3343 struct __reg_SCOCR3HH { 3344 unsigned int scocr3hh : 8; /* Symbol Counter Output Compare Register 3 HH-Byte */ 3345 }; 3346 3347 #define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH) 3348 3349 #endif /* __ASSEMBLER__ */ 3350 3351 /* SCOCR3HH */ 3352 3353 #define SCOCR3HH0 0 3354 #define SCOCR3HH1 1 3355 #define SCOCR3HH2 2 3356 #define SCOCR3HH3 3 3357 #define SCOCR3HH4 4 3358 #define SCOCR3HH5 5 3359 #define SCOCR3HH6 6 3360 #define SCOCR3HH7 7 3361 3362 /* Symbol Counter Output Compare Register 2 LL-Byte */ 3363 #define SCOCR2LL _SFR_MEM8(0xF1) 3364 3365 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3366 3367 struct __reg_SCOCR2LL { 3368 unsigned int scocr2ll : 8; /* Symbol Counter Output Compare Register 2 LL-Byte */ 3369 }; 3370 3371 #define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL) 3372 3373 #endif /* __ASSEMBLER__ */ 3374 3375 /* SCOCR2LL */ 3376 3377 #define SCOCR2LL0 0 3378 #define SCOCR2LL1 1 3379 #define SCOCR2LL2 2 3380 #define SCOCR2LL3 3 3381 #define SCOCR2LL4 4 3382 #define SCOCR2LL5 5 3383 #define SCOCR2LL6 6 3384 #define SCOCR2LL7 7 3385 3386 /* Symbol Counter Output Compare Register 2 LH-Byte */ 3387 #define SCOCR2LH _SFR_MEM8(0xF2) 3388 3389 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3390 3391 struct __reg_SCOCR2LH { 3392 unsigned int scocr2lh : 8; /* Symbol Counter Output Compare Register 2 LH-Byte */ 3393 }; 3394 3395 #define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH) 3396 3397 #endif /* __ASSEMBLER__ */ 3398 3399 /* SCOCR2LH */ 3400 3401 #define SCOCR2LH0 0 3402 #define SCOCR2LH1 1 3403 #define SCOCR2LH2 2 3404 #define SCOCR2LH3 3 3405 #define SCOCR2LH4 4 3406 #define SCOCR2LH5 5 3407 #define SCOCR2LH6 6 3408 #define SCOCR2LH7 7 3409 3410 /* Symbol Counter Output Compare Register 2 HL-Byte */ 3411 #define SCOCR2HL _SFR_MEM8(0xF3) 3412 3413 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3414 3415 struct __reg_SCOCR2HL { 3416 unsigned int scocr2hl : 8; /* Symbol Counter Output Compare Register 2 HL-Byte */ 3417 }; 3418 3419 #define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL) 3420 3421 #endif /* __ASSEMBLER__ */ 3422 3423 /* SCOCR2HL */ 3424 3425 #define SCOCR2HL0 0 3426 #define SCOCR2HL1 1 3427 #define SCOCR2HL2 2 3428 #define SCOCR2HL3 3 3429 #define SCOCR2HL4 4 3430 #define SCOCR2HL5 5 3431 #define SCOCR2HL6 6 3432 #define SCOCR2HL7 7 3433 3434 /* Symbol Counter Output Compare Register 2 HH-Byte */ 3435 #define SCOCR2HH _SFR_MEM8(0xF4) 3436 3437 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3438 3439 struct __reg_SCOCR2HH { 3440 unsigned int scocr2hh : 8; /* Symbol Counter Output Compare Register 2 HH-Byte */ 3441 }; 3442 3443 #define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH) 3444 3445 #endif /* __ASSEMBLER__ */ 3446 3447 /* SCOCR2HH */ 3448 3449 #define SCOCR2HH0 0 3450 #define SCOCR2HH1 1 3451 #define SCOCR2HH2 2 3452 #define SCOCR2HH3 3 3453 #define SCOCR2HH4 4 3454 #define SCOCR2HH5 5 3455 #define SCOCR2HH6 6 3456 #define SCOCR2HH7 7 3457 3458 /* Symbol Counter Output Compare Register 1 LL-Byte */ 3459 #define SCOCR1LL _SFR_MEM8(0xF5) 3460 3461 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3462 3463 struct __reg_SCOCR1LL { 3464 unsigned int scocr1ll : 8; /* Symbol Counter Output Compare Register 1 LL-Byte */ 3465 }; 3466 3467 #define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL) 3468 3469 #endif /* __ASSEMBLER__ */ 3470 3471 /* SCOCR1LL */ 3472 3473 #define SCOCR1LL0 0 3474 #define SCOCR1LL1 1 3475 #define SCOCR1LL2 2 3476 #define SCOCR1LL3 3 3477 #define SCOCR1LL4 4 3478 #define SCOCR1LL5 5 3479 #define SCOCR1LL6 6 3480 #define SCOCR1LL7 7 3481 3482 /* Symbol Counter Output Compare Register 1 LH-Byte */ 3483 #define SCOCR1LH _SFR_MEM8(0xF6) 3484 3485 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3486 3487 struct __reg_SCOCR1LH { 3488 unsigned int scocr1lh : 8; /* Symbol Counter Output Compare Register 1 LH-Byte */ 3489 }; 3490 3491 #define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH) 3492 3493 #endif /* __ASSEMBLER__ */ 3494 3495 /* SCOCR1LH */ 3496 3497 #define SCOCR1LH0 0 3498 #define SCOCR1LH1 1 3499 #define SCOCR1LH2 2 3500 #define SCOCR1LH3 3 3501 #define SCOCR1LH4 4 3502 #define SCOCR1LH5 5 3503 #define SCOCR1LH6 6 3504 #define SCOCR1LH7 7 3505 3506 /* Symbol Counter Output Compare Register 1 HL-Byte */ 3507 #define SCOCR1HL _SFR_MEM8(0xF7) 3508 3509 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3510 3511 struct __reg_SCOCR1HL { 3512 unsigned int scocr1hl : 8; /* Symbol Counter Output Compare Register 1 HL-Byte */ 3513 }; 3514 3515 #define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL) 3516 3517 #endif /* __ASSEMBLER__ */ 3518 3519 /* SCOCR1HL */ 3520 3521 #define SCOCR1HL0 0 3522 #define SCOCR1HL1 1 3523 #define SCOCR1HL2 2 3524 #define SCOCR1HL3 3 3525 #define SCOCR1HL4 4 3526 #define SCOCR1HL5 5 3527 #define SCOCR1HL6 6 3528 #define SCOCR1HL7 7 3529 3530 /* Symbol Counter Output Compare Register 1 HH-Byte */ 3531 #define SCOCR1HH _SFR_MEM8(0xF8) 3532 3533 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3534 3535 struct __reg_SCOCR1HH { 3536 unsigned int scocr1hh : 8; /* Symbol Counter Output Compare Register 1 HH-Byte */ 3537 }; 3538 3539 #define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH) 3540 3541 #endif /* __ASSEMBLER__ */ 3542 3543 /* SCOCR1HH */ 3544 3545 #define SCOCR1HH0 0 3546 #define SCOCR1HH1 1 3547 #define SCOCR1HH2 2 3548 #define SCOCR1HH3 3 3549 #define SCOCR1HH4 4 3550 #define SCOCR1HH5 5 3551 #define SCOCR1HH6 6 3552 #define SCOCR1HH7 7 3553 3554 /* Symbol Counter Transmit Frame Timestamp Register LL-Byte */ 3555 #define SCTSTRLL _SFR_MEM8(0xF9) 3556 3557 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3558 3559 struct __reg_SCTSTRLL { 3560 unsigned int sctstrll : 8; /* Symbol Counter Transmit Frame Timestamp Register LL-Byte */ 3561 }; 3562 3563 #define SCTSTRLL_struct _SFR_MEM8_STRUCT(0xf9, struct __reg_SCTSTRLL) 3564 3565 #endif /* __ASSEMBLER__ */ 3566 3567 /* SCTSTRLL */ 3568 3569 #define SCTSTRLL0 0 3570 #define SCTSTRLL1 1 3571 #define SCTSTRLL2 2 3572 #define SCTSTRLL3 3 3573 #define SCTSTRLL4 4 3574 #define SCTSTRLL5 5 3575 #define SCTSTRLL6 6 3576 #define SCTSTRLL7 7 3577 3578 /* Symbol Counter Transmit Frame Timestamp Register LH-Byte */ 3579 #define SCTSTRLH _SFR_MEM8(0xFA) 3580 3581 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3582 3583 struct __reg_SCTSTRLH { 3584 unsigned int sctstrlh : 8; /* Symbol Counter Transmit Frame Timestamp Register LH-Byte */ 3585 }; 3586 3587 #define SCTSTRLH_struct _SFR_MEM8_STRUCT(0xfa, struct __reg_SCTSTRLH) 3588 3589 #endif /* __ASSEMBLER__ */ 3590 3591 /* SCTSTRLH */ 3592 3593 #define SCTSTRLH0 0 3594 #define SCTSTRLH1 1 3595 #define SCTSTRLH2 2 3596 #define SCTSTRLH3 3 3597 #define SCTSTRLH4 4 3598 #define SCTSTRLH5 5 3599 #define SCTSTRLH6 6 3600 #define SCTSTRLH7 7 3601 3602 /* Symbol Counter Transmit Frame Timestamp Register HL-Byte */ 3603 #define SCTSTRHL _SFR_MEM8(0xFB) 3604 3605 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3606 3607 struct __reg_SCTSTRHL { 3608 unsigned int sctstrhl : 8; /* Symbol Counter Transmit Frame Timestamp Register HL-Byte */ 3609 }; 3610 3611 #define SCTSTRHL_struct _SFR_MEM8_STRUCT(0xfb, struct __reg_SCTSTRHL) 3612 3613 #endif /* __ASSEMBLER__ */ 3614 3615 /* SCTSTRHL */ 3616 3617 #define SCTSTRHL0 0 3618 #define SCTSTRHL1 1 3619 #define SCTSTRHL2 2 3620 #define SCTSTRHL3 3 3621 #define SCTSTRHL4 4 3622 #define SCTSTRHL5 5 3623 #define SCTSTRHL6 6 3624 #define SCTSTRHL7 7 3625 3626 /* Symbol Counter Transmit Frame Timestamp Register HH-Byte */ 3627 #define SCTSTRHH _SFR_MEM8(0xFC) 3628 3629 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3630 3631 struct __reg_SCTSTRHH { 3632 unsigned int sctstrhh : 8; /* Symbol Counter Transmit Frame Timestamp Register HH-Byte */ 3633 }; 3634 3635 #define SCTSTRHH_struct _SFR_MEM8_STRUCT(0xfc, struct __reg_SCTSTRHH) 3636 3637 #endif /* __ASSEMBLER__ */ 3638 3639 /* SCTSTRHH */ 3640 3641 #define SCTSTRHH0 0 3642 #define SCTSTRHH1 1 3643 #define SCTSTRHH2 2 3644 #define SCTSTRHH3 3 3645 #define SCTSTRHH4 4 3646 #define SCTSTRHH5 5 3647 #define SCTSTRHH6 6 3648 #define SCTSTRHH7 7 3649 3650 /* Multiple Address Filter Configuration Register 0 */ 3651 #define MAFCR0 _SFR_MEM8(0x10C) 3652 3653 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3654 3655 struct __reg_MAFCR0 { 3656 unsigned int maf0en : 1; /* Multiple Address Filter 0 Enable */ 3657 unsigned int maf1en : 1; /* Multiple Address Filter 1 Enable */ 3658 unsigned int maf2en : 1; /* Multiple Address Filter 2 Enable */ 3659 unsigned int maf3en : 1; /* Multiple Address Filter 3 Enable */ 3660 unsigned int : 4; 3661 }; 3662 3663 #define MAFCR0_struct _SFR_MEM8_STRUCT(0x10c, struct __reg_MAFCR0) 3664 3665 #endif /* __ASSEMBLER__ */ 3666 3667 /* MAFCR0 */ 3668 3669 #define MAF0EN 0 3670 #define MAF1EN 1 3671 #define MAF2EN 2 3672 #define MAF3EN 3 3673 3674 /* Multiple Address Filter Configuration Register 1 */ 3675 #define MAFCR1 _SFR_MEM8(0x10D) 3676 3677 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3678 3679 struct __reg_MAFCR1 { 3680 unsigned int aack_0_i_am_coord : 1; /* Enable PAN Coordinator mode for address filter 0. */ 3681 unsigned int aack_0_set_pd : 1; /* Set Data Pending bit for address filter 0. */ 3682 unsigned int aack_1_i_am_coord : 1; /* Enable PAN Coordinator mode for address filter 1. */ 3683 unsigned int aack_1_set_pd : 1; /* Set Data Pending bit for address filter 1. */ 3684 unsigned int aack_2_i_am_coord : 1; /* Enable PAN Coordinator mode for address filter 2. */ 3685 unsigned int aack_2_set_pd : 1; /* Set Data Pending bit for address filter 2. */ 3686 unsigned int aack_3_i_am_coord : 1; /* Enable PAN Coordinator mode for address filter 3. */ 3687 unsigned int aack_3_set_pd : 1; /* Set Data Pending bit for address filter 3. */ 3688 }; 3689 3690 #define MAFCR1_struct _SFR_MEM8_STRUCT(0x10d, struct __reg_MAFCR1) 3691 3692 #endif /* __ASSEMBLER__ */ 3693 3694 /* MAFCR1 */ 3695 3696 #define AACK_0_I_AM_COORD 0 3697 #define AACK_0_SET_PD 1 3698 #define AACK_1_I_AM_COORD 2 3699 #define AACK_1_SET_PD 3 3700 #define AACK_2_I_AM_COORD 4 3701 #define AACK_2_SET_PD 5 3702 #define AACK_3_I_AM_COORD 6 3703 #define AACK_3_SET_PD 7 3704 3705 /* Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte) */ 3706 #define MAFSA0L _SFR_MEM8(0x10E) 3707 3708 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3709 3710 struct __reg_MAFSA0L { 3711 unsigned int mafsa0l : 8; /* MAC Short Address low Byte for Frame Filter 0 */ 3712 }; 3713 3714 #define MAFSA0L_struct _SFR_MEM8_STRUCT(0x10e, struct __reg_MAFSA0L) 3715 3716 #endif /* __ASSEMBLER__ */ 3717 3718 /* MAFSA0L */ 3719 3720 #define MAFSA0L0 0 3721 #define MAFSA0L1 1 3722 #define MAFSA0L2 2 3723 #define MAFSA0L3 3 3724 #define MAFSA0L4 4 3725 #define MAFSA0L5 5 3726 #define MAFSA0L6 6 3727 #define MAFSA0L7 7 3728 3729 /* Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) */ 3730 #define MAFSA0H _SFR_MEM8(0x10F) 3731 3732 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3733 3734 struct __reg_MAFSA0H { 3735 unsigned int mafsa0h : 8; /* MAC Short Address high Byte for Frame Filter 0 */ 3736 }; 3737 3738 #define MAFSA0H_struct _SFR_MEM8_STRUCT(0x10f, struct __reg_MAFSA0H) 3739 3740 #endif /* __ASSEMBLER__ */ 3741 3742 /* MAFSA0H */ 3743 3744 #define MAFSA0H0 0 3745 #define MAFSA0H1 1 3746 #define MAFSA0H2 2 3747 #define MAFSA0H3 3 3748 #define MAFSA0H4 4 3749 #define MAFSA0H5 5 3750 #define MAFSA0H6 6 3751 #define MAFSA0H7 7 3752 3753 /* Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) */ 3754 #define MAFPA0L _SFR_MEM8(0x110) 3755 3756 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3757 3758 struct __reg_MAFPA0L { 3759 unsigned int mafpa0l : 8; /* MAC Personal Area Network ID low Byte for Frame Filter 0 */ 3760 }; 3761 3762 #define MAFPA0L_struct _SFR_MEM8_STRUCT(0x110, struct __reg_MAFPA0L) 3763 3764 #endif /* __ASSEMBLER__ */ 3765 3766 /* MAFPA0L */ 3767 3768 #define MAFPA0L0 0 3769 #define MAFPA0L1 1 3770 #define MAFPA0L2 2 3771 #define MAFPA0L3 3 3772 #define MAFPA0L4 4 3773 #define MAFPA0L5 5 3774 #define MAFPA0L6 6 3775 #define MAFPA0L7 7 3776 3777 /* Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte) */ 3778 #define MAFPA0H _SFR_MEM8(0x111) 3779 3780 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3781 3782 struct __reg_MAFPA0H { 3783 unsigned int mafpa0h : 8; /* MAC Personal Area Network ID high Byte for Frame Filter 0 */ 3784 }; 3785 3786 #define MAFPA0H_struct _SFR_MEM8_STRUCT(0x111, struct __reg_MAFPA0H) 3787 3788 #endif /* __ASSEMBLER__ */ 3789 3790 /* MAFPA0H */ 3791 3792 #define MAFPA0H0 0 3793 #define MAFPA0H1 1 3794 #define MAFPA0H2 2 3795 #define MAFPA0H3 3 3796 #define MAFPA0H4 4 3797 #define MAFPA0H5 5 3798 #define MAFPA0H6 6 3799 #define MAFPA0H7 7 3800 3801 /* Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte) */ 3802 #define MAFSA1L _SFR_MEM8(0x112) 3803 3804 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3805 3806 struct __reg_MAFSA1L { 3807 unsigned int mafsa1l : 8; /* MAC Short Address low Byte for Frame Filter 1 */ 3808 }; 3809 3810 #define MAFSA1L_struct _SFR_MEM8_STRUCT(0x112, struct __reg_MAFSA1L) 3811 3812 #endif /* __ASSEMBLER__ */ 3813 3814 /* MAFSA1L */ 3815 3816 #define MAFSA1L0 0 3817 #define MAFSA1L1 1 3818 #define MAFSA1L2 2 3819 #define MAFSA1L3 3 3820 #define MAFSA1L4 4 3821 #define MAFSA1L5 5 3822 #define MAFSA1L6 6 3823 #define MAFSA1L7 7 3824 3825 /* Transceiver MAC Short Address Register for Frame Filter 1 (High Byte) */ 3826 #define MAFSA1H _SFR_MEM8(0x113) 3827 3828 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3829 3830 struct __reg_MAFSA1H { 3831 unsigned int mafsa1h : 8; /* MAC Short Address high Byte for Frame Filter 1 */ 3832 }; 3833 3834 #define MAFSA1H_struct _SFR_MEM8_STRUCT(0x113, struct __reg_MAFSA1H) 3835 3836 #endif /* __ASSEMBLER__ */ 3837 3838 /* MAFSA1H */ 3839 3840 #define MAFSA1H0 0 3841 #define MAFSA1H1 1 3842 #define MAFSA1H2 2 3843 #define MAFSA1H3 3 3844 #define MAFSA1H4 4 3845 #define MAFSA1H5 5 3846 #define MAFSA1H6 6 3847 #define MAFSA1H7 7 3848 3849 /* Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte) */ 3850 #define MAFPA1L _SFR_MEM8(0x114) 3851 3852 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3853 3854 struct __reg_MAFPA1L { 3855 unsigned int mafpa1l : 8; /* MAC Personal Area Network ID low Byte for Frame Filter 1 */ 3856 }; 3857 3858 #define MAFPA1L_struct _SFR_MEM8_STRUCT(0x114, struct __reg_MAFPA1L) 3859 3860 #endif /* __ASSEMBLER__ */ 3861 3862 /* MAFPA1L */ 3863 3864 #define MAFPA1L0 0 3865 #define MAFPA1L1 1 3866 #define MAFPA1L2 2 3867 #define MAFPA1L3 3 3868 #define MAFPA1L4 4 3869 #define MAFPA1L5 5 3870 #define MAFPA1L6 6 3871 #define MAFPA1L7 7 3872 3873 /* Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte) */ 3874 #define MAFPA1H _SFR_MEM8(0x115) 3875 3876 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3877 3878 struct __reg_MAFPA1H { 3879 unsigned int mafpa1h : 8; /* MAC Personal Area Network ID high Byte for Frame Filter 1 */ 3880 }; 3881 3882 #define MAFPA1H_struct _SFR_MEM8_STRUCT(0x115, struct __reg_MAFPA1H) 3883 3884 #endif /* __ASSEMBLER__ */ 3885 3886 /* MAFPA1H */ 3887 3888 #define MAFPA1H0 0 3889 #define MAFPA1H1 1 3890 #define MAFPA1H2 2 3891 #define MAFPA1H3 3 3892 #define MAFPA1H4 4 3893 #define MAFPA1H5 5 3894 #define MAFPA1H6 6 3895 #define MAFPA1H7 7 3896 3897 /* Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte) */ 3898 #define MAFSA2L _SFR_MEM8(0x116) 3899 3900 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3901 3902 struct __reg_MAFSA2L { 3903 unsigned int mafsa2l : 8; /* MAC Short Address low Byte for Frame Filter 2 */ 3904 }; 3905 3906 #define MAFSA2L_struct _SFR_MEM8_STRUCT(0x116, struct __reg_MAFSA2L) 3907 3908 #endif /* __ASSEMBLER__ */ 3909 3910 /* MAFSA2L */ 3911 3912 #define MAFSA2L0 0 3913 #define MAFSA2L1 1 3914 #define MAFSA2L2 2 3915 #define MAFSA2L3 3 3916 #define MAFSA2L4 4 3917 #define MAFSA2L5 5 3918 #define MAFSA2L6 6 3919 #define MAFSA2L7 7 3920 3921 /* Transceiver MAC Short Address Register for Frame Filter 2 (High Byte) */ 3922 #define MAFSA2H _SFR_MEM8(0x117) 3923 3924 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3925 3926 struct __reg_MAFSA2H { 3927 unsigned int mafsa2h : 8; /* MAC Short Address high Byte for Frame Filter 2 */ 3928 }; 3929 3930 #define MAFSA2H_struct _SFR_MEM8_STRUCT(0x117, struct __reg_MAFSA2H) 3931 3932 #endif /* __ASSEMBLER__ */ 3933 3934 /* MAFSA2H */ 3935 3936 #define MAFSA2H0 0 3937 #define MAFSA2H1 1 3938 #define MAFSA2H2 2 3939 #define MAFSA2H3 3 3940 #define MAFSA2H4 4 3941 #define MAFSA2H5 5 3942 #define MAFSA2H6 6 3943 #define MAFSA2H7 7 3944 3945 /* Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte) */ 3946 #define MAFPA2L _SFR_MEM8(0x118) 3947 3948 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3949 3950 struct __reg_MAFPA2L { 3951 unsigned int mafpa2l : 8; /* MAC Personal Area Network ID low Byte for Frame Filter 2 */ 3952 }; 3953 3954 #define MAFPA2L_struct _SFR_MEM8_STRUCT(0x118, struct __reg_MAFPA2L) 3955 3956 #endif /* __ASSEMBLER__ */ 3957 3958 /* MAFPA2L */ 3959 3960 #define MAFPA2L0 0 3961 #define MAFPA2L1 1 3962 #define MAFPA2L2 2 3963 #define MAFPA2L3 3 3964 #define MAFPA2L4 4 3965 #define MAFPA2L5 5 3966 #define MAFPA2L6 6 3967 #define MAFPA2L7 7 3968 3969 /* Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte) */ 3970 #define MAFPA2H _SFR_MEM8(0x119) 3971 3972 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3973 3974 struct __reg_MAFPA2H { 3975 unsigned int mafpa2h : 8; /* MAC Personal Area Network ID high Byte for Frame Filter 2 */ 3976 }; 3977 3978 #define MAFPA2H_struct _SFR_MEM8_STRUCT(0x119, struct __reg_MAFPA2H) 3979 3980 #endif /* __ASSEMBLER__ */ 3981 3982 /* MAFPA2H */ 3983 3984 #define MAFPA2H0 0 3985 #define MAFPA2H1 1 3986 #define MAFPA2H2 2 3987 #define MAFPA2H3 3 3988 #define MAFPA2H4 4 3989 #define MAFPA2H5 5 3990 #define MAFPA2H6 6 3991 #define MAFPA2H7 7 3992 3993 /* Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) */ 3994 #define MAFSA3L _SFR_MEM8(0x11A) 3995 3996 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 3997 3998 struct __reg_MAFSA3L { 3999 unsigned int mafsa3l : 8; /* MAC Short Address low Byte for Frame Filter 3 */ 4000 }; 4001 4002 #define MAFSA3L_struct _SFR_MEM8_STRUCT(0x11a, struct __reg_MAFSA3L) 4003 4004 #endif /* __ASSEMBLER__ */ 4005 4006 /* MAFSA3L */ 4007 4008 #define MAFSA3L0 0 4009 #define MAFSA3L1 1 4010 #define MAFSA3L2 2 4011 #define MAFSA3L3 3 4012 #define MAFSA3L4 4 4013 #define MAFSA3L5 5 4014 #define MAFSA3L6 6 4015 #define MAFSA3L7 7 4016 4017 /* Transceiver MAC Short Address Register for Frame Filter 3 (High Byte) */ 4018 #define MAFSA3H _SFR_MEM8(0x11B) 4019 4020 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4021 4022 struct __reg_MAFSA3H { 4023 unsigned int mafsa3h : 8; /* MAC Short Address high Byte for Frame Filter 3 */ 4024 }; 4025 4026 #define MAFSA3H_struct _SFR_MEM8_STRUCT(0x11b, struct __reg_MAFSA3H) 4027 4028 #endif /* __ASSEMBLER__ */ 4029 4030 /* MAFSA3H */ 4031 4032 #define MAFSA3H0 0 4033 #define MAFSA3H1 1 4034 #define MAFSA3H2 2 4035 #define MAFSA3H3 3 4036 #define MAFSA3H4 4 4037 #define MAFSA3H5 5 4038 #define MAFSA3H6 6 4039 #define MAFSA3H7 7 4040 4041 /* Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte) */ 4042 #define MAFPA3L _SFR_MEM8(0x11C) 4043 4044 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4045 4046 struct __reg_MAFPA3L { 4047 unsigned int mafpa3l : 8; /* MAC Personal Area Network ID low Byte for Frame Filter 3 */ 4048 }; 4049 4050 #define MAFPA3L_struct _SFR_MEM8_STRUCT(0x11c, struct __reg_MAFPA3L) 4051 4052 #endif /* __ASSEMBLER__ */ 4053 4054 /* MAFPA3L */ 4055 4056 #define MAFPA3L0 0 4057 #define MAFPA3L1 1 4058 #define MAFPA3L2 2 4059 #define MAFPA3L3 3 4060 #define MAFPA3L4 4 4061 #define MAFPA3L5 5 4062 #define MAFPA3L6 6 4063 #define MAFPA3L7 7 4064 4065 /* Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte) */ 4066 #define MAFPA3H _SFR_MEM8(0x11D) 4067 4068 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4069 4070 struct __reg_MAFPA3H { 4071 unsigned int mafpa3h : 8; /* MAC Personal Area Network ID high Byte for Frame Filter 3 */ 4072 }; 4073 4074 #define MAFPA3H_struct _SFR_MEM8_STRUCT(0x11d, struct __reg_MAFPA3H) 4075 4076 #endif /* __ASSEMBLER__ */ 4077 4078 /* MAFPA3H */ 4079 4080 #define MAFPA3H0 0 4081 #define MAFPA3H1 1 4082 #define MAFPA3H2 2 4083 #define MAFPA3H3 3 4084 #define MAFPA3H4 4 4085 #define MAFPA3H5 5 4086 #define MAFPA3H6 6 4087 #define MAFPA3H7 7 4088 4089 /* Timer/Counter5 Control Register A */ 4090 #define TCCR5A _SFR_MEM8(0x120) 4091 4092 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4093 4094 struct __reg_TCCR5A { 4095 unsigned int wgm5 : 2; /* Waveform Generation Mode */ 4096 unsigned int com5c : 2; /* Compare Output Mode for Channel C */ 4097 unsigned int com5b : 2; /* Compare Output Mode for Channel B */ 4098 unsigned int com5a : 2; /* Compare Output Mode for Channel A */ 4099 }; 4100 4101 #define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A) 4102 4103 #endif /* __ASSEMBLER__ */ 4104 4105 /* TCCR5A */ 4106 4107 #define WGM50 0 4108 #define WGM51 1 4109 #define COM5C0 2 4110 #define COM5C1 3 4111 #define COM5B0 4 4112 #define COM5B1 5 4113 #define COM5A0 6 4114 #define COM5A1 7 4115 4116 /* Timer/Counter5 Control Register B */ 4117 #define TCCR5B _SFR_MEM8(0x121) 4118 4119 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4120 4121 struct __reg_TCCR5B { 4122 unsigned int cs5 : 3; /* Clock Select */ 4123 unsigned int wgm5 : 2; /* Waveform Generation Mode */ 4124 unsigned int : 1; 4125 unsigned int ices5 : 1; /* Input Capture 5 Edge Select */ 4126 unsigned int icnc5 : 1; /* Input Capture 5 Noise Canceller */ 4127 }; 4128 4129 #define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B) 4130 4131 #endif /* __ASSEMBLER__ */ 4132 4133 /* TCCR5B */ 4134 4135 #define CS50 0 4136 #define CS51 1 4137 #define CS52 2 4138 #define WGM52 3 4139 #define WGM53 4 4140 #define ICES5 6 4141 #define ICNC5 7 4142 4143 /* Timer/Counter5 Control Register C */ 4144 #define TCCR5C _SFR_MEM8(0x122) 4145 4146 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4147 4148 struct __reg_TCCR5C { 4149 unsigned int : 5; 4150 unsigned int foc5c : 1; /* Force Output Compare for Channel C */ 4151 unsigned int foc5b : 1; /* Force Output Compare for Channel B */ 4152 unsigned int foc5a : 1; /* Force Output Compare for Channel A */ 4153 }; 4154 4155 #define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C) 4156 4157 #endif /* __ASSEMBLER__ */ 4158 4159 /* TCCR5C */ 4160 4161 #define FOC5C 5 4162 #define FOC5B 6 4163 #define FOC5A 7 4164 4165 /* Timer/Counter5 Bytes */ 4166 #define TCNT5 _SFR_MEM16(0x124) 4167 #define TCNT5L _SFR_MEM8(0x124) 4168 #define TCNT5H _SFR_MEM8(0x125) 4169 4170 /* Timer/Counter5 Input Capture Register Bytes */ 4171 #define ICR5 _SFR_MEM16(0x126) 4172 #define ICR5L _SFR_MEM8(0x126) 4173 #define ICR5H _SFR_MEM8(0x127) 4174 4175 /* Timer/Counter5 Output Compare Register A Bytes */ 4176 #define OCR5A _SFR_MEM16(0x128) 4177 #define OCR5AL _SFR_MEM8(0x128) 4178 #define OCR5AH _SFR_MEM8(0x129) 4179 4180 /* Timer/Counter5 Output Compare Register B Bytes */ 4181 #define OCR5B _SFR_MEM16(0x12A) 4182 #define OCR5BL _SFR_MEM8(0x12A) 4183 #define OCR5BH _SFR_MEM8(0x12B) 4184 4185 /* Timer/Counter5 Output Compare Register C Bytes */ 4186 #define OCR5C _SFR_MEM16(0x12C) 4187 #define OCR5CL _SFR_MEM8(0x12C) 4188 #define OCR5CH _SFR_MEM8(0x12D) 4189 4190 /* Low Leakage Voltage Regulator Control Register */ 4191 #define LLCR _SFR_MEM8(0x12F) 4192 4193 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4194 4195 struct __reg_LLCR { 4196 unsigned int llencal : 1; /* Enable Automatic Calibration */ 4197 unsigned int llshort : 1; /* Short Lower Calibration Circuit */ 4198 unsigned int lltco : 1; /* Temperature Coefficient of Current Source */ 4199 unsigned int llcal : 1; /* Calibration Active */ 4200 unsigned int llcomp : 1; /* Comparator Output */ 4201 unsigned int lldone : 1; /* Calibration Done */ 4202 unsigned int : 2; 4203 }; 4204 4205 #define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR) 4206 4207 #endif /* __ASSEMBLER__ */ 4208 4209 /* LLCR */ 4210 4211 #define LLENCAL 0 4212 #define LLSHORT 1 4213 #define LLTCO 2 4214 #define LLCAL 3 4215 #define LLCOMP 4 4216 #define LLDONE 5 4217 4218 /* Low Leakage Voltage Regulator Data Register (Low-Byte) */ 4219 #define LLDRL _SFR_MEM8(0x130) 4220 4221 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4222 4223 struct __reg_LLDRL { 4224 unsigned int lldrl : 4; /* Low-Byte Data Register Bits */ 4225 unsigned int : 4; 4226 }; 4227 4228 #define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL) 4229 4230 #endif /* __ASSEMBLER__ */ 4231 4232 /* LLDRL */ 4233 4234 #define LLDRL0 0 4235 #define LLDRL1 1 4236 #define LLDRL2 2 4237 #define LLDRL3 3 4238 4239 /* Low Leakage Voltage Regulator Data Register (High-Byte) */ 4240 #define LLDRH _SFR_MEM8(0x131) 4241 4242 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4243 4244 struct __reg_LLDRH { 4245 unsigned int lldrh : 5; /* High-Byte Data Register Bits */ 4246 unsigned int : 3; 4247 }; 4248 4249 #define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH) 4250 4251 #endif /* __ASSEMBLER__ */ 4252 4253 /* LLDRH */ 4254 4255 #define LLDRH0 0 4256 #define LLDRH1 1 4257 #define LLDRH2 2 4258 #define LLDRH3 3 4259 #define LLDRH4 4 4260 4261 /* Data Retention Configuration Register #3 */ 4262 #define DRTRAM3 _SFR_MEM8(0x132) 4263 4264 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4265 4266 struct __reg_DRTRAM3 { 4267 unsigned int : 4; 4268 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 4269 unsigned int drtswok : 1; /* DRT Switch OK */ 4270 unsigned int : 2; 4271 }; 4272 4273 #define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3) 4274 4275 #endif /* __ASSEMBLER__ */ 4276 4277 /* DRTRAM3 */ 4278 4279 #define ENDRT 4 4280 #define DRTSWOK 5 4281 4282 /* Data Retention Configuration Register #2 */ 4283 #define DRTRAM2 _SFR_MEM8(0x133) 4284 4285 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4286 4287 struct __reg_DRTRAM2 { 4288 unsigned int : 4; 4289 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 4290 unsigned int drtswok : 1; /* DRT Switch OK */ 4291 unsigned int : 2; 4292 }; 4293 4294 #define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2) 4295 4296 #endif /* __ASSEMBLER__ */ 4297 4298 /* DRTRAM2 */ 4299 4300 #define ENDRT 4 4301 #define DRTSWOK 5 4302 4303 /* Data Retention Configuration Register #1 */ 4304 #define DRTRAM1 _SFR_MEM8(0x134) 4305 4306 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4307 4308 struct __reg_DRTRAM1 { 4309 unsigned int : 4; 4310 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 4311 unsigned int drtswok : 1; /* DRT Switch OK */ 4312 unsigned int : 2; 4313 }; 4314 4315 #define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1) 4316 4317 #endif /* __ASSEMBLER__ */ 4318 4319 /* DRTRAM1 */ 4320 4321 #define ENDRT 4 4322 #define DRTSWOK 5 4323 4324 /* Data Retention Configuration Register #0 */ 4325 #define DRTRAM0 _SFR_MEM8(0x135) 4326 4327 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4328 4329 struct __reg_DRTRAM0 { 4330 unsigned int : 4; 4331 unsigned int endrt : 1; /* Enable SRAM Data Retention */ 4332 unsigned int drtswok : 1; /* DRT Switch OK */ 4333 unsigned int : 2; 4334 }; 4335 4336 #define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0) 4337 4338 #endif /* __ASSEMBLER__ */ 4339 4340 /* DRTRAM0 */ 4341 4342 #define ENDRT 4 4343 #define DRTSWOK 5 4344 4345 /* Port Driver Strength Register 0 */ 4346 #define DPDS0 _SFR_MEM8(0x136) 4347 4348 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4349 4350 struct __reg_DPDS0 { 4351 unsigned int pbdrv : 2; /* Driver Strength Port B */ 4352 unsigned int pddrv : 2; /* Driver Strength Port D */ 4353 unsigned int pedrv : 2; /* Driver Strength Port E */ 4354 unsigned int pfdrv : 2; /* Driver Strength Port F */ 4355 }; 4356 4357 #define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0) 4358 4359 #endif /* __ASSEMBLER__ */ 4360 4361 /* DPDS0 */ 4362 4363 #define PBDRV0 0 4364 #define PBDRV1 1 4365 #define PDDRV0 2 4366 #define PDDRV1 3 4367 #define PEDRV0 4 4368 #define PEDRV1 5 4369 #define PFDRV0 6 4370 #define PFDRV1 7 4371 4372 /* Port Driver Strength Register 1 */ 4373 #define DPDS1 _SFR_MEM8(0x137) 4374 4375 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4376 4377 struct __reg_DPDS1 { 4378 unsigned int pgdrv : 2; /* Driver Strength Port G */ 4379 unsigned int : 6; 4380 }; 4381 4382 #define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1) 4383 4384 #endif /* __ASSEMBLER__ */ 4385 4386 /* DPDS1 */ 4387 4388 #define PGDRV0 0 4389 #define PGDRV1 1 4390 4391 /* Power Amplifier Ramp up/down Control Register */ 4392 #define PARCR _SFR_MEM8(0x138) 4393 4394 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4395 4396 struct __reg_PARCR { 4397 unsigned int parufi : 1; /* Power Amplifier Ramp Up Frequency Inversion */ 4398 unsigned int pardfi : 1; /* Power Amplifier Ramp Down Frequency Inversion */ 4399 unsigned int paltu : 3; /* ext. PA Ramp Up Lead Time */ 4400 unsigned int paltd : 3; /* ext. PA Ramp Down Lead Time */ 4401 }; 4402 4403 #define PARCR_struct _SFR_MEM8_STRUCT(0x138, struct __reg_PARCR) 4404 4405 /* symbolic names */ 4406 4407 #define PALTU_MINUS_3US 0 4408 #define PALTU_MINUS_2US 1 4409 #define PALTU_MINUS_1US 2 4410 #define PALTU_0US 3 4411 #define PALTU_1US 4 4412 #define PALTU_2US 5 4413 #define PALTU_3US 6 4414 #define PALTU_4US 7 4415 #define PALTD_MINUS_3US 0 4416 #define PALTD_MINUS_2US 1 4417 #define PALTD_MINUS_1US 2 4418 #define PALTD_0US 3 4419 #define PALTD_1US 4 4420 #define PALTD_2US 5 4421 #define PALTD_3US 6 4422 #define PALTD_4US 7 4423 4424 #endif /* __ASSEMBLER__ */ 4425 4426 /* PARCR */ 4427 4428 #define PARUFI 0 4429 #define PARDFI 1 4430 #define PALTU0 2 4431 #define PALTU1 3 4432 #define PALTU2 4 4433 #define PALTD0 5 4434 #define PALTD1 6 4435 #define PALTD2 7 4436 4437 /* Transceiver Pin Register */ 4438 #define TRXPR _SFR_MEM8(0x139) 4439 4440 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4441 4442 struct __reg_TRXPR { 4443 unsigned int trxrst : 1; /* Force Transceiver Reset */ 4444 unsigned int slptr : 1; /* Multi-purpose Transceiver Control Bit */ 4445 unsigned int : 6; 4446 }; 4447 4448 #define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR) 4449 4450 #endif /* __ASSEMBLER__ */ 4451 4452 /* TRXPR */ 4453 4454 #define TRXRST 0 4455 #define SLPTR 1 4456 4457 /* AES Control Register */ 4458 #define AES_CTRL _SFR_MEM8(0x13C) 4459 4460 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4461 4462 struct __reg_AES_CTRL { 4463 unsigned int : 2; 4464 unsigned int aes_im : 1; /* AES Interrupt Enable */ 4465 unsigned int aes_dir : 1; /* Set AES Operation Direction */ 4466 unsigned int : 1; 4467 unsigned int aes_mode : 1; /* Set AES Operation Mode */ 4468 unsigned int : 1; 4469 unsigned int aes_request : 1; /* Request AES Operation. */ 4470 }; 4471 4472 #define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL) 4473 4474 /* symbolic names */ 4475 4476 #define AES_DIR_ENC 0 4477 #define AES_DIR_DEC 1 4478 #define AES_MODE_ECB 0 4479 #define AES_MODE_CBC 1 4480 4481 #endif /* __ASSEMBLER__ */ 4482 4483 /* AES_CTRL */ 4484 4485 #define AES_IM 2 4486 #define AES_DIR 3 4487 #define AES_MODE 5 4488 #define AES_REQUEST 7 4489 4490 /* AES Status Register */ 4491 #define AES_STATUS _SFR_MEM8(0x13D) 4492 4493 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4494 4495 struct __reg_AES_STATUS { 4496 unsigned int aes_done : 1; /* AES Operation Finished with Success */ 4497 unsigned int : 6; 4498 unsigned int aes_er : 1; /* AES Operation Finished with Error */ 4499 }; 4500 4501 #define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS) 4502 4503 #endif /* __ASSEMBLER__ */ 4504 4505 /* AES_STATUS */ 4506 4507 #define AES_DONE 0 4508 #define AES_ER 7 4509 4510 /* AES Plain and Cipher Text Buffer Register */ 4511 #define AES_STATE _SFR_MEM8(0x13E) 4512 4513 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4514 4515 struct __reg_AES_STATE { 4516 unsigned int aes_state : 8; /* AES Plain and Cipher Text Buffer */ 4517 }; 4518 4519 #define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE) 4520 4521 #endif /* __ASSEMBLER__ */ 4522 4523 /* AES_STATE */ 4524 4525 #define AES_STATE0 0 4526 #define AES_STATE1 1 4527 #define AES_STATE2 2 4528 #define AES_STATE3 3 4529 #define AES_STATE4 4 4530 #define AES_STATE5 5 4531 #define AES_STATE6 6 4532 #define AES_STATE7 7 4533 4534 /* AES Encryption and Decryption Key Buffer Register */ 4535 #define AES_KEY _SFR_MEM8(0x13F) 4536 4537 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4538 4539 struct __reg_AES_KEY { 4540 unsigned int aes_key : 8; /* AES Encryption/Decryption Key Buffer */ 4541 }; 4542 4543 #define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY) 4544 4545 #endif /* __ASSEMBLER__ */ 4546 4547 /* AES_KEY */ 4548 4549 #define AES_KEY0 0 4550 #define AES_KEY1 1 4551 #define AES_KEY2 2 4552 #define AES_KEY3 3 4553 #define AES_KEY4 4 4554 #define AES_KEY5 5 4555 #define AES_KEY6 6 4556 #define AES_KEY7 7 4557 4558 /* Transceiver Status Register */ 4559 #define TRX_STATUS _SFR_MEM8(0x141) 4560 4561 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4562 4563 struct __reg_TRX_STATUS { 4564 unsigned int trx_status : 5; /* Transceiver Main Status */ 4565 unsigned int tst_status : 1; /* Test mode status */ 4566 unsigned int cca_status : 1; /* CCA Status Result */ 4567 unsigned int cca_done : 1; /* CCA Algorithm Status */ 4568 }; 4569 4570 #define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS) 4571 4572 /* symbolic names */ 4573 4574 #define BUSY_RX 1 4575 #define BUSY_TX 2 4576 #define RX_ON 6 4577 #define TRX_OFF 8 4578 #define PLL_ON 9 4579 #define SLEEP 15 4580 #define BUSY_RX_AACK 17 4581 #define BUSY_TX_ARET 18 4582 #define RX_AACK_ON 22 4583 #define TX_ARET_ON 25 4584 #define STATE_TRANSITION_IN_PROGRESS 31 4585 #define TST_DISABLED 0 4586 #define TST_ENABLED 1 4587 #define CCA_BUSY 0 4588 #define CCA_IDLE 1 4589 #define CCA_NOT_FIN 0 4590 #define CCA_FIN 1 4591 4592 #endif /* __ASSEMBLER__ */ 4593 4594 /* TRX_STATUS */ 4595 4596 #define TRX_STATUS0 0 4597 #define TRX_STATUS1 1 4598 #define TRX_STATUS2 2 4599 #define TRX_STATUS3 3 4600 #define TRX_STATUS4 4 4601 #define TST_STATUS 5 4602 #define CCA_STATUS 6 4603 #define CCA_DONE 7 4604 4605 /* Transceiver State Control Register */ 4606 #define TRX_STATE _SFR_MEM8(0x142) 4607 4608 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4609 4610 struct __reg_TRX_STATE { 4611 unsigned int trx_cmd : 5; /* State Control Command */ 4612 unsigned int trac_status : 3; /* Transaction Status */ 4613 }; 4614 4615 #define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE) 4616 4617 /* symbolic names */ 4618 4619 #define CMD_NOP 0 4620 #define CMD_TX_START 2 4621 #define CMD_FORCE_TRX_OFF 3 4622 #define CMD_FORCE_PLL_ON 4 4623 #define CMD_RX_ON 6 4624 #define CMD_TRX_OFF 8 4625 #define CMD_PLL_ON 9 4626 #define CMD_RX_AACK_ON 22 4627 #define CMD_TX_ARET_ON 25 4628 #define TRAC_SUCCESS 0 4629 #define TRAC_SUCCESS_DATA_PENDING 1 4630 #define TRAC_SUCCESS_WAIT_FOR_ACK 2 4631 #define TRAC_CHANNEL_ACCESS_FAILURE 3 4632 #define TRAC_NO_ACK 5 4633 #define TRAC_INVALID 7 4634 4635 #endif /* __ASSEMBLER__ */ 4636 4637 /* TRX_STATE */ 4638 4639 #define TRX_CMD0 0 4640 #define TRX_CMD1 1 4641 #define TRX_CMD2 2 4642 #define TRX_CMD3 3 4643 #define TRX_CMD4 4 4644 #define TRAC_STATUS0 5 4645 #define TRAC_STATUS1 6 4646 #define TRAC_STATUS2 7 4647 4648 /* Tranceiver Control Register 0 */ 4649 #define TRX_CTRL_0 _SFR_MEM8(0x143) 4650 4651 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4652 4653 struct __reg_TRX_CTRL_0 { 4654 unsigned int : 4; 4655 unsigned int pmu_if_inv : 1; /* PMU IF Inverse */ 4656 unsigned int pmu_start : 1; /* Start of Phase Measurement Unit */ 4657 unsigned int pmu_en : 1; /* Enable Phase Measurement Unit */ 4658 unsigned int res7 : 1; /* Reserved */ 4659 }; 4660 4661 #define TRX_CTRL_0_struct _SFR_MEM8_STRUCT(0x143, struct __reg_TRX_CTRL_0) 4662 4663 #endif /* __ASSEMBLER__ */ 4664 4665 /* TRX_CTRL_0 */ 4666 4667 #define PMU_IF_INV 4 4668 #define PMU_START 5 4669 #define PMU_EN 6 4670 4671 /* Transceiver Control Register 1 */ 4672 #define TRX_CTRL_1 _SFR_MEM8(0x144) 4673 4674 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4675 4676 struct __reg_TRX_CTRL_1 { 4677 unsigned int : 4; 4678 unsigned int pll_tx_flt : 1; /* Enable PLL TX Filter */ 4679 unsigned int tx_auto_crc_on : 1; /* Enable Automatic CRC Calculation */ 4680 unsigned int irq_2_ext_en : 1; /* Connect Frame Start IRQ to TC1 */ 4681 unsigned int pa_ext_en : 1; /* External PA support enable */ 4682 }; 4683 4684 #define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1) 4685 4686 #endif /* __ASSEMBLER__ */ 4687 4688 /* TRX_CTRL_1 */ 4689 4690 #define PLL_TX_FLT 4 4691 #define TX_AUTO_CRC_ON 5 4692 #define IRQ_2_EXT_EN 6 4693 #define PA_EXT_EN 7 4694 4695 /* Transceiver Transmit Power Control Register */ 4696 #define PHY_TX_PWR _SFR_MEM8(0x145) 4697 4698 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4699 4700 struct __reg_PHY_TX_PWR { 4701 unsigned int tx_pwr : 4; /* Transmit Power Setting */ 4702 unsigned int : 4; 4703 }; 4704 4705 #define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR) 4706 4707 #endif /* __ASSEMBLER__ */ 4708 4709 /* PHY_TX_PWR */ 4710 4711 #define TX_PWR0 0 4712 #define TX_PWR1 1 4713 #define TX_PWR2 2 4714 #define TX_PWR3 3 4715 4716 /* Receiver Signal Strength Indicator Register */ 4717 #define PHY_RSSI _SFR_MEM8(0x146) 4718 4719 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4720 4721 struct __reg_PHY_RSSI { 4722 unsigned int rssi : 5; /* Receiver Signal Strength Indicator */ 4723 unsigned int rnd_value : 2; /* Random Value */ 4724 unsigned int rx_crc_valid : 1; /* Received Frame CRC Status */ 4725 }; 4726 4727 #define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI) 4728 4729 /* symbolic names */ 4730 4731 #define RSSI_MIN 0 4732 #define RSSI_MIN_PLUS_3dB 1 4733 #define RSSI_MAX 28 4734 #define CRC_INVALID 0 4735 #define CRC_VALID 1 4736 4737 #endif /* __ASSEMBLER__ */ 4738 4739 /* PHY_RSSI */ 4740 4741 #define RSSI0 0 4742 #define RSSI1 1 4743 #define RSSI2 2 4744 #define RSSI3 3 4745 #define RSSI4 4 4746 #define RND_VALUE0 5 4747 #define RND_VALUE1 6 4748 #define RX_CRC_VALID 7 4749 4750 /* Transceiver Energy Detection Level Register */ 4751 #define PHY_ED_LEVEL _SFR_MEM8(0x147) 4752 4753 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4754 4755 struct __reg_PHY_ED_LEVEL { 4756 unsigned int ed_level : 8; /* Energy Detection Level */ 4757 }; 4758 4759 #define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL) 4760 4761 /* symbolic names */ 4762 4763 #define ED_MIN 0 4764 #define ED_MIN_PLUS_1dB 1 4765 #define ED_MAX 83 4766 #define ED_RESET 255 4767 4768 #endif /* __ASSEMBLER__ */ 4769 4770 /* PHY_ED_LEVEL */ 4771 4772 #define ED_LEVEL0 0 4773 #define ED_LEVEL1 1 4774 #define ED_LEVEL2 2 4775 #define ED_LEVEL3 3 4776 #define ED_LEVEL4 4 4777 #define ED_LEVEL5 5 4778 #define ED_LEVEL6 6 4779 #define ED_LEVEL7 7 4780 4781 /* Transceiver Clear Channel Assessment (CCA) Control Register */ 4782 #define PHY_CC_CCA _SFR_MEM8(0x148) 4783 4784 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4785 4786 struct __reg_PHY_CC_CCA { 4787 unsigned int channel : 5; /* RX/TX Channel Selection */ 4788 unsigned int cca_mode : 2; /* Select CCA Measurement Mode */ 4789 unsigned int cca_request : 1; /* Manual CCA Measurement Request */ 4790 }; 4791 4792 #define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA) 4793 4794 /* symbolic names */ 4795 4796 #define F_2405MHZ 11 4797 #define F_2410MHZ 12 4798 #define F_2415MHZ 13 4799 #define F_2420MHZ 14 4800 #define F_2425MHZ 15 4801 #define F_2430MHZ 16 4802 #define F_2435MHZ 17 4803 #define F_2440MHZ 18 4804 #define F_2445MHZ 19 4805 #define F_2450MHZ 20 4806 #define F_2455MHZ 21 4807 #define F_2460MHZ 22 4808 #define F_2465MHZ 23 4809 #define F_2470MHZ 24 4810 #define F_2475MHZ 25 4811 #define F_2480MHZ 26 4812 #define CCA_CS_OR_ED 0 4813 #define CCA_ED 1 4814 #define CCA_CS 2 4815 #define CCA_CS_AND_ED 3 4816 4817 #endif /* __ASSEMBLER__ */ 4818 4819 /* PHY_CC_CCA */ 4820 4821 #define CHANNEL0 0 4822 #define CHANNEL1 1 4823 #define CHANNEL2 2 4824 #define CHANNEL3 3 4825 #define CHANNEL4 4 4826 #define CCA_MODE0 5 4827 #define CCA_MODE1 6 4828 #define CCA_REQUEST 7 4829 4830 /* Transceiver CCA Threshold Setting Register */ 4831 #define CCA_THRES _SFR_MEM8(0x149) 4832 4833 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4834 4835 struct __reg_CCA_THRES { 4836 unsigned int cca_ed_thres : 4; /* ED Threshold Level for CCA Measurement */ 4837 unsigned int cca_cs_thres : 4; /* CS Threshold Level for CCA Measurement */ 4838 }; 4839 4840 #define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES) 4841 4842 #endif /* __ASSEMBLER__ */ 4843 4844 /* CCA_THRES */ 4845 4846 #define CCA_ED_THRES0 0 4847 #define CCA_ED_THRES1 1 4848 #define CCA_ED_THRES2 2 4849 #define CCA_ED_THRES3 3 4850 #define CCA_CS_THRES0 4 4851 #define CCA_CS_THRES1 5 4852 #define CCA_CS_THRES2 6 4853 #define CCA_CS_THRES3 7 4854 4855 /* Transceiver Receive Control Register */ 4856 #define RX_CTRL _SFR_MEM8(0x14A) 4857 4858 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4859 4860 struct __reg_RX_CTRL { 4861 unsigned int pdt_thres : 4; /* Receiver Sensitivity Control */ 4862 unsigned int : 4; 4863 }; 4864 4865 #define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL) 4866 4867 /* symbolic names */ 4868 4869 #define PDT_THRES_ANT_DIV_OFF 7 4870 #define PDT_THRES_ANT_DIV_ON 3 4871 4872 #endif /* __ASSEMBLER__ */ 4873 4874 /* RX_CTRL */ 4875 4876 #define PDT_THRES0 0 4877 #define PDT_THRES1 1 4878 #define PDT_THRES2 2 4879 #define PDT_THRES3 3 4880 4881 /* Start of Frame Delimiter Value Register */ 4882 #define SFD_VALUE _SFR_MEM8(0x14B) 4883 4884 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4885 4886 struct __reg_SFD_VALUE { 4887 unsigned int sfd_value : 8; /* Start of Frame Delimiter Value */ 4888 }; 4889 4890 #define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE) 4891 4892 /* symbolic names */ 4893 4894 #define IEEE_SFD 167 4895 4896 #endif /* __ASSEMBLER__ */ 4897 4898 /* SFD_VALUE */ 4899 4900 #define SFD_VALUE0 0 4901 #define SFD_VALUE1 1 4902 #define SFD_VALUE2 2 4903 #define SFD_VALUE3 3 4904 #define SFD_VALUE4 4 4905 #define SFD_VALUE5 5 4906 #define SFD_VALUE6 6 4907 #define SFD_VALUE7 7 4908 4909 /* Transceiver Control Register 2 */ 4910 #define TRX_CTRL_2 _SFR_MEM8(0x14C) 4911 4912 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4913 4914 struct __reg_TRX_CTRL_2 { 4915 unsigned int oqpsk_data_rate : 2; /* Data Rate Selection */ 4916 unsigned int : 5; 4917 unsigned int rx_safe_mode : 1; /* RX Safe Mode */ 4918 }; 4919 4920 #define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2) 4921 4922 /* symbolic names */ 4923 4924 #define RATE_250KB 0 4925 #define RATE_500KB 1 4926 #define RATE_1000KB 2 4927 #define RATE_2000KB 3 4928 4929 #endif /* __ASSEMBLER__ */ 4930 4931 /* TRX_CTRL_2 */ 4932 4933 #define OQPSK_DATA_RATE0 0 4934 #define OQPSK_DATA_RATE1 1 4935 #define RX_SAFE_MODE 7 4936 4937 /* Antenna Diversity Control Register */ 4938 #define ANT_DIV _SFR_MEM8(0x14D) 4939 4940 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4941 4942 struct __reg_ANT_DIV { 4943 unsigned int ant_ctrl : 2; /* Static Antenna Diversity Switch Control */ 4944 unsigned int ant_ext_sw_en : 1; /* Enable External Antenna Switch Control */ 4945 unsigned int ant_div_en : 1; /* Enable Antenna Diversity */ 4946 unsigned int : 3; 4947 unsigned int ant_sel : 1; /* Antenna Diversity Antenna Status */ 4948 }; 4949 4950 #define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV) 4951 4952 /* symbolic names */ 4953 4954 #define ANT_1 1 4955 #define ANT_0 2 4956 #define ANT_RESET 3 4957 #define ANT_DIV_EXT_SW_DIS 0 4958 #define ANT_DIV_EXT_SW_EN 1 4959 #define ANTENNA_0 0 4960 #define ANTENNA_1 1 4961 4962 #endif /* __ASSEMBLER__ */ 4963 4964 /* ANT_DIV */ 4965 4966 #define ANT_CTRL0 0 4967 #define ANT_CTRL1 1 4968 #define ANT_EXT_SW_EN 2 4969 #define ANT_DIV_EN 3 4970 #define ANT_SEL 7 4971 4972 /* Transceiver Interrupt Enable Register */ 4973 #define IRQ_MASK _SFR_MEM8(0x14E) 4974 4975 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 4976 4977 struct __reg_IRQ_MASK { 4978 unsigned int pll_lock_en : 1; /* PLL Lock Interrupt Enable */ 4979 unsigned int pll_unlock_en : 1; /* PLL Unlock Interrupt Enable */ 4980 unsigned int rx_start_en : 1; /* RX_START Interrupt Enable */ 4981 unsigned int rx_end_en : 1; /* RX_END Interrupt Enable */ 4982 unsigned int cca_ed_done_en : 1; /* End of ED Measurement Interrupt Enable */ 4983 unsigned int ami_en : 1; /* Address Match Interrupt Enable */ 4984 unsigned int tx_end_en : 1; /* TX_END Interrupt Enable */ 4985 unsigned int awake_en : 1; /* Awake Interrupt Enable */ 4986 }; 4987 4988 #define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK) 4989 4990 #endif /* __ASSEMBLER__ */ 4991 4992 /* IRQ_MASK */ 4993 4994 #define PLL_LOCK_EN 0 4995 #define PLL_UNLOCK_EN 1 4996 #define RX_START_EN 2 4997 #define RX_END_EN 3 4998 #define CCA_ED_DONE_EN 4 4999 #define AMI_EN 5 5000 #define TX_END_EN 6 5001 #define AWAKE_EN 7 5002 5003 /* Transceiver Interrupt Status Register */ 5004 #define IRQ_STATUS _SFR_MEM8(0x14F) 5005 5006 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5007 5008 struct __reg_IRQ_STATUS { 5009 unsigned int pll_lock : 1; /* PLL Lock Interrupt Status */ 5010 unsigned int pll_unlock : 1; /* PLL Unlock Interrupt Status */ 5011 unsigned int rx_start : 1; /* RX_START Interrupt Status */ 5012 unsigned int rx_end : 1; /* RX_END Interrupt Status */ 5013 unsigned int cca_ed_done : 1; /* End of ED Measurement Interrupt Status */ 5014 unsigned int ami : 1; /* Address Match Interrupt Status */ 5015 unsigned int tx_end : 1; /* TX_END Interrupt Status */ 5016 unsigned int awake : 1; /* Awake Interrupt Status */ 5017 }; 5018 5019 #define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS) 5020 5021 #endif /* __ASSEMBLER__ */ 5022 5023 /* IRQ_STATUS */ 5024 5025 #define PLL_LOCK 0 5026 #define PLL_UNLOCK 1 5027 #define RX_START 2 5028 #define RX_END 3 5029 #define CCA_ED_DONE 4 5030 #define AMI 5 5031 #define TX_END 6 5032 #define AWAKE 7 5033 5034 /* Voltage Regulator Control and Status Register */ 5035 #define VREG_CTRL _SFR_MEM8(0x150) 5036 5037 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5038 5039 struct __reg_VREG_CTRL { 5040 unsigned int : 2; 5041 unsigned int dvdd_ok : 1; /* DVDD Supply Voltage Valid */ 5042 unsigned int dvreg_ext : 1; /* Use External DVDD Regulator */ 5043 unsigned int : 2; 5044 unsigned int avdd_ok : 1; /* AVDD Supply Voltage Valid */ 5045 unsigned int avreg_ext : 1; /* Use External AVDD Regulator */ 5046 }; 5047 5048 #define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL) 5049 5050 /* symbolic names */ 5051 5052 #define DVDD_INT 0 5053 #define DVDD_EXT 1 5054 #define AVDD_INT 0 5055 #define AVDD_EXT 1 5056 5057 #endif /* __ASSEMBLER__ */ 5058 5059 /* VREG_CTRL */ 5060 5061 #define DVDD_OK 2 5062 #define DVREG_EXT 3 5063 #define AVDD_OK 6 5064 #define AVREG_EXT 7 5065 5066 /* Battery Monitor Control and Status Register */ 5067 #define BATMON _SFR_MEM8(0x151) 5068 5069 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5070 5071 struct __reg_BATMON { 5072 unsigned int batmon_vth : 4; /* Battery Monitor Threshold Voltage */ 5073 unsigned int batmon_hr : 1; /* Battery Monitor Voltage Range */ 5074 unsigned int batmon_ok : 1; /* Battery Monitor Status */ 5075 unsigned int bat_low_en : 1; /* Battery Monitor Interrupt Enable */ 5076 unsigned int bat_low : 1; /* Battery Monitor Interrupt Status */ 5077 }; 5078 5079 #define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON) 5080 5081 /* symbolic names */ 5082 5083 #define BATMON_HR_DIS 0 5084 #define BATMON_HR_EN 1 5085 5086 #endif /* __ASSEMBLER__ */ 5087 5088 /* BATMON */ 5089 5090 #define BATMON_VTH0 0 5091 #define BATMON_VTH1 1 5092 #define BATMON_VTH2 2 5093 #define BATMON_VTH3 3 5094 #define BATMON_HR 4 5095 #define BATMON_OK 5 5096 #define BAT_LOW_EN 6 5097 #define BAT_LOW 7 5098 5099 /* Crystal Oscillator Control Register */ 5100 #define XOSC_CTRL _SFR_MEM8(0x152) 5101 5102 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5103 5104 struct __reg_XOSC_CTRL { 5105 unsigned int xtal_trim : 4; /* Crystal Oscillator Load Capacitance Trimming */ 5106 unsigned int xtal_mode : 4; /* Crystal Oscillator Operating Mode */ 5107 }; 5108 5109 #define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL) 5110 5111 /* symbolic names */ 5112 5113 #define XTAL_TRIM_MIN 0 5114 #define XTAL_TRIM_MAX 15 5115 5116 #endif /* __ASSEMBLER__ */ 5117 5118 /* XOSC_CTRL */ 5119 5120 #define XTAL_TRIM0 0 5121 #define XTAL_TRIM1 1 5122 #define XTAL_TRIM2 2 5123 #define XTAL_TRIM3 3 5124 #define XTAL_MODE0 4 5125 #define XTAL_MODE1 5 5126 #define XTAL_MODE2 6 5127 #define XTAL_MODE3 7 5128 5129 /* Channel Control Register 0 */ 5130 #define CC_CTRL_0 _SFR_MEM8(0x153) 5131 5132 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5133 5134 struct __reg_CC_CTRL_0 { 5135 unsigned int cc_number : 8; /* Channel Number */ 5136 }; 5137 5138 #define CC_CTRL_0_struct _SFR_MEM8_STRUCT(0x153, struct __reg_CC_CTRL_0) 5139 5140 #endif /* __ASSEMBLER__ */ 5141 5142 /* CC_CTRL_0 */ 5143 5144 #define CC_NUMBER0 0 5145 #define CC_NUMBER1 1 5146 #define CC_NUMBER2 2 5147 #define CC_NUMBER3 3 5148 #define CC_NUMBER4 4 5149 #define CC_NUMBER5 5 5150 #define CC_NUMBER6 6 5151 #define CC_NUMBER7 7 5152 5153 /* Channel Control Register 1 */ 5154 #define CC_CTRL_1 _SFR_MEM8(0x154) 5155 5156 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5157 5158 struct __reg_CC_CTRL_1 { 5159 unsigned int cc_band : 4; /* Channel Band */ 5160 unsigned int : 4; 5161 }; 5162 5163 #define CC_CTRL_1_struct _SFR_MEM8_STRUCT(0x154, struct __reg_CC_CTRL_1) 5164 5165 #endif /* __ASSEMBLER__ */ 5166 5167 /* CC_CTRL_1 */ 5168 5169 #define CC_BAND0 0 5170 #define CC_BAND1 1 5171 #define CC_BAND2 2 5172 #define CC_BAND3 3 5173 5174 /* Transceiver Receiver Sensitivity Control Register */ 5175 #define RX_SYN _SFR_MEM8(0x155) 5176 5177 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5178 5179 struct __reg_RX_SYN { 5180 unsigned int rx_pdt_level : 4; /* Reduce Receiver Sensitivity */ 5181 unsigned int : 2; 5182 unsigned int rx_override : 1; /* Receiver Override Function */ 5183 unsigned int rx_pdt_dis : 1; /* Prevent Frame Reception */ 5184 }; 5185 5186 #define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN) 5187 5188 /* symbolic names */ 5189 5190 #define RX_PDT_LEVEL_MIN 0 5191 #define RX_PDT_LEVEL_MAX 15 5192 5193 #endif /* __ASSEMBLER__ */ 5194 5195 /* RX_SYN */ 5196 5197 #define RX_PDT_LEVEL0 0 5198 #define RX_PDT_LEVEL1 1 5199 #define RX_PDT_LEVEL2 2 5200 #define RX_PDT_LEVEL3 3 5201 #define RX_OVERRIDE 6 5202 #define RX_PDT_DIS 7 5203 5204 /* Transceiver Reduced Power Consumption Control */ 5205 #define TRX_RPC _SFR_MEM8(0x156) 5206 5207 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5208 5209 struct __reg_TRX_RPC { 5210 unsigned int : 1; 5211 unsigned int ipan_rpc_en : 1; /* Smart Receiving Mode IPAN Handling Enable */ 5212 unsigned int res0 : 1; /* Reserved */ 5213 unsigned int pll_rpc_en : 1; /* PLL Smart Receiving Mode Enable */ 5214 unsigned int pdt_rpc_en : 1; /* Smart Receiving Mode Reduced Sensitivity Enable */ 5215 unsigned int rx_rpc_en : 1; /* Receiver Smart Receiving Mode Enable */ 5216 unsigned int rx_rpc_ctrl : 2; /* Smart Receiving Mode Timing */ 5217 }; 5218 5219 #define TRX_RPC_struct _SFR_MEM8_STRUCT(0x156, struct __reg_TRX_RPC) 5220 5221 #endif /* __ASSEMBLER__ */ 5222 5223 /* TRX_RPC */ 5224 5225 #define IPAN_RPC_EN 1 5226 #define PLL_RPC_EN 3 5227 #define PDT_RPC_EN 4 5228 #define RX_RPC_EN 5 5229 #define RX_RPC_CTRL0 6 5230 #define RX_RPC_CTRL1 7 5231 5232 /* Transceiver Acknowledgment Frame Control Register 1 */ 5233 #define XAH_CTRL_1 _SFR_MEM8(0x157) 5234 5235 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5236 5237 struct __reg_XAH_CTRL_1 { 5238 unsigned int : 1; 5239 unsigned int aack_prom_mode : 1; /* Enable Promiscuous Mode */ 5240 unsigned int aack_ack_time : 1; /* Reduce Acknowledgment Time */ 5241 unsigned int : 1; 5242 unsigned int aack_upld_res_ft : 1; /* Process Reserved Frames */ 5243 unsigned int aack_fltr_res_ft : 1; /* Filter Reserved Frames */ 5244 unsigned int : 2; 5245 }; 5246 5247 #define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1) 5248 5249 /* symbolic names */ 5250 5251 #define AACK_ACK_TIME_12_SYM 0 5252 #define AACK_ACK_TIME_2_SYM 1 5253 5254 #endif /* __ASSEMBLER__ */ 5255 5256 /* XAH_CTRL_1 */ 5257 5258 #define AACK_PROM_MODE 1 5259 #define AACK_ACK_TIME 2 5260 #define AACK_UPLD_RES_FT 4 5261 #define AACK_FLTR_RES_FT 5 5262 5263 /* Transceiver Filter Tuning Control Register */ 5264 #define FTN_CTRL _SFR_MEM8(0x158) 5265 5266 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5267 5268 struct __reg_FTN_CTRL { 5269 unsigned int : 7; 5270 unsigned int ftn_start : 1; /* Start Calibration Loop of Filter Tuning Network */ 5271 }; 5272 5273 #define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL) 5274 5275 #endif /* __ASSEMBLER__ */ 5276 5277 /* FTN_CTRL */ 5278 5279 #define FTN_START 7 5280 5281 /* Transceiver Center Frequency Calibration Control Register */ 5282 #define PLL_CF _SFR_MEM8(0x15A) 5283 5284 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5285 5286 struct __reg_PLL_CF { 5287 unsigned int : 7; 5288 unsigned int pll_cf_start : 1; /* Start Center Frequency Calibration */ 5289 }; 5290 5291 #define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF) 5292 5293 #endif /* __ASSEMBLER__ */ 5294 5295 /* PLL_CF */ 5296 5297 #define PLL_CF_START 7 5298 5299 /* Transceiver Delay Cell Calibration Control Register */ 5300 #define PLL_DCU _SFR_MEM8(0x15B) 5301 5302 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5303 5304 struct __reg_PLL_DCU { 5305 unsigned int : 7; 5306 unsigned int pll_dcu_start : 1; /* Start Delay Cell Calibration */ 5307 }; 5308 5309 #define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU) 5310 5311 #endif /* __ASSEMBLER__ */ 5312 5313 /* PLL_DCU */ 5314 5315 #define PLL_DCU_START 7 5316 5317 /* Device Identification Register (Part Number) */ 5318 #define PART_NUM _SFR_MEM8(0x15C) 5319 5320 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5321 5322 struct __reg_PART_NUM { 5323 unsigned int part_num : 8; /* Part Number */ 5324 }; 5325 5326 #define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM) 5327 5328 /* symbolic names */ 5329 5330 #define P_RFR2 148 5331 5332 #endif /* __ASSEMBLER__ */ 5333 5334 /* PART_NUM */ 5335 5336 #define PART_NUM0 0 5337 #define PART_NUM1 1 5338 #define PART_NUM2 2 5339 #define PART_NUM3 3 5340 #define PART_NUM4 4 5341 #define PART_NUM5 5 5342 #define PART_NUM6 6 5343 #define PART_NUM7 7 5344 5345 /* Device Identification Register (Version Number) */ 5346 #define VERSION_NUM _SFR_MEM8(0x15D) 5347 5348 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5349 5350 struct __reg_VERSION_NUM { 5351 unsigned int version_num : 8; /* Version Number */ 5352 }; 5353 5354 #define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM) 5355 5356 /* symbolic names */ 5357 5358 #define REV_A 12 5359 #define REV_B 1 5360 #define REV_C 3 5361 #define REV_D 4 5362 5363 #endif /* __ASSEMBLER__ */ 5364 5365 /* VERSION_NUM */ 5366 5367 #define VERSION_NUM0 0 5368 #define VERSION_NUM1 1 5369 #define VERSION_NUM2 2 5370 #define VERSION_NUM3 3 5371 #define VERSION_NUM4 4 5372 #define VERSION_NUM5 5 5373 #define VERSION_NUM6 6 5374 #define VERSION_NUM7 7 5375 5376 /* Device Identification Register (Manufacture ID Low Byte) */ 5377 #define MAN_ID_0 _SFR_MEM8(0x15E) 5378 5379 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5380 5381 struct __reg_MAN_ID_0 { 5382 unsigned int man_id_00 : 1; /* Manufacturer ID (Low Byte) */ 5383 unsigned int man_id_01 : 1; /* Manufacturer ID (Low Byte) */ 5384 unsigned int man_id_02 : 1; /* Manufacturer ID (Low Byte) */ 5385 unsigned int man_id_03 : 1; /* Manufacturer ID (Low Byte) */ 5386 unsigned int man_id_04 : 1; /* Manufacturer ID (Low Byte) */ 5387 unsigned int man_id_05 : 1; /* Manufacturer ID (Low Byte) */ 5388 unsigned int man_id_06 : 1; /* Manufacturer ID (Low Byte) */ 5389 unsigned int man_id_07 : 1; /* Manufacturer ID (Low Byte) */ 5390 }; 5391 5392 #define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0) 5393 5394 /* symbolic names */ 5395 5396 #define ATMEL_BYTE_0 31 5397 5398 #endif /* __ASSEMBLER__ */ 5399 5400 /* MAN_ID_0 */ 5401 5402 #define MAN_ID_00 0 5403 #define MAN_ID_01 1 5404 #define MAN_ID_02 2 5405 #define MAN_ID_03 3 5406 #define MAN_ID_04 4 5407 #define MAN_ID_05 5 5408 #define MAN_ID_06 6 5409 #define MAN_ID_07 7 5410 5411 /* Device Identification Register (Manufacture ID High Byte) */ 5412 #define MAN_ID_1 _SFR_MEM8(0x15F) 5413 5414 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5415 5416 struct __reg_MAN_ID_1 { 5417 unsigned int man_id_ : 8; /* Manufacturer ID (High Byte) */ 5418 }; 5419 5420 #define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1) 5421 5422 /* symbolic names */ 5423 5424 #define ATMEL_BYTE_1 0 5425 5426 #endif /* __ASSEMBLER__ */ 5427 5428 /* MAN_ID_1 */ 5429 5430 #define MAN_ID_10 0 5431 #define MAN_ID_11 1 5432 #define MAN_ID_12 2 5433 #define MAN_ID_13 3 5434 #define MAN_ID_14 4 5435 #define MAN_ID_15 5 5436 #define MAN_ID_16 6 5437 #define MAN_ID_17 7 5438 5439 /* Transceiver MAC Short Address Register (Low Byte) */ 5440 #define SHORT_ADDR_0 _SFR_MEM8(0x160) 5441 5442 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5443 5444 struct __reg_SHORT_ADDR_0 { 5445 unsigned int short_addr_00 : 1; /* MAC Short Address */ 5446 unsigned int short_addr_01 : 1; /* MAC Short Address */ 5447 unsigned int short_addr_02 : 1; /* MAC Short Address */ 5448 unsigned int short_addr_03 : 1; /* MAC Short Address */ 5449 unsigned int short_addr_04 : 1; /* MAC Short Address */ 5450 unsigned int short_addr_05 : 1; /* MAC Short Address */ 5451 unsigned int short_addr_06 : 1; /* MAC Short Address */ 5452 unsigned int short_addr_07 : 1; /* MAC Short Address */ 5453 }; 5454 5455 #define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0) 5456 5457 #endif /* __ASSEMBLER__ */ 5458 5459 /* SHORT_ADDR_0 */ 5460 5461 #define SHORT_ADDR_00 0 5462 #define SHORT_ADDR_01 1 5463 #define SHORT_ADDR_02 2 5464 #define SHORT_ADDR_03 3 5465 #define SHORT_ADDR_04 4 5466 #define SHORT_ADDR_05 5 5467 #define SHORT_ADDR_06 6 5468 #define SHORT_ADDR_07 7 5469 5470 /* Transceiver MAC Short Address Register (High Byte) */ 5471 #define SHORT_ADDR_1 _SFR_MEM8(0x161) 5472 5473 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5474 5475 struct __reg_SHORT_ADDR_1 { 5476 unsigned int short_addr_ : 8; /* MAC Short Address */ 5477 }; 5478 5479 #define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1) 5480 5481 #endif /* __ASSEMBLER__ */ 5482 5483 /* SHORT_ADDR_1 */ 5484 5485 #define SHORT_ADDR_10 0 5486 #define SHORT_ADDR_11 1 5487 #define SHORT_ADDR_12 2 5488 #define SHORT_ADDR_13 3 5489 #define SHORT_ADDR_14 4 5490 #define SHORT_ADDR_15 5 5491 #define SHORT_ADDR_16 6 5492 #define SHORT_ADDR_17 7 5493 5494 /* Transceiver Personal Area Network ID Register (Low Byte) */ 5495 #define PAN_ID_0 _SFR_MEM8(0x162) 5496 5497 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5498 5499 struct __reg_PAN_ID_0 { 5500 unsigned int pan_id_00 : 1; /* MAC Personal Area Network ID */ 5501 unsigned int pan_id_01 : 1; /* MAC Personal Area Network ID */ 5502 unsigned int pan_id_02 : 1; /* MAC Personal Area Network ID */ 5503 unsigned int pan_id_03 : 1; /* MAC Personal Area Network ID */ 5504 unsigned int pan_id_04 : 1; /* MAC Personal Area Network ID */ 5505 unsigned int pan_id_05 : 1; /* MAC Personal Area Network ID */ 5506 unsigned int pan_id_06 : 1; /* MAC Personal Area Network ID */ 5507 unsigned int pan_id_07 : 1; /* MAC Personal Area Network ID */ 5508 }; 5509 5510 #define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0) 5511 5512 #endif /* __ASSEMBLER__ */ 5513 5514 /* PAN_ID_0 */ 5515 5516 #define PAN_ID_00 0 5517 #define PAN_ID_01 1 5518 #define PAN_ID_02 2 5519 #define PAN_ID_03 3 5520 #define PAN_ID_04 4 5521 #define PAN_ID_05 5 5522 #define PAN_ID_06 6 5523 #define PAN_ID_07 7 5524 5525 /* Transceiver Personal Area Network ID Register (High Byte) */ 5526 #define PAN_ID_1 _SFR_MEM8(0x163) 5527 5528 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5529 5530 struct __reg_PAN_ID_1 { 5531 unsigned int pan_id_ : 8; /* MAC Personal Area Network ID */ 5532 }; 5533 5534 #define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1) 5535 5536 #endif /* __ASSEMBLER__ */ 5537 5538 /* PAN_ID_1 */ 5539 5540 #define PAN_ID_10 0 5541 #define PAN_ID_11 1 5542 #define PAN_ID_12 2 5543 #define PAN_ID_13 3 5544 #define PAN_ID_14 4 5545 #define PAN_ID_15 5 5546 #define PAN_ID_16 6 5547 #define PAN_ID_17 7 5548 5549 /* Transceiver MAC IEEE Address Register 0 */ 5550 #define IEEE_ADDR_0 _SFR_MEM8(0x164) 5551 5552 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5553 5554 struct __reg_IEEE_ADDR_0 { 5555 unsigned int ieee_addr_00 : 1; /* MAC IEEE Address */ 5556 unsigned int ieee_addr_01 : 1; /* MAC IEEE Address */ 5557 unsigned int ieee_addr_02 : 1; /* MAC IEEE Address */ 5558 unsigned int ieee_addr_03 : 1; /* MAC IEEE Address */ 5559 unsigned int ieee_addr_04 : 1; /* MAC IEEE Address */ 5560 unsigned int ieee_addr_05 : 1; /* MAC IEEE Address */ 5561 unsigned int ieee_addr_06 : 1; /* MAC IEEE Address */ 5562 unsigned int ieee_addr_07 : 1; /* MAC IEEE Address */ 5563 }; 5564 5565 #define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0) 5566 5567 #endif /* __ASSEMBLER__ */ 5568 5569 /* IEEE_ADDR_0 */ 5570 5571 #define IEEE_ADDR_00 0 5572 #define IEEE_ADDR_01 1 5573 #define IEEE_ADDR_02 2 5574 #define IEEE_ADDR_03 3 5575 #define IEEE_ADDR_04 4 5576 #define IEEE_ADDR_05 5 5577 #define IEEE_ADDR_06 6 5578 #define IEEE_ADDR_07 7 5579 5580 /* Transceiver MAC IEEE Address Register 1 */ 5581 #define IEEE_ADDR_1 _SFR_MEM8(0x165) 5582 5583 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5584 5585 struct __reg_IEEE_ADDR_1 { 5586 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5587 }; 5588 5589 #define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1) 5590 5591 #endif /* __ASSEMBLER__ */ 5592 5593 /* IEEE_ADDR_1 */ 5594 5595 #define IEEE_ADDR_10 0 5596 #define IEEE_ADDR_11 1 5597 #define IEEE_ADDR_12 2 5598 #define IEEE_ADDR_13 3 5599 #define IEEE_ADDR_14 4 5600 #define IEEE_ADDR_15 5 5601 #define IEEE_ADDR_16 6 5602 #define IEEE_ADDR_17 7 5603 5604 /* Transceiver MAC IEEE Address Register 2 */ 5605 #define IEEE_ADDR_2 _SFR_MEM8(0x166) 5606 5607 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5608 5609 struct __reg_IEEE_ADDR_2 { 5610 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5611 }; 5612 5613 #define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2) 5614 5615 #endif /* __ASSEMBLER__ */ 5616 5617 /* IEEE_ADDR_2 */ 5618 5619 #define IEEE_ADDR_20 0 5620 #define IEEE_ADDR_21 1 5621 #define IEEE_ADDR_22 2 5622 #define IEEE_ADDR_23 3 5623 #define IEEE_ADDR_24 4 5624 #define IEEE_ADDR_25 5 5625 #define IEEE_ADDR_26 6 5626 #define IEEE_ADDR_27 7 5627 5628 /* Transceiver MAC IEEE Address Register 3 */ 5629 #define IEEE_ADDR_3 _SFR_MEM8(0x167) 5630 5631 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5632 5633 struct __reg_IEEE_ADDR_3 { 5634 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5635 }; 5636 5637 #define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3) 5638 5639 #endif /* __ASSEMBLER__ */ 5640 5641 /* IEEE_ADDR_3 */ 5642 5643 #define IEEE_ADDR_30 0 5644 #define IEEE_ADDR_31 1 5645 #define IEEE_ADDR_32 2 5646 #define IEEE_ADDR_33 3 5647 #define IEEE_ADDR_34 4 5648 #define IEEE_ADDR_35 5 5649 #define IEEE_ADDR_36 6 5650 #define IEEE_ADDR_37 7 5651 5652 /* Transceiver MAC IEEE Address Register 4 */ 5653 #define IEEE_ADDR_4 _SFR_MEM8(0x168) 5654 5655 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5656 5657 struct __reg_IEEE_ADDR_4 { 5658 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5659 }; 5660 5661 #define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4) 5662 5663 #endif /* __ASSEMBLER__ */ 5664 5665 /* IEEE_ADDR_4 */ 5666 5667 #define IEEE_ADDR_40 0 5668 #define IEEE_ADDR_41 1 5669 #define IEEE_ADDR_42 2 5670 #define IEEE_ADDR_43 3 5671 #define IEEE_ADDR_44 4 5672 #define IEEE_ADDR_45 5 5673 #define IEEE_ADDR_46 6 5674 #define IEEE_ADDR_47 7 5675 5676 /* Transceiver MAC IEEE Address Register 5 */ 5677 #define IEEE_ADDR_5 _SFR_MEM8(0x169) 5678 5679 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5680 5681 struct __reg_IEEE_ADDR_5 { 5682 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5683 }; 5684 5685 #define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5) 5686 5687 #endif /* __ASSEMBLER__ */ 5688 5689 /* IEEE_ADDR_5 */ 5690 5691 #define IEEE_ADDR_50 0 5692 #define IEEE_ADDR_51 1 5693 #define IEEE_ADDR_52 2 5694 #define IEEE_ADDR_53 3 5695 #define IEEE_ADDR_54 4 5696 #define IEEE_ADDR_55 5 5697 #define IEEE_ADDR_56 6 5698 #define IEEE_ADDR_57 7 5699 5700 /* Transceiver MAC IEEE Address Register 6 */ 5701 #define IEEE_ADDR_6 _SFR_MEM8(0x16A) 5702 5703 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5704 5705 struct __reg_IEEE_ADDR_6 { 5706 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5707 }; 5708 5709 #define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6) 5710 5711 #endif /* __ASSEMBLER__ */ 5712 5713 /* IEEE_ADDR_6 */ 5714 5715 #define IEEE_ADDR_60 0 5716 #define IEEE_ADDR_61 1 5717 #define IEEE_ADDR_62 2 5718 #define IEEE_ADDR_63 3 5719 #define IEEE_ADDR_64 4 5720 #define IEEE_ADDR_65 5 5721 #define IEEE_ADDR_66 6 5722 #define IEEE_ADDR_67 7 5723 5724 /* Transceiver MAC IEEE Address Register 7 */ 5725 #define IEEE_ADDR_7 _SFR_MEM8(0x16B) 5726 5727 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5728 5729 struct __reg_IEEE_ADDR_7 { 5730 unsigned int ieee_addr_ : 8; /* MAC IEEE Address */ 5731 }; 5732 5733 #define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7) 5734 5735 #endif /* __ASSEMBLER__ */ 5736 5737 /* IEEE_ADDR_7 */ 5738 5739 #define IEEE_ADDR_70 0 5740 #define IEEE_ADDR_71 1 5741 #define IEEE_ADDR_72 2 5742 #define IEEE_ADDR_73 3 5743 #define IEEE_ADDR_74 4 5744 #define IEEE_ADDR_75 5 5745 #define IEEE_ADDR_76 6 5746 #define IEEE_ADDR_77 7 5747 5748 /* Transceiver Extended Operating Mode Control Register */ 5749 #define XAH_CTRL_0 _SFR_MEM8(0x16C) 5750 5751 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5752 5753 struct __reg_XAH_CTRL_0 { 5754 unsigned int slotted_operation : 1; /* Set Slotted Acknowledgment */ 5755 unsigned int max_csma_retries : 3; /* Maximum Number of CSMA-CA Procedure Repetition Attempts */ 5756 unsigned int max_frame_retries : 4; /* Maximum Number of Frame Re-transmission Attempts */ 5757 }; 5758 5759 #define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0) 5760 5761 /* symbolic names */ 5762 5763 #define SLOTTED_OP_DIS 0 5764 #define SLOTTED_OP_EN 1 5765 5766 #endif /* __ASSEMBLER__ */ 5767 5768 /* XAH_CTRL_0 */ 5769 5770 #define SLOTTED_OPERATION 0 5771 #define MAX_CSMA_RETRIES0 1 5772 #define MAX_CSMA_RETRIES1 2 5773 #define MAX_CSMA_RETRIES2 3 5774 #define MAX_FRAME_RETRIES0 4 5775 #define MAX_FRAME_RETRIES1 5 5776 #define MAX_FRAME_RETRIES2 6 5777 #define MAX_FRAME_RETRIES3 7 5778 5779 /* Transceiver CSMA-CA Random Number Generator Seed Register */ 5780 #define CSMA_SEED_0 _SFR_MEM8(0x16D) 5781 5782 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5783 5784 struct __reg_CSMA_SEED_0 { 5785 unsigned int csma_seed_00 : 1; /* Seed Value for CSMA Random Number Generator */ 5786 unsigned int csma_seed_01 : 1; /* Seed Value for CSMA Random Number Generator */ 5787 unsigned int csma_seed_02 : 1; /* Seed Value for CSMA Random Number Generator */ 5788 unsigned int csma_seed_03 : 1; /* Seed Value for CSMA Random Number Generator */ 5789 unsigned int csma_seed_04 : 1; /* Seed Value for CSMA Random Number Generator */ 5790 unsigned int csma_seed_05 : 1; /* Seed Value for CSMA Random Number Generator */ 5791 unsigned int csma_seed_06 : 1; /* Seed Value for CSMA Random Number Generator */ 5792 unsigned int csma_seed_07 : 1; /* Seed Value for CSMA Random Number Generator */ 5793 }; 5794 5795 #define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0) 5796 5797 #endif /* __ASSEMBLER__ */ 5798 5799 /* CSMA_SEED_0 */ 5800 5801 #define CSMA_SEED_00 0 5802 #define CSMA_SEED_01 1 5803 #define CSMA_SEED_02 2 5804 #define CSMA_SEED_03 3 5805 #define CSMA_SEED_04 4 5806 #define CSMA_SEED_05 5 5807 #define CSMA_SEED_06 6 5808 #define CSMA_SEED_07 7 5809 5810 /* Transceiver Acknowledgment Frame Control Register 2 */ 5811 #define CSMA_SEED_1 _SFR_MEM8(0x16E) 5812 5813 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5814 5815 struct __reg_CSMA_SEED_1 { 5816 unsigned int csma_seed_1 : 3; /* Seed Value for CSMA Random Number Generator */ 5817 unsigned int aack_i_am_coord : 1; /* Set Personal Area Network Coordinator */ 5818 unsigned int aack_dis_ack : 1; /* Disable Acknowledgment Frame Transmission */ 5819 unsigned int aack_set_pd : 1; /* Set Frame Pending Sub-field */ 5820 unsigned int aack_fvn_mode : 2; /* Acknowledgment Frame Filter Mode */ 5821 }; 5822 5823 #define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1) 5824 5825 #endif /* __ASSEMBLER__ */ 5826 5827 /* CSMA_SEED_1 */ 5828 5829 #define CSMA_SEED_10 0 5830 #define CSMA_SEED_11 1 5831 #define CSMA_SEED_12 2 5832 #define AACK_I_AM_COORD 3 5833 #define AACK_DIS_ACK 4 5834 #define AACK_SET_PD 5 5835 #define AACK_FVN_MODE0 6 5836 #define AACK_FVN_MODE1 7 5837 5838 /* Transceiver CSMA-CA Back-off Exponent Control Register */ 5839 #define CSMA_BE _SFR_MEM8(0x16F) 5840 5841 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5842 5843 struct __reg_CSMA_BE { 5844 unsigned int min_be : 4; /* Minimum Back-off Exponent */ 5845 unsigned int max_be : 4; /* Maximum Back-off Exponent */ 5846 }; 5847 5848 #define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE) 5849 5850 #endif /* __ASSEMBLER__ */ 5851 5852 /* CSMA_BE */ 5853 5854 #define MIN_BE0 0 5855 #define MIN_BE1 1 5856 #define MIN_BE2 2 5857 #define MIN_BE3 3 5858 #define MAX_BE0 4 5859 #define MAX_BE1 5 5860 #define MAX_BE2 6 5861 #define MAX_BE3 7 5862 5863 /* Transceiver Digital Test Control Register */ 5864 #define TST_CTRL_DIGI _SFR_MEM8(0x176) 5865 5866 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5867 5868 struct __reg_TST_CTRL_DIGI { 5869 unsigned int tst_ctrl_dig : 4; /* Digital Test Controller Register */ 5870 unsigned int : 4; 5871 }; 5872 5873 #define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI) 5874 5875 #endif /* __ASSEMBLER__ */ 5876 5877 /* TST_CTRL_DIGI */ 5878 5879 #define TST_CTRL_DIG0 0 5880 #define TST_CTRL_DIG1 1 5881 #define TST_CTRL_DIG2 2 5882 #define TST_CTRL_DIG3 3 5883 5884 /* Transceiver Received Frame Length Register */ 5885 #define TST_RX_LENGTH _SFR_MEM8(0x17B) 5886 5887 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5888 5889 struct __reg_TST_RX_LENGTH { 5890 unsigned int rx_length : 8; /* Received Frame Length */ 5891 }; 5892 5893 #define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH) 5894 5895 #endif /* __ASSEMBLER__ */ 5896 5897 /* TST_RX_LENGTH */ 5898 5899 #define RX_LENGTH0 0 5900 #define RX_LENGTH1 1 5901 #define RX_LENGTH2 2 5902 #define RX_LENGTH3 3 5903 #define RX_LENGTH4 4 5904 #define RX_LENGTH5 5 5905 #define RX_LENGTH6 6 5906 #define RX_LENGTH7 7 5907 5908 /* Transceiver Automatic Gain Control and Test Register */ 5909 #define TST_AGC _SFR_MEM8(0x17C) 5910 5911 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5912 5913 struct __reg_TST_AGC { 5914 unsigned int gc : 2; /* Receiver Gain Control Word */ 5915 unsigned int agc_hold : 1; /* Select AGC Hold Function */ 5916 unsigned int agc_off : 1; /* Disable AGC Regulation */ 5917 unsigned int agc_rst : 1; /* Reset AGC Gain */ 5918 unsigned int agc_hold_sel : 1; /* Enable AGC Hold Function */ 5919 unsigned int : 2; 5920 }; 5921 5922 #define TST_AGC_struct _SFR_MEM8_STRUCT(0x17c, struct __reg_TST_AGC) 5923 5924 #endif /* __ASSEMBLER__ */ 5925 5926 /* TST_AGC */ 5927 5928 #define GC0 0 5929 #define GC1 1 5930 #define AGC_HOLD 2 5931 #define AGC_OFF 3 5932 #define AGC_RST 4 5933 #define AGC_HOLD_SEL 5 5934 5935 /* Transceiver Sigma-Delta Modulator Control and Test Register */ 5936 #define TST_SDM _SFR_MEM8(0x17D) 5937 5938 #if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) 5939 5940 struct __reg_TST_SDM { 5941 unsigned int : 4; 5942 unsigned int tx_rx_sel : 1; /* Select Transmit/Receive Control Signal */ 5943 unsigned int tx_rx : 1; /* Switch between Transmit and Receive */ 5944 unsigned int mod : 1; /* Select Modulation Signal Type */ 5945 unsigned int mod_sel : 1; /* Select Modulation Data Source */ 5946 }; 5947 5948 #define TST_SDM_struct _SFR_MEM8_STRUCT(0x17d, struct __reg_TST_SDM) 5949 5950 #endif /* __ASSEMBLER__ */ 5951 5952 /* TST_SDM */ 5953 5954 #define TX_RX_SEL 4 5955 #define TX_RX 5 5956 #define MOD 6 5957 #define MOD_SEL 7 5958 5959 /* Start of frame buffer */ 5960 #define TRXFBST _SFR_MEM8(0x180) 5961 5962 /* TRXFBST */ 5963 5964 #define TRXFBST0 0 5965 #define TRXFBST1 1 5966 #define TRXFBST2 2 5967 #define TRXFBST3 3 5968 #define TRXFBST4 4 5969 #define TRXFBST5 5 5970 #define TRXFBST6 6 5971 #define TRXFBST7 7 5972 5973 /* End of frame buffer */ 5974 #define TRXFBEND _SFR_MEM8(0x1FF) 5975 5976 /* TRXFBEND */ 5977 5978 #define TRXFBEND0 0 5979 #define TRXFBEND1 1 5980 #define TRXFBEND2 2 5981 #define TRXFBEND3 3 5982 #define TRXFBEND4 4 5983 #define TRXFBEND5 5 5984 #define TRXFBEND6 6 5985 #define TRXFBEND7 7 5986 5987 5988 /* Interrupt vectors */ 5989 /* Vector 0 is the reset vector */ 5990 5991 #define _VECTORS_SIZE 308 5992 5993 /* External Interrupt Request 0 */ 5994 #define INT0_vect _VECTOR(1) 5995 #define INT0_vect_num 1 5996 5997 /* External Interrupt Request 1 */ 5998 #define INT1_vect _VECTOR(2) 5999 #define INT1_vect_num 2 6000 6001 /* External Interrupt Request 2 */ 6002 #define INT2_vect _VECTOR(3) 6003 #define INT2_vect_num 3 6004 6005 /* External Interrupt Request 3 */ 6006 #define INT3_vect _VECTOR(4) 6007 #define INT3_vect_num 4 6008 6009 /* External Interrupt Request 4 */ 6010 #define INT4_vect _VECTOR(5) 6011 #define INT4_vect_num 5 6012 6013 /* External Interrupt Request 5 */ 6014 #define INT5_vect _VECTOR(6) 6015 #define INT5_vect_num 6 6016 6017 /* External Interrupt Request 6 */ 6018 #define INT6_vect _VECTOR(7) 6019 #define INT6_vect_num 7 6020 6021 /* External Interrupt Request 7 */ 6022 #define INT7_vect _VECTOR(8) 6023 #define INT7_vect_num 8 6024 6025 /* Pin Change Interrupt Request 0 */ 6026 #define PCINT0_vect _VECTOR(9) 6027 #define PCINT0_vect_num 9 6028 6029 /* Pin Change Interrupt Request 1 */ 6030 #define PCINT1_vect _VECTOR(10) 6031 #define PCINT1_vect_num 10 6032 6033 /* Pin Change Interrupt Request 2 */ 6034 #define PCINT2_vect _VECTOR(11) 6035 #define PCINT2_vect_num 11 6036 6037 /* Watchdog Time-out Interrupt */ 6038 #define WDT_vect _VECTOR(12) 6039 #define WDT_vect_num 12 6040 6041 /* Timer/Counter2 Compare Match A */ 6042 #define TIMER2_COMPA_vect _VECTOR(13) 6043 #define TIMER2_COMPA_vect_num 13 6044 6045 /* Timer/Counter2 Compare Match B */ 6046 #define TIMER2_COMPB_vect _VECTOR(14) 6047 #define TIMER2_COMPB_vect_num 14 6048 6049 /* Timer/Counter2 Overflow */ 6050 #define TIMER2_OVF_vect _VECTOR(15) 6051 #define TIMER2_OVF_vect_num 15 6052 6053 /* Timer/Counter1 Capture Event */ 6054 #define TIMER1_CAPT_vect _VECTOR(16) 6055 #define TIMER1_CAPT_vect_num 16 6056 6057 /* Timer/Counter1 Compare Match A */ 6058 #define TIMER1_COMPA_vect _VECTOR(17) 6059 #define TIMER1_COMPA_vect_num 17 6060 6061 /* Timer/Counter1 Compare Match B */ 6062 #define TIMER1_COMPB_vect _VECTOR(18) 6063 #define TIMER1_COMPB_vect_num 18 6064 6065 /* Timer/Counter1 Compare Match C */ 6066 #define TIMER1_COMPC_vect _VECTOR(19) 6067 #define TIMER1_COMPC_vect_num 19 6068 6069 /* Timer/Counter1 Overflow */ 6070 #define TIMER1_OVF_vect _VECTOR(20) 6071 #define TIMER1_OVF_vect_num 20 6072 6073 /* Timer/Counter0 Compare Match A */ 6074 #define TIMER0_COMPA_vect _VECTOR(21) 6075 #define TIMER0_COMPA_vect_num 21 6076 6077 /* Timer/Counter0 Compare Match B */ 6078 #define TIMER0_COMPB_vect _VECTOR(22) 6079 #define TIMER0_COMPB_vect_num 22 6080 6081 /* Timer/Counter0 Overflow */ 6082 #define TIMER0_OVF_vect _VECTOR(23) 6083 #define TIMER0_OVF_vect_num 23 6084 6085 /* SPI Serial Transfer Complete */ 6086 #define SPI_STC_vect _VECTOR(24) 6087 #define SPI_STC_vect_num 24 6088 6089 /* USART0, Rx Complete */ 6090 #define USART0_RX_vect _VECTOR(25) 6091 #define USART0_RX_vect_num 25 6092 6093 /* USART0 Data register Empty */ 6094 #define USART0_UDRE_vect _VECTOR(26) 6095 #define USART0_UDRE_vect_num 26 6096 6097 /* USART0, Tx Complete */ 6098 #define USART0_TX_vect _VECTOR(27) 6099 #define USART0_TX_vect_num 27 6100 6101 /* Analog Comparator */ 6102 #define ANALOG_COMP_vect _VECTOR(28) 6103 #define ANALOG_COMP_vect_num 28 6104 6105 /* ADC Conversion Complete */ 6106 #define ADC_vect _VECTOR(29) 6107 #define ADC_vect_num 29 6108 6109 /* EEPROM Ready */ 6110 #define EE_READY_vect _VECTOR(30) 6111 #define EE_READY_vect_num 30 6112 6113 /* Timer/Counter3 Capture Event */ 6114 #define TIMER3_CAPT_vect _VECTOR(31) 6115 #define TIMER3_CAPT_vect_num 31 6116 6117 /* Timer/Counter3 Compare Match A */ 6118 #define TIMER3_COMPA_vect _VECTOR(32) 6119 #define TIMER3_COMPA_vect_num 32 6120 6121 /* Timer/Counter3 Compare Match B */ 6122 #define TIMER3_COMPB_vect _VECTOR(33) 6123 #define TIMER3_COMPB_vect_num 33 6124 6125 /* Timer/Counter3 Compare Match C */ 6126 #define TIMER3_COMPC_vect _VECTOR(34) 6127 #define TIMER3_COMPC_vect_num 34 6128 6129 /* Timer/Counter3 Overflow */ 6130 #define TIMER3_OVF_vect _VECTOR(35) 6131 #define TIMER3_OVF_vect_num 35 6132 6133 /* USART1, Rx Complete */ 6134 #define USART1_RX_vect _VECTOR(36) 6135 #define USART1_RX_vect_num 36 6136 6137 /* USART1 Data register Empty */ 6138 #define USART1_UDRE_vect _VECTOR(37) 6139 #define USART1_UDRE_vect_num 37 6140 6141 /* USART1, Tx Complete */ 6142 #define USART1_TX_vect _VECTOR(38) 6143 #define USART1_TX_vect_num 38 6144 6145 /* 2-wire Serial Interface */ 6146 #define TWI_vect _VECTOR(39) 6147 #define TWI_vect_num 39 6148 6149 /* Store Program Memory Read */ 6150 #define SPM_READY_vect _VECTOR(40) 6151 #define SPM_READY_vect_num 40 6152 6153 /* Timer/Counter4 Capture Event */ 6154 #define TIMER4_CAPT_vect _VECTOR(41) 6155 #define TIMER4_CAPT_vect_num 41 6156 6157 /* Timer/Counter4 Compare Match A */ 6158 #define TIMER4_COMPA_vect _VECTOR(42) 6159 #define TIMER4_COMPA_vect_num 42 6160 6161 /* Timer/Counter4 Compare Match B */ 6162 #define TIMER4_COMPB_vect _VECTOR(43) 6163 #define TIMER4_COMPB_vect_num 43 6164 6165 /* Timer/Counter4 Compare Match C */ 6166 #define TIMER4_COMPC_vect _VECTOR(44) 6167 #define TIMER4_COMPC_vect_num 44 6168 6169 /* Timer/Counter4 Overflow */ 6170 #define TIMER4_OVF_vect _VECTOR(45) 6171 #define TIMER4_OVF_vect_num 45 6172 6173 /* Timer/Counter5 Capture Event */ 6174 #define TIMER5_CAPT_vect _VECTOR(46) 6175 #define TIMER5_CAPT_vect_num 46 6176 6177 /* Timer/Counter5 Compare Match A */ 6178 #define TIMER5_COMPA_vect _VECTOR(47) 6179 #define TIMER5_COMPA_vect_num 47 6180 6181 /* Timer/Counter5 Compare Match B */ 6182 #define TIMER5_COMPB_vect _VECTOR(48) 6183 #define TIMER5_COMPB_vect_num 48 6184 6185 /* Timer/Counter5 Compare Match C */ 6186 #define TIMER5_COMPC_vect _VECTOR(49) 6187 #define TIMER5_COMPC_vect_num 49 6188 6189 /* Timer/Counter5 Overflow */ 6190 #define TIMER5_OVF_vect _VECTOR(50) 6191 #define TIMER5_OVF_vect_num 50 6192 6193 /* Reserved, vector numbers above has to be kept unchanged */ 6194 #define RESERVED_51_vect _VECTOR(51) 6195 #define RESERVED_51_vect_num 51 6196 6197 /* Reserved, vector numbers above has to be kept unchanged */ 6198 #define RESERVED_52_vect _VECTOR(52) 6199 #define RESERVED_52_vect_num 52 6200 6201 /* Reserved, vector numbers above has to be kept unchanged */ 6202 #define RESERVED_53_vect _VECTOR(53) 6203 #define RESERVED_53_vect_num 53 6204 6205 /* Reserved, vector numbers above has to be kept unchanged */ 6206 #define RESERVED_54_vect _VECTOR(54) 6207 #define RESERVED_54_vect_num 54 6208 6209 /* Reserved, vector numbers above has to be kept unchanged */ 6210 #define RESERVED_55_vect _VECTOR(55) 6211 #define RESERVED_55_vect_num 55 6212 6213 /* Reserved, vector numbers above has to be kept unchanged */ 6214 #define RESERVED_56_vect _VECTOR(56) 6215 #define RESERVED_56_vect_num 56 6216 6217 /* TRX24 - PLL lock interrupt */ 6218 #define TRX24_PLL_LOCK_vect _VECTOR(57) 6219 #define TRX24_PLL_LOCK_vect_num 57 6220 6221 /* TRX24 - PLL unlock interrupt */ 6222 #define TRX24_PLL_UNLOCK_vect _VECTOR(58) 6223 #define TRX24_PLL_UNLOCK_vect_num 58 6224 6225 /* TRX24 - Receive start interrupt */ 6226 #define TRX24_RX_START_vect _VECTOR(59) 6227 #define TRX24_RX_START_vect_num 59 6228 6229 /* TRX24 - RX_END interrupt */ 6230 #define TRX24_RX_END_vect _VECTOR(60) 6231 #define TRX24_RX_END_vect_num 60 6232 6233 /* TRX24 - CCA/ED done interrupt */ 6234 #define TRX24_CCA_ED_DONE_vect _VECTOR(61) 6235 #define TRX24_CCA_ED_DONE_vect_num 61 6236 6237 /* TRX24 - XAH - AMI */ 6238 #define TRX24_XAH_AMI_vect _VECTOR(62) 6239 #define TRX24_XAH_AMI_vect_num 62 6240 6241 /* TRX24 - TX_END interrupt */ 6242 #define TRX24_TX_END_vect _VECTOR(63) 6243 #define TRX24_TX_END_vect_num 63 6244 6245 /* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ 6246 #define TRX24_AWAKE_vect _VECTOR(64) 6247 #define TRX24_AWAKE_vect_num 64 6248 6249 /* Symbol counter - compare match 1 interrupt */ 6250 #define SCNT_CMP1_vect _VECTOR(65) 6251 #define SCNT_CMP1_vect_num 65 6252 6253 /* Symbol counter - compare match 2 interrupt */ 6254 #define SCNT_CMP2_vect _VECTOR(66) 6255 #define SCNT_CMP2_vect_num 66 6256 6257 /* Symbol counter - compare match 3 interrupt */ 6258 #define SCNT_CMP3_vect _VECTOR(67) 6259 #define SCNT_CMP3_vect_num 67 6260 6261 /* Symbol counter - overflow interrupt */ 6262 #define SCNT_OVFL_vect _VECTOR(68) 6263 #define SCNT_OVFL_vect_num 68 6264 6265 /* Symbol counter - backoff interrupt */ 6266 #define SCNT_BACKOFF_vect _VECTOR(69) 6267 #define SCNT_BACKOFF_vect_num 69 6268 6269 /* AES engine ready interrupt */ 6270 #define AES_READY_vect _VECTOR(70) 6271 #define AES_READY_vect_num 70 6272 6273 /* Battery monitor indicates supply voltage below threshold */ 6274 #define BAT_LOW_vect _VECTOR(71) 6275 #define BAT_LOW_vect_num 71 6276 6277 /* TRX24 TX start interrupt */ 6278 #define TRX24_TX_START_vect _VECTOR(72) 6279 #define TRX24_TX_START_vect_num 72 6280 6281 /* Address match interrupt of address filter 0 */ 6282 #define TRX24_AMI0_vect _VECTOR(73) 6283 #define TRX24_AMI0_vect_num 73 6284 6285 /* Address match interrupt of address filter 1 */ 6286 #define TRX24_AMI1_vect _VECTOR(74) 6287 #define TRX24_AMI1_vect_num 74 6288 6289 /* Address match interrupt of address filter 2 */ 6290 #define TRX24_AMI2_vect _VECTOR(75) 6291 #define TRX24_AMI2_vect_num 75 6292 6293 /* Address match interrupt of address filter 3 */ 6294 #define TRX24_AMI3_vect _VECTOR(76) 6295 #define TRX24_AMI3_vect_num 76 6296 6297 6298 /* memory parameters */ 6299 6300 #define SPM_PAGESIZE (256) 6301 #define RAMSTART (0x200) 6302 #define RAMSIZE (0x4000) 6303 #define RAMEND (0x41FF) 6304 #define XRAMSTART (0x0000) 6305 #define XRAMSIZE (0x0000) 6306 #define XRAMEND RAMEND 6307 #define E2END (0xFFF) 6308 #define E2PAGESIZE (0x08) 6309 #define FLASHEND (0x1ffff) 6310 6311 6312 /* Fuses */ 6313 6314 #define FUSE_MEMORY_SIZE 3 6315 6316 /* LFUSE Byte */ 6317 #define FUSE_CKSEL0 ~_BV(0) /* Select Clock Source */ 6318 #define FUSE_CKSEL1 ~_BV(1) /* Select Clock Source */ 6319 #define FUSE_CKSEL2 ~_BV(2) /* Select Clock Source */ 6320 #define FUSE_CKSEL3 ~_BV(3) /* Select Clock Source */ 6321 #define FUSE_SUT0 ~_BV(4) /* Select start-up time */ 6322 #define FUSE_SUT1 ~_BV(5) /* Select start-up time */ 6323 #define FUSE_CKOUT ~_BV(6) /* Clock output */ 6324 #define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */ 6325 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) 6326 6327 /* HFUSE Byte */ 6328 #define FUSE_BOOTRST ~_BV(0) /* Select Reset Vector */ 6329 #define FUSE_BOOTSZ0 ~_BV(1) /* Select Boot Size */ 6330 #define FUSE_BOOTSZ1 ~_BV(2) /* Select Boot Size */ 6331 #define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */ 6332 #define FUSE_WDTON ~_BV(4) /* Watchdog timer always on */ 6333 #define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */ 6334 #define FUSE_JTAGEN ~_BV(6) /* Enable JTAG */ 6335 #define FUSE_OCDEN ~_BV(7) /* Enable OCD */ 6336 #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) 6337 6338 /* EFUSE Byte */ 6339 #define FUSE_BODLEVEL0 ~_BV(0) /* Brown-out Detector trigger level */ 6340 #define FUSE_BODLEVEL1 ~_BV(1) /* Brown-out Detector trigger level */ 6341 #define FUSE_BODLEVEL2 ~_BV(2) /* Brown-out Detector trigger level */ 6342 #define EFUSE_DEFAULT (0xFF) 6343 6344 6345 6346 /* Lock Bits */ 6347 6348 #define __BOOT_LOCK_BITS_0_EXIST 6349 #define __BOOT_LOCK_BITS_1_EXIST 6350 #define __LOCK_BITS_EXIST 6351 6352 6353 /* Signature */ 6354 6355 #define SIGNATURE_0 0x1E 6356 #define SIGNATURE_1 0xA7 6357 #define SIGNATURE_2 0x02 6358 6359 #define SLEEP_MODE_IDLE (0x00<<1) 6360 #define SLEEP_MODE_ADC (0x01<<1) 6361 #define SLEEP_MODE_PWR_DOWN (0x02<<1) 6362 #define SLEEP_MODE_PWR_SAVE (0x03<<1) 6363 #define SLEEP_MODE_STANDBY (0x06<<1) 6364 #define SLEEP_MODE_EXT_STANDBY (0x07<<1) 6365 6366 6367 #endif /* _AVR_IOM128RFR2_H_ */ 6368