1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the SelectionDAGISel class, which is used as the common 10 // base class for SelectionDAG-based instruction selectors. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H 15 #define LLVM_CODEGEN_SELECTIONDAGISEL_H 16 17 #include "llvm/CodeGen/MachineFunctionPass.h" 18 #include "llvm/CodeGen/SelectionDAG.h" 19 #include "llvm/CodeGen/TargetSubtargetInfo.h" 20 #include "llvm/IR/BasicBlock.h" 21 #include <memory> 22 23 namespace llvm { 24 class AAResults; 25 class SelectionDAGBuilder; 26 class SDValue; 27 class MachineRegisterInfo; 28 class MachineFunction; 29 class OptimizationRemarkEmitter; 30 class TargetLowering; 31 class TargetLibraryInfo; 32 class FunctionLoweringInfo; 33 class SwiftErrorValueTracking; 34 class GCFunctionInfo; 35 class ScheduleDAGSDNodes; 36 37 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based 38 /// pattern-matching instruction selectors. 39 class SelectionDAGISel : public MachineFunctionPass { 40 public: 41 TargetMachine &TM; 42 const TargetLibraryInfo *LibInfo; 43 std::unique_ptr<FunctionLoweringInfo> FuncInfo; 44 SwiftErrorValueTracking *SwiftError; 45 MachineFunction *MF; 46 MachineRegisterInfo *RegInfo; 47 SelectionDAG *CurDAG; 48 std::unique_ptr<SelectionDAGBuilder> SDB; 49 AAResults *AA; 50 GCFunctionInfo *GFI; 51 CodeGenOpt::Level OptLevel; 52 const TargetInstrInfo *TII; 53 const TargetLowering *TLI; 54 bool FastISelFailed; 55 SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs; 56 57 /// Current optimization remark emitter. 58 /// Used to report things like combines and FastISel failures. 59 std::unique_ptr<OptimizationRemarkEmitter> ORE; 60 61 static char ID; 62 63 explicit SelectionDAGISel(TargetMachine &tm, 64 CodeGenOpt::Level OL = CodeGenOpt::Default); 65 ~SelectionDAGISel() override; 66 getTargetLowering()67 const TargetLowering *getTargetLowering() const { return TLI; } 68 69 void getAnalysisUsage(AnalysisUsage &AU) const override; 70 71 bool runOnMachineFunction(MachineFunction &MF) override; 72 emitFunctionEntryCode()73 virtual void emitFunctionEntryCode() {} 74 75 /// PreprocessISelDAG - This hook allows targets to hack on the graph before 76 /// instruction selection starts. PreprocessISelDAG()77 virtual void PreprocessISelDAG() {} 78 79 /// PostprocessISelDAG() - This hook allows the target to hack on the graph 80 /// right after selection. PostprocessISelDAG()81 virtual void PostprocessISelDAG() {} 82 83 /// Main hook for targets to transform nodes into machine nodes. 84 virtual void Select(SDNode *N) = 0; 85 86 /// SelectInlineAsmMemoryOperand - Select the specified address as a target 87 /// addressing mode, according to the specified constraint. If this does 88 /// not match or is not implemented, return true. The resultant operands 89 /// (which will appear in the machine instruction) should be added to the 90 /// OutOps vector. SelectInlineAsmMemoryOperand(const SDValue & Op,unsigned ConstraintID,std::vector<SDValue> & OutOps)91 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 92 unsigned ConstraintID, 93 std::vector<SDValue> &OutOps) { 94 return true; 95 } 96 97 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 98 /// operand node N of U during instruction selection that starts at Root. 99 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 100 101 /// IsLegalToFold - Returns true if the specific operand node N of 102 /// U can be folded during instruction selection that starts at Root. 103 /// FIXME: This is a static member function because the MSP430/X86 104 /// targets, which uses it during isel. This could become a proper member. 105 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 106 CodeGenOpt::Level OptLevel, 107 bool IgnoreChains = false); 108 109 static void InvalidateNodeId(SDNode *N); 110 static int getUninvalidatedNodeId(SDNode *N); 111 112 static void EnforceNodeIdInvariant(SDNode *N); 113 114 // Opcodes used by the DAG state machine: 115 enum BuiltinOpcodes { 116 OPC_Scope, 117 OPC_RecordNode, 118 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3, 119 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7, 120 OPC_RecordMemRef, 121 OPC_CaptureGlueInput, 122 OPC_MoveChild, 123 OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2, OPC_MoveChild3, 124 OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6, OPC_MoveChild7, 125 OPC_MoveParent, 126 OPC_CheckSame, 127 OPC_CheckChild0Same, OPC_CheckChild1Same, 128 OPC_CheckChild2Same, OPC_CheckChild3Same, 129 OPC_CheckPatternPredicate, 130 OPC_CheckPredicate, 131 OPC_CheckPredicateWithOperands, 132 OPC_CheckOpcode, 133 OPC_SwitchOpcode, 134 OPC_CheckType, 135 OPC_CheckTypeRes, 136 OPC_SwitchType, 137 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type, 138 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type, 139 OPC_CheckChild6Type, OPC_CheckChild7Type, 140 OPC_CheckInteger, 141 OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer, 142 OPC_CheckChild3Integer, OPC_CheckChild4Integer, 143 OPC_CheckCondCode, OPC_CheckChild2CondCode, 144 OPC_CheckValueType, 145 OPC_CheckComplexPat, 146 OPC_CheckAndImm, OPC_CheckOrImm, 147 OPC_CheckImmAllOnesV, 148 OPC_CheckImmAllZerosV, 149 OPC_CheckFoldableChainNode, 150 151 OPC_EmitInteger, 152 OPC_EmitStringInteger, 153 OPC_EmitRegister, 154 OPC_EmitRegister2, 155 OPC_EmitConvertToTarget, 156 OPC_EmitMergeInputChains, 157 OPC_EmitMergeInputChains1_0, 158 OPC_EmitMergeInputChains1_1, 159 OPC_EmitMergeInputChains1_2, 160 OPC_EmitCopyToReg, 161 OPC_EmitCopyToReg2, 162 OPC_EmitNodeXForm, 163 OPC_EmitNode, 164 // Space-optimized forms that implicitly encode number of result VTs. 165 OPC_EmitNode0, OPC_EmitNode1, OPC_EmitNode2, 166 OPC_MorphNodeTo, 167 // Space-optimized forms that implicitly encode number of result VTs. 168 OPC_MorphNodeTo0, OPC_MorphNodeTo1, OPC_MorphNodeTo2, 169 OPC_CompleteMatch, 170 // Contains offset in table for pattern being selected 171 OPC_Coverage 172 }; 173 174 enum { 175 OPFL_None = 0, // Node has no chain or glue input and isn't variadic. 176 OPFL_Chain = 1, // Node has a chain input. 177 OPFL_GlueInput = 2, // Node has a glue input. 178 OPFL_GlueOutput = 4, // Node has a glue output. 179 OPFL_MemRefs = 8, // Node gets accumulated MemRefs. 180 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs. 181 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs. 182 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs. 183 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs. 184 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs. 185 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs. 186 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs. 187 188 OPFL_VariadicInfo = OPFL_Variadic6 189 }; 190 191 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the 192 /// number of fixed arity values that should be skipped when copying from the 193 /// root. getNumFixedFromVariadicInfo(unsigned Flags)194 static inline int getNumFixedFromVariadicInfo(unsigned Flags) { 195 return ((Flags&OPFL_VariadicInfo) >> 4)-1; 196 } 197 198 199 protected: 200 /// DAGSize - Size of DAG being instruction selected. 201 /// 202 unsigned DAGSize; 203 204 /// ReplaceUses - replace all uses of the old node F with the use 205 /// of the new node T. ReplaceUses(SDValue F,SDValue T)206 void ReplaceUses(SDValue F, SDValue T) { 207 CurDAG->ReplaceAllUsesOfValueWith(F, T); 208 EnforceNodeIdInvariant(T.getNode()); 209 } 210 211 /// ReplaceUses - replace all uses of the old nodes F with the use 212 /// of the new nodes T. ReplaceUses(const SDValue * F,const SDValue * T,unsigned Num)213 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { 214 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num); 215 for (unsigned i = 0; i < Num; ++i) 216 EnforceNodeIdInvariant(T[i].getNode()); 217 } 218 219 /// ReplaceUses - replace all uses of the old node F with the use 220 /// of the new node T. ReplaceUses(SDNode * F,SDNode * T)221 void ReplaceUses(SDNode *F, SDNode *T) { 222 CurDAG->ReplaceAllUsesWith(F, T); 223 EnforceNodeIdInvariant(T); 224 } 225 226 /// Replace all uses of \c F with \c T, then remove \c F from the DAG. ReplaceNode(SDNode * F,SDNode * T)227 void ReplaceNode(SDNode *F, SDNode *T) { 228 CurDAG->ReplaceAllUsesWith(F, T); 229 EnforceNodeIdInvariant(T); 230 CurDAG->RemoveDeadNode(F); 231 } 232 233 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 234 /// by tblgen. Others should not call it. 235 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, 236 const SDLoc &DL); 237 238 /// getPatternForIndex - Patterns selected by tablegen during ISEL getPatternForIndex(unsigned index)239 virtual StringRef getPatternForIndex(unsigned index) { 240 llvm_unreachable("Tblgen should generate the implementation of this!"); 241 } 242 243 /// getIncludePathForIndex - get the td source location of pattern instantiation getIncludePathForIndex(unsigned index)244 virtual StringRef getIncludePathForIndex(unsigned index) { 245 llvm_unreachable("Tblgen should generate the implementation of this!"); 246 } 247 shouldOptForSize(const MachineFunction * MF)248 bool shouldOptForSize(const MachineFunction *MF) const { 249 return CurDAG->shouldOptForSize(); 250 } 251 252 public: 253 // Calls to these predicates are generated by tblgen. 254 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 255 int64_t DesiredMaskS) const; 256 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 257 int64_t DesiredMaskS) const; 258 259 260 /// CheckPatternPredicate - This function is generated by tblgen in the 261 /// target. It runs the specified pattern predicate and returns true if it 262 /// succeeds or false if it fails. The number is a private implementation 263 /// detail to the code tblgen produces. CheckPatternPredicate(unsigned PredNo)264 virtual bool CheckPatternPredicate(unsigned PredNo) const { 265 llvm_unreachable("Tblgen should generate the implementation of this!"); 266 } 267 268 /// CheckNodePredicate - This function is generated by tblgen in the target. 269 /// It runs node predicate number PredNo and returns true if it succeeds or 270 /// false if it fails. The number is a private implementation 271 /// detail to the code tblgen produces. CheckNodePredicate(SDNode * N,unsigned PredNo)272 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const { 273 llvm_unreachable("Tblgen should generate the implementation of this!"); 274 } 275 276 /// CheckNodePredicateWithOperands - This function is generated by tblgen in 277 /// the target. 278 /// It runs node predicate number PredNo and returns true if it succeeds or 279 /// false if it fails. The number is a private implementation detail to the 280 /// code tblgen produces. CheckNodePredicateWithOperands(SDNode * N,unsigned PredNo,const SmallVectorImpl<SDValue> & Operands)281 virtual bool CheckNodePredicateWithOperands( 282 SDNode *N, unsigned PredNo, 283 const SmallVectorImpl<SDValue> &Operands) const { 284 llvm_unreachable("Tblgen should generate the implementation of this!"); 285 } 286 CheckComplexPattern(SDNode * Root,SDNode * Parent,SDValue N,unsigned PatternNo,SmallVectorImpl<std::pair<SDValue,SDNode * >> & Result)287 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, 288 unsigned PatternNo, 289 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { 290 llvm_unreachable("Tblgen should generate the implementation of this!"); 291 } 292 RunSDNodeXForm(SDValue V,unsigned XFormNo)293 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) { 294 llvm_unreachable("Tblgen should generate this!"); 295 } 296 297 void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 298 unsigned TableSize); 299 300 /// Return true if complex patterns for this target can mutate the 301 /// DAG. ComplexPatternFuncMutatesDAG()302 virtual bool ComplexPatternFuncMutatesDAG() const { 303 return false; 304 } 305 306 /// Return whether the node may raise an FP exception. 307 bool mayRaiseFPException(SDNode *Node) const; 308 309 bool isOrEquivalentToAdd(const SDNode *N) const; 310 311 private: 312 313 // Calls to these functions are generated by tblgen. 314 void Select_INLINEASM(SDNode *N); 315 void Select_READ_REGISTER(SDNode *Op); 316 void Select_WRITE_REGISTER(SDNode *Op); 317 void Select_UNDEF(SDNode *N); 318 void CannotYetSelect(SDNode *N); 319 320 void Select_FREEZE(SDNode *N); 321 322 private: 323 void DoInstructionSelection(); 324 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 325 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo); 326 327 /// Prepares the landing pad to take incoming values or do other EH 328 /// personality specific tasks. Returns true if the block should be 329 /// instruction selected, false if no code should be emitted for it. 330 bool PrepareEHLandingPad(); 331 332 /// Perform instruction selection on all basic blocks in the function. 333 void SelectAllBasicBlocks(const Function &Fn); 334 335 /// Perform instruction selection on a single basic block, for 336 /// instructions between \p Begin and \p End. \p HadTailCall will be set 337 /// to true if a call in the block was translated as a tail call. 338 void SelectBasicBlock(BasicBlock::const_iterator Begin, 339 BasicBlock::const_iterator End, 340 bool &HadTailCall); 341 void FinishBasicBlock(); 342 343 void CodeGenAndEmitDAG(); 344 345 /// Generate instructions for lowering the incoming arguments of the 346 /// given function. 347 void LowerArguments(const Function &F); 348 349 void ComputeLiveOutVRegInfo(); 350 351 /// Create the scheduler. If a specific scheduler was specified 352 /// via the SchedulerRegistry, use it, otherwise select the 353 /// one preferred by the target. 354 /// 355 ScheduleDAGSDNodes *CreateScheduler(); 356 357 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel 358 /// state machines that start with a OPC_SwitchOpcode node. 359 std::vector<unsigned> OpcodeOffset; 360 361 void UpdateChains(SDNode *NodeToMatch, SDValue InputChain, 362 SmallVectorImpl<SDNode *> &ChainNodesMatched, 363 bool isMorphNodeTo); 364 }; 365 366 } 367 368 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */ 369