1 /***************************************************************************** 2 3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or 4 more contributor license agreements. See the NOTICE file distributed 5 with this work for additional information regarding copyright ownership. 6 Accellera licenses this file to you under the Apache License, Version 2.0 7 (the "License"); you may not use this file except in compliance with the 8 License. You may obtain a copy of the License at 9 10 http://www.apache.org/licenses/LICENSE-2.0 11 12 Unless required by applicable law or agreed to in writing, software 13 distributed under the License is distributed on an "AS IS" BASIS, 14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 15 implied. See the License for the specific language governing 16 permissions and limitations under the License. 17 18 *****************************************************************************/ 19 20 //============================================================================== 21 /// @file lt_top.h 22 // 23 /// @brief Top level interconnect and instantiation for lt example 24 // 25 //============================================================================== 26 // 27 // Original Authors: 28 // Jack Donovan, ESLX 29 // Charles Wilson, ESLX 30 // Anna Keist, ESLX 31 // 32 //============================================================================== 33 34 #ifndef __LT_TOP_H__ 35 #define __LT_TOP_H__ 36 37 #include "tlm.h" // TLM header 38 #include "lt_target.h" // lt memory target 39 #include "at_target_1_phase.h" // at and lt memory target 40 #include "initiator_top.h" // processor abstraction initiator 41 #include "models/SimpleBusLT.h" // Bus/Router Implementation 42 43 /// Top wrapper Module 44 class lt_top // Declare SC_MODULE 45 : public sc_core::sc_module 46 { 47 public: 48 49 /// Constructor 50 lt_top ( sc_core::sc_module_name name); 51 52 //Member Variables =========================================================== 53 private: 54 SimpleBusLT<2, 2> m_bus; ///< simple bus 55 at_target_1_phase m_at_and_lt_target_1; ///< combined blocking/non-blocking 56 lt_target m_lt_target_2; ///< blocking with convenienece socket 57 initiator_top m_initiator_1; ///< instance 1 initiator 58 initiator_top m_initiator_2; ///< instance 2 initiator 59 }; 60 #endif /* __LT_TOP_H__ */ 61