1 //////////////////////////////////////////////////
2 // //
3 // Emu64 //
4 // von Thorsten Kattanek //
5 // //
6 // #file: mmu_class.cpp //
7 // //
8 // Dieser Sourcecode ist Copyright geschützt! //
9 // Geistiges Eigentum von Th.Kattanek //
10 // //
11 // Letzte Änderung am 13.09.2019 //
12 // www.emu64.de //
13 // //
14 //////////////////////////////////////////////////
15
16 #include "mmu_class.h"
17 #include <fstream>
18 using namespace std;
19
MMU(void)20 MMU::MMU(void)
21 {
22 for(int i=0;i<0x10000;i++) RAM[i]=0;
23
24 VicIOWriteProc = std::bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
25 SidIOWriteProc = std::bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
26 Cia1IOWriteProc = std::bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
27 Cia2IOWriteProc = std::bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
28 VicIOReadProc = std::bind(&MMU::ReadRam,this,std::placeholders::_1);
29 SidIOReadProc = std::bind(&MMU::ReadRam,this,std::placeholders::_1);
30 Cia1IOReadProc = std::bind(&MMU::ReadRam,this,std::placeholders::_1);
31 Cia2IOReadProc = std::bind(&MMU::ReadRam,this,std::placeholders::_1);
32
33 InitProcTables();
34 }
35
~MMU(void)36 MMU::~MMU(void)
37 {
38 }
39
Reset()40 void MMU::Reset()
41 {
42 CPU_PORT->Reset();
43 ChangeMemMap();
44 for(int i=0;i<0x10000;i++)
45 {
46 if(i & 0x40) RAM[i] = 0xFF;
47 else RAM[i] = 0x00;
48 }
49 }
50
GetFarbramPointer(void)51 unsigned char* MMU::GetFarbramPointer(void)
52 {
53 return FARB_RAM;
54 }
55
LoadKernalRom(const char * filename)56 bool MMU::LoadKernalRom(const char* filename)
57 {
58 FILE *file;
59 file = fopen(filename, "rb");
60 if (file == NULL)
61 {
62 return false;
63 }
64
65 if(0x2000 != fread (KERNAL_ROM,1,0x2000,file))
66 {
67 return false;
68 }
69
70 fclose(file);
71
72 return true;
73 }
74
LoadBasicRom(const char * filename)75 bool MMU::LoadBasicRom(const char* filename)
76 {
77 FILE *file;
78 file = fopen(filename, "rb");
79 if (file == NULL)
80 {
81 return false;
82 }
83
84 if(0x2000 != fread (BASIC_ROM,1,0x2000,file))
85 {
86 return false;
87 }
88
89 fclose(file);
90
91 return true;
92 }
93
LoadCharRom(const char * filename)94 bool MMU::LoadCharRom(const char* filename)
95 {
96 FILE *file;
97 file = fopen (filename, "rb");
98 if (file == NULL)
99 {
100 return false;
101 }
102
103 if(0x1000 != fread (CHAR_ROM,1,0x1000,file))
104 {
105 return false;
106 }
107
108 fclose(file);
109
110 return true;
111 }
112
113 /*
114 bool MMU::SaveFreez(FILE* File)
115 {
116 fwrite(RAM,1,0x10000,File);
117 fwrite(FARB_RAM,1,0x0400,File);
118 return true;
119 }
120
121 bool MMU::LoadFreez(FILE* File,unsigned short Version)
122 {
123 switch(Version)
124 {
125 case 0x0100:
126 case 0x0101:
127 ChangeMemMap();
128 fread(RAM,1,0x10000,File);
129 fread(FARB_RAM,1,0x0400,File);
130 break;
131 }
132 return true;
133 }
134 */
135
GetRAMPointer(void)136 unsigned char* MMU::GetRAMPointer(void)
137 {
138 return RAM;
139 }
140
GetReadSource(unsigned char page)141 unsigned char MMU::GetReadSource(unsigned char page)
142 {
143 return MapReadSource[page];
144 }
145
GetWriteDestination(unsigned char page)146 unsigned char MMU::GetWriteDestination(unsigned char page)
147 {
148 return MapWriteDestination[page];
149 }
150
151 ///////////////////// Intern ////////////////////////
152
ChangeMemMap()153 void MMU::ChangeMemMap()
154 {
155 CPU_PORT->ConfigChanged(CPU_PORT->TAPE_SENSE, 1, 0x17);
156 unsigned char AE = ((~CPU_PORT->DIR | CPU_PORT->DATA) & 0x7);
157
158 MEMORY_MAP = 0;
159 if (*EXROM) MEMORY_MAP|=2;
160 if (*GAME) MEMORY_MAP|=1;
161 if ((AE&4)==4) MEMORY_MAP|=4;
162 if ((AE&2)==2) MEMORY_MAP|=8;
163 if ((AE&1)==1) MEMORY_MAP|=16;
164
165 if(MEMORY_MAP == MEMORY_MAP_OLD) return;
166
167 switch(MEMORY_MAP_OLD)
168 {
169 case 2: case 18: case 10: case 6: case 26: case 22: case 14: case 30:
170 for(int i=0;i<112;i++)
171 {
172 CPUReadProcTbl[0x10+i] = std::bind(&MMU::ReadRam,this,std::placeholders::_1);
173 CPUWriteProcTbl[0x10+i] = std::bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
174 MapReadSource[0x10+i] = MV_RAM;
175 MapWriteDestination[0x10+i] = MV_RAM;
176
177 }
178 for(int i=0;i<16;i++)
179 {
180 CPUReadProcTbl[0xC0+i] = std::bind(&MMU::ReadRam,this,std::placeholders::_1);
181 CPUWriteProcTbl[0xC0+i] = std::bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
182 MapReadSource[0xC0+i] = MV_RAM;
183 MapWriteDestination[0xC0+i] = MV_RAM;
184 }
185 break;
186 }
187
188 switch (MEMORY_MAP)
189 {
190 case 31:
191 {
192 /// READ
193 for(int i=0;i<32;++i)
194 {
195 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
196 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadBasicRom,this,std::placeholders::_1);
197 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadKernalRom,this,std::placeholders::_1);
198 MapReadSource[0x80+i] = MV_RAM;
199 MapReadSource[0xA0+i] = MV_BASIC_ROM;
200 MapReadSource[0xE0+i] = MV_KERNAL_ROM;
201 }
202 for(int i=0;i<4;++i)
203 {
204 CPUReadProcTbl[0xD0+i] = VicIOReadProc;
205 CPUReadProcTbl[0xD4+i] = SidIOReadProc;
206 CPUReadProcTbl[0xD8+i] = bind(&MMU::ReadFarbRam,this,std::placeholders::_1);
207 MapReadSource[0xD0+i] = MV_VIC;
208 MapReadSource[0xD4+i] = MV_SID;
209 MapReadSource[0xD8+i] = MV_FARB_RAM;
210 }
211 CPUReadProcTbl[0xDC] = Cia1IOReadProc;
212 CPUReadProcTbl[0xDD] = Cia2IOReadProc;
213 CPUReadProcTbl[0xDE] = IO1ReadProc;
214 CPUReadProcTbl[0xDF] = IO2ReadProc;
215 MapReadSource[0xDC] = MV_CIA1;
216 MapReadSource[0xDD] = MV_CIA2;
217 MapReadSource[0xDE] = MV_IO1;
218 MapReadSource[0xDF] = MV_IO2;
219
220 /// WRITE
221 for(int i=0;i<32;++i)
222 {
223 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
224 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
225 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
226 MapWriteDestination[0x80+i] = MV_RAM;
227 MapWriteDestination[0xA0+i] = MV_RAM;
228 MapWriteDestination[0xE0+i] = MV_RAM;
229 }
230 for(int i=0;i<4;++i)
231 {
232 CPUWriteProcTbl[0xD0+i] = VicIOWriteProc;
233 CPUWriteProcTbl[0xD4+i] = SidIOWriteProc;
234 CPUWriteProcTbl[0xD8+i] = bind(&MMU::WriteFarbRam,this,std::placeholders::_1,std::placeholders::_2);
235 MapWriteDestination[0xD0+i] = MV_VIC;
236 MapWriteDestination[0xD4+i] = MV_SID;
237 MapWriteDestination[0xD8+i] = MV_FARB_RAM;
238 }
239 CPUWriteProcTbl[0xDC] = Cia1IOWriteProc;
240 CPUWriteProcTbl[0xDD] = Cia2IOWriteProc;
241 CPUWriteProcTbl[0xDE] = IO1WriteProc;
242 CPUWriteProcTbl[0xDF] = IO2WriteProc;
243 MapWriteDestination[0xDC] = MV_CIA1;
244 MapWriteDestination[0xDD] = MV_CIA2;
245 MapWriteDestination[0xDE] = MV_IO1;
246 MapWriteDestination[0xDF] = MV_IO2;
247 }break;
248
249 case 27:
250 {
251 /// READ
252 for(int i=0;i<32;++i)
253 {
254 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
255 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadBasicRom,this,std::placeholders::_1);
256 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadKernalRom,this,std::placeholders::_1);
257 MapReadSource[0x80+i] = MV_RAM;
258 MapReadSource[0xA0+i] = MV_BASIC_ROM;
259 MapReadSource[0xE0+i] = MV_KERNAL_ROM;
260 }
261 for(int i=0;i<16;++i)
262 {
263 CPUReadProcTbl[0xD0+i] = bind(&MMU::ReadCharRom,this,std::placeholders::_1);
264 MapReadSource[0xD0+i] = MV_CHAR_ROM;
265 }
266
267 /// WRITE
268 for(int i=0;i<32;++i)
269 {
270 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
271 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
272 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
273 MapWriteDestination[0x80+i] = MV_RAM;
274 MapWriteDestination[0xA0+i] = MV_RAM;
275 MapWriteDestination[0xE0+i] = MV_RAM;
276 }
277 for(int i=0;i<16;++i)
278 {
279 CPUWriteProcTbl[0xD0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
280 MapWriteDestination[0xD0+i] = MV_RAM;
281 }
282 }break;
283
284 case 29:
285 {
286 /// READ
287 for(int i=0;i<32;++i)
288 {
289 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadCRT1,this,std::placeholders::_1);
290 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadBasicRom,this,std::placeholders::_1);
291 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadKernalRom,this,std::placeholders::_1);
292 MapReadSource[0x80+i] = MV_CRT_1;
293 MapReadSource[0xA0+i] = MV_BASIC_ROM;
294 MapReadSource[0xE0+i] = MV_KERNAL_ROM;
295 }
296 for(int i=0;i<4;++i)
297 {
298 CPUReadProcTbl[0xD0+i] = VicIOReadProc;
299 CPUReadProcTbl[0xD4+i] = SidIOReadProc;
300 CPUReadProcTbl[0xD8+i] = bind(&MMU::ReadFarbRam,this,std::placeholders::_1);
301 MapReadSource[0xD0+i] = MV_VIC;
302 MapReadSource[0xD4+i] = MV_SID;
303 MapReadSource[0xD8+i] = MV_FARB_RAM;
304 }
305 CPUReadProcTbl[0xDC] = Cia1IOReadProc;
306 CPUReadProcTbl[0xDD] = Cia2IOReadProc;
307 CPUReadProcTbl[0xDE] = IO1ReadProc;
308 CPUReadProcTbl[0xDF] = IO2ReadProc;
309 MapReadSource[0xDC] = MV_CIA1;
310 MapReadSource[0xDD] = MV_CIA2;
311 MapReadSource[0xDE] = MV_IO1;
312 MapReadSource[0xDF] = MV_IO2;
313
314 /// WRITE
315 for(int i=0;i<32;++i)
316 {
317 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteCRT1,this,std::placeholders::_1,std::placeholders::_2);
318 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
319 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
320 MapWriteDestination[0x80+i] = MV_CRT_1;
321 MapWriteDestination[0xA0+i] = MV_RAM;
322 MapWriteDestination[0xE0+i] = MV_RAM;
323 }
324 for(int i=0;i<4;++i)
325 {
326 CPUWriteProcTbl[0xD0+i] = VicIOWriteProc;
327 CPUWriteProcTbl[0xD4+i] = SidIOWriteProc;
328 CPUWriteProcTbl[0xD8+i] = bind(&MMU::WriteFarbRam,this,std::placeholders::_1,std::placeholders::_2);
329 MapWriteDestination[0xD0+i] = MV_VIC;
330 MapWriteDestination[0xD4+i] = MV_SID;
331 MapWriteDestination[0xD8+i] = MV_FARB_RAM;
332 }
333 CPUWriteProcTbl[0xDC] = Cia1IOWriteProc;
334 CPUWriteProcTbl[0xDD] = Cia2IOWriteProc;
335 CPUWriteProcTbl[0xDE] = IO1WriteProc;
336 CPUWriteProcTbl[0xDF] = IO2WriteProc;
337 MapWriteDestination[0xDC] = MV_CIA1;
338 MapWriteDestination[0xDD] = MV_CIA2;
339 MapWriteDestination[0xDE] = MV_IO1;
340 MapWriteDestination[0xDF] = MV_IO2;
341 }break;
342
343 case 25:
344 {
345 /// READ
346 for(int i=0;i<32;++i)
347 {
348 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadCRT1,this,std::placeholders::_1);
349 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadBasicRom,this,std::placeholders::_1);
350 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadKernalRom,this,std::placeholders::_1);
351 MapReadSource[0x80+i] = MV_CRT_1;
352 MapReadSource[0xA0+i] = MV_BASIC_ROM;
353 MapReadSource[0xE0+i] = MV_KERNAL_ROM;
354 }
355 for(int i=0;i<16;++i)
356 {
357 CPUReadProcTbl[0xD0+i] = bind(&MMU::ReadCharRom,this,std::placeholders::_1);
358 MapReadSource[0xD0+i] = MV_CHAR_ROM;
359 }
360
361 /// WRITE
362 for(int i=0;i<32;++i)
363 {
364 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteCRT1,this,std::placeholders::_1,std::placeholders::_2);
365 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
366 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
367 MapWriteDestination[0x80+i] = MV_CRT_1;
368 MapWriteDestination[0xA0+i] = MV_RAM;
369 MapWriteDestination[0xE0+i] = MV_RAM;
370 }
371 for(int i=0;i<16;++i)
372 {
373 CPUWriteProcTbl[0xD0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
374 MapWriteDestination[0xD0+i] = MV_RAM;
375 }
376 }break;
377
378 case 28:
379 {
380 /// READ
381 for(int i=0;i<32;++i)
382 {
383 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadCRT1,this,std::placeholders::_1);
384 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadCRT2,this,std::placeholders::_1);
385 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadKernalRom,this,std::placeholders::_1);
386 MapReadSource[0x80+i] = MV_CRT_1;
387 MapReadSource[0xA0+i] = MV_CRT_2;
388 MapReadSource[0xE0+i] = MV_KERNAL_ROM;
389 }
390 for(int i=0;i<4;++i)
391 {
392 CPUReadProcTbl[0xD0+i] = VicIOReadProc;
393 CPUReadProcTbl[0xD4+i] = SidIOReadProc;
394 CPUReadProcTbl[0xD8+i] = bind(&MMU::ReadFarbRam,this,std::placeholders::_1);
395 MapReadSource[0xD0+i] = MV_VIC;
396 MapReadSource[0xD4+i] = MV_SID;
397 MapReadSource[0xD8+i] = MV_FARB_RAM;
398 }
399 CPUReadProcTbl[0xDC] = Cia1IOReadProc;
400 CPUReadProcTbl[0xDD] = Cia2IOReadProc;
401 CPUReadProcTbl[0xDE] = IO1ReadProc;
402 CPUReadProcTbl[0xDF] = IO2ReadProc;
403 MapReadSource[0xDC] = MV_CIA1;
404 MapReadSource[0xDD] = MV_CIA2;
405 MapReadSource[0xDE] = MV_IO1;
406 MapReadSource[0xDF] = MV_IO2;
407
408 /// WRITE
409 for(int i=0;i<32;++i)
410 {
411 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteCRT1,this,std::placeholders::_1,std::placeholders::_2);
412 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteCRT2,this,std::placeholders::_1,std::placeholders::_2);
413 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
414 MapWriteDestination[0x80+i] = MV_CRT_1;
415 MapWriteDestination[0xA0+i] = MV_CRT_2;
416 MapWriteDestination[0xE0+i] = MV_RAM;
417 }
418 for(int i=0;i<4;++i)
419 {
420 CPUWriteProcTbl[0xD0+i] = VicIOWriteProc;
421 CPUWriteProcTbl[0xD4+i] = SidIOWriteProc;
422 CPUWriteProcTbl[0xD8+i] = bind(&MMU::WriteFarbRam,this,std::placeholders::_1,std::placeholders::_2);
423 MapWriteDestination[0xD0+i] = MV_VIC;
424 MapWriteDestination[0xD4+i] = MV_SID;
425 MapWriteDestination[0xD8+i] = MV_FARB_RAM;
426 }
427 CPUWriteProcTbl[0xDC] = Cia1IOWriteProc;
428 CPUWriteProcTbl[0xDD] = Cia2IOWriteProc;
429 CPUWriteProcTbl[0xDE] = IO1WriteProc;
430 CPUWriteProcTbl[0xDF] = IO2WriteProc;
431 MapWriteDestination[0xDC] = MV_CIA1;
432 MapWriteDestination[0xDD] = MV_CIA2;
433 MapWriteDestination[0xDE] = MV_IO1;
434 MapWriteDestination[0xDF] = MV_IO2;
435 }break;
436
437 case 24:
438 {
439 /// READ
440 for(int i=0;i<32;++i)
441 {
442 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadCRT1,this,std::placeholders::_1);
443 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadCRT2,this,std::placeholders::_1);
444 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadKernalRom,this,std::placeholders::_1);
445 MapReadSource[0x80+i] = MV_CRT_1;
446 MapReadSource[0xA0+i] = MV_CRT_2;
447 MapReadSource[0xE0+i] = MV_KERNAL_ROM;
448 }
449 for(int i=0;i<16;++i)
450 {
451 CPUReadProcTbl[0xD0+i] = bind(&MMU::ReadCharRom,this,std::placeholders::_1);
452 MapReadSource[0xD0+i] = MV_CHAR_ROM;
453 }
454
455 /// WRITE
456 for(int i=0;i<32;++i)
457 {
458 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteCRT1,this,std::placeholders::_1,std::placeholders::_2);
459 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteCRT2,this,std::placeholders::_1,std::placeholders::_2);
460 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
461 MapWriteDestination[0x80+i] = MV_CRT_1;
462 MapWriteDestination[0xA0+i] = MV_CRT_2;
463 MapWriteDestination[0xE0+i] = MV_RAM;
464 }
465 for(int i=0;i<16;++i)
466 {
467 CPUWriteProcTbl[0xD0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
468 MapWriteDestination[0xD0+i] = MV_RAM;
469 }
470 }break;
471
472 case 12:
473 {
474 /// READ
475 for(int i=0;i<32;++i)
476 {
477 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
478 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadCRT2,this,std::placeholders::_1);
479 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadKernalRom,this,std::placeholders::_1);
480 MapReadSource[0x80+i] = MV_RAM;
481 MapReadSource[0xA0+i] = MV_CRT_2;
482 MapReadSource[0xE0+i] = MV_KERNAL_ROM;
483 }
484 for(int i=0;i<4;++i)
485 {
486 CPUReadProcTbl[0xD0+i] = VicIOReadProc;
487 CPUReadProcTbl[0xD4+i] = SidIOReadProc;
488 CPUReadProcTbl[0xD8+i] = bind(&MMU::ReadFarbRam,this,std::placeholders::_1);
489 MapReadSource[0xD0+i] = MV_VIC;
490 MapReadSource[0xD4+i] = MV_SID;
491 MapReadSource[0xD8+i] = MV_FARB_RAM;
492 }
493 CPUReadProcTbl[0xDC] = Cia1IOReadProc;
494 CPUReadProcTbl[0xDD] = Cia2IOReadProc;
495 CPUReadProcTbl[0xDE] = IO1ReadProc;
496 CPUReadProcTbl[0xDF] = IO2ReadProc;
497 MapReadSource[0xDC] = MV_CIA1;
498 MapReadSource[0xDD] = MV_CIA2;
499 MapReadSource[0xDE] = MV_IO1;
500 MapReadSource[0xDF] = MV_IO2;
501
502 /// WRITE
503 for(int i=0;i<32;++i)
504 {
505 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
506 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteCRT2,this,std::placeholders::_1,std::placeholders::_2);
507 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
508 MapWriteDestination[0x80+i] = MV_RAM;
509 MapWriteDestination[0xA0+i] = MV_CRT_2;
510 MapWriteDestination[0xE0+i] = MV_RAM;
511 }
512 for(int i=0;i<4;++i)
513 {
514 CPUWriteProcTbl[0xD0+i] = VicIOWriteProc;
515 CPUWriteProcTbl[0xD4+i] = SidIOWriteProc;
516 CPUWriteProcTbl[0xD8+i] = bind(&MMU::WriteFarbRam,this,std::placeholders::_1,std::placeholders::_2);
517 MapWriteDestination[0xD0+i] = MV_VIC;
518 MapWriteDestination[0xD4+i] = MV_SID;
519 MapWriteDestination[0xD8+i] = MV_FARB_RAM;
520 }
521 CPUWriteProcTbl[0xDC] = Cia1IOWriteProc;
522 CPUWriteProcTbl[0xDD] = Cia2IOWriteProc;
523 CPUWriteProcTbl[0xDE] = IO1WriteProc;
524 CPUWriteProcTbl[0xDF] = IO2WriteProc;
525 MapWriteDestination[0xDC] = MV_CIA1;
526 MapWriteDestination[0xDD] = MV_CIA2;
527 MapWriteDestination[0xDE] = MV_IO1;
528 MapWriteDestination[0xDF] = MV_IO2;
529 }break;
530
531 case 8:
532 {
533 /// READ
534 for(int i=0;i<32;++i)
535 {
536 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
537 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadCRT2,this,std::placeholders::_1);
538 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadKernalRom,this,std::placeholders::_1);
539 MapReadSource[0x80+i] = MV_RAM;
540 MapReadSource[0xA0+i] = MV_CRT_2;
541 MapReadSource[0xE0+i] = MV_KERNAL_ROM;
542 }
543 for(int i=0;i<16;++i)
544 {
545 CPUReadProcTbl[0xD0+i] = bind(&MMU::ReadCharRom,this,std::placeholders::_1);
546 MapReadSource[0xD0+i] = MV_CHAR_ROM;
547 }
548
549 /// WRITE
550
551 for(int i=0;i<32;++i)
552 {
553 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
554 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteCRT2,this,std::placeholders::_1,std::placeholders::_2);
555 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
556 MapWriteDestination[0x80+i] = MV_RAM;
557 MapWriteDestination[0xA0+i] = MV_CRT_2;
558 MapWriteDestination[0xE0+i] = MV_RAM;
559 }
560 for(int i=0;i<16;++i)
561 {
562 CPUWriteProcTbl[0xD0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
563 MapWriteDestination[0xD0+i] = MV_RAM;
564 }
565 }break;
566
567 case 13: case 15:
568 {
569 /// READ
570 for(int i=0;i<32;++i)
571 {
572 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
573 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
574 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadKernalRom,this,std::placeholders::_1);
575 MapReadSource[0x80+i] = MV_RAM;
576 MapReadSource[0xA0+i] = MV_RAM;
577 MapReadSource[0xE0+i] = MV_KERNAL_ROM;
578 }
579 for(int i=0;i<4;++i)
580 {
581 CPUReadProcTbl[0xD0+i] = VicIOReadProc;
582 CPUReadProcTbl[0xD4+i] = SidIOReadProc;
583 CPUReadProcTbl[0xD8+i] = bind(&MMU::ReadFarbRam,this,std::placeholders::_1);
584 MapReadSource[0xD0+i] = MV_VIC;
585 MapReadSource[0xD4+i] = MV_SID;
586 MapReadSource[0xD8+i] = MV_FARB_RAM;
587 }
588 CPUReadProcTbl[0xDC] = Cia1IOReadProc;
589 CPUReadProcTbl[0xDD] = Cia2IOReadProc;
590 CPUReadProcTbl[0xDE] = IO1ReadProc;
591 CPUReadProcTbl[0xDF] = IO2ReadProc;
592 MapReadSource[0xDC] = MV_CIA1;
593 MapReadSource[0xDD] = MV_CIA2;
594 MapReadSource[0xDE] = MV_IO1;
595 MapReadSource[0xDF] = MV_IO2;
596
597 /// WRITE
598 for(int i=0;i<32;++i)
599 {
600 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
601 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
602 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
603 MapWriteDestination[0x80+i] = MV_RAM;
604 MapWriteDestination[0xA0+i] = MV_RAM;
605 MapWriteDestination[0xE0+i] = MV_RAM;
606 }
607 for(int i=0;i<4;++i)
608 {
609 CPUWriteProcTbl[0xD0+i] = VicIOWriteProc;
610 CPUWriteProcTbl[0xD4+i] = SidIOWriteProc;
611 CPUWriteProcTbl[0xD8+i] = bind(&MMU::WriteFarbRam,this,std::placeholders::_1,std::placeholders::_2);
612 MapWriteDestination[0xD0+i] = MV_VIC;
613 MapWriteDestination[0xD4+i] = MV_SID;
614 MapWriteDestination[0xD8+i] = MV_FARB_RAM;
615 }
616 CPUWriteProcTbl[0xDC] = Cia1IOWriteProc;
617 CPUWriteProcTbl[0xDD] = Cia2IOWriteProc;
618 CPUWriteProcTbl[0xDE] = IO1WriteProc;
619 CPUWriteProcTbl[0xDF] = IO2WriteProc;
620 MapWriteDestination[0xDC] = MV_CIA1;
621 MapWriteDestination[0xDD] = MV_CIA2;
622 MapWriteDestination[0xDE] = MV_IO1;
623 MapWriteDestination[0xDF] = MV_IO2;
624 }break;
625
626 case 9: case 11:
627 {
628 /// READ
629 for(int i=0;i<32;++i)
630 {
631 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
632 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
633 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadKernalRom,this,std::placeholders::_1);
634 MapReadSource[0x80+i] = MV_RAM;
635 MapReadSource[0xA0+i] = MV_RAM;
636 MapReadSource[0xE0+i] = MV_KERNAL_ROM;
637 }
638 for(int i=0;i<16;++i)
639 {
640 CPUReadProcTbl[0xD0+i] = bind(&MMU::ReadCharRom,this,std::placeholders::_1);
641 MapReadSource[0xD0+i] = MV_CHAR_ROM;
642 }
643
644 /// WRITE
645 for(int i=0;i<32;++i)
646 {
647 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
648 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
649 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
650 MapWriteDestination[0x80+i] = MV_RAM;
651 MapWriteDestination[0xA0+i] = MV_RAM;
652 MapWriteDestination[0xE0+i] = MV_RAM;
653 }
654 for(int i=0;i<16;++i)
655 {
656 CPUWriteProcTbl[0xD0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
657 MapWriteDestination[0xD0+i] = MV_RAM;
658 }
659 }break;
660
661 case 21: case 23: case 20:
662 {
663 /// READ
664 for(int i=0;i<32;++i)
665 {
666 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
667 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
668 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
669 MapReadSource[0x80+i] = MV_RAM;
670 MapReadSource[0xA0+i] = MV_RAM;
671 MapReadSource[0xE0+i] = MV_RAM;
672 }
673 for(int i=0;i<4;++i)
674 {
675 CPUReadProcTbl[0xD0+i] = VicIOReadProc;
676 CPUReadProcTbl[0xD4+i] = SidIOReadProc;
677 CPUReadProcTbl[0xD8+i] = bind(&MMU::ReadFarbRam,this,std::placeholders::_1);
678 MapReadSource[0xD0+i] = MV_VIC;
679 MapReadSource[0xD4+i] = MV_SID;
680 MapReadSource[0xD8+i] = MV_FARB_RAM;
681 }
682 CPUReadProcTbl[0xDC] = Cia1IOReadProc;
683 CPUReadProcTbl[0xDD] = Cia2IOReadProc;
684 CPUReadProcTbl[0xDE] = IO1ReadProc;
685 CPUReadProcTbl[0xDF] = IO2ReadProc;
686 MapReadSource[0xDC] = MV_CIA1;
687 MapReadSource[0xDD] = MV_CIA2;
688 MapReadSource[0xDE] = MV_IO1;
689 MapReadSource[0xDF] = MV_IO2;
690
691 for(int i=0;i<32;++i)
692 {
693 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
694 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
695 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
696 MapWriteDestination[0x80+i] = MV_RAM;
697 MapWriteDestination[0xA0+i] = MV_RAM;
698 MapWriteDestination[0xE0+i] = MV_RAM;
699 }
700 for(int i=0;i<4;++i)
701 {
702 CPUWriteProcTbl[0xD0+i] = VicIOWriteProc;
703 CPUWriteProcTbl[0xD4+i] = SidIOWriteProc;
704 CPUWriteProcTbl[0xD8+i] = bind(&MMU::WriteFarbRam,this,std::placeholders::_1,std::placeholders::_2);
705 MapWriteDestination[0xD0+i] = MV_VIC;
706 MapWriteDestination[0xD4+i] = MV_SID;
707 MapWriteDestination[0xD8+i] = MV_FARB_RAM;
708 }
709 CPUWriteProcTbl[0xDC] = Cia1IOWriteProc;
710 CPUWriteProcTbl[0xDD] = Cia2IOWriteProc;
711 CPUWriteProcTbl[0xDE] = IO1WriteProc;
712 CPUWriteProcTbl[0xDF] = IO2WriteProc;
713 MapWriteDestination[0xDC] = MV_CIA1;
714 MapWriteDestination[0xDD] = MV_CIA2;
715 MapWriteDestination[0xDE] = MV_IO1;
716 MapWriteDestination[0xDF] = MV_IO2;
717 }break;
718
719 case 17: case 19:
720 {
721 /// READ
722 for(int i=0;i<32;++i)
723 {
724 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
725 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
726 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
727 MapReadSource[0x80+i] = MV_RAM;
728 MapReadSource[0xA0+i] = MV_RAM;
729 MapReadSource[0xE0+i] = MV_RAM;
730 }
731 for(int i=0;i<16;++i)
732 {
733 CPUReadProcTbl[0xD0+i] = bind(&MMU::ReadCharRom,this,std::placeholders::_1);
734 MapReadSource[0xD0+i] = MV_CHAR_ROM;
735 }
736
737 /// WRITE
738 for(int i=0;i<32;++i)
739 {
740 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
741 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
742 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
743 MapWriteDestination[0x80+i] = MV_RAM;
744 MapWriteDestination[0xA0+i] = MV_RAM;
745 MapWriteDestination[0xE0+i] = MV_RAM;
746 }
747 for(int i=0;i<16;++i)
748 {
749 CPUWriteProcTbl[0xD0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
750 MapWriteDestination[0xD0+i] = MV_RAM;
751 }
752 }break;
753
754 case 1: case 5: case 3: case 7: case 0: case 4: case 16:
755 {
756 /// READ
757 for(int i=0;i<32;++i)
758 {
759 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
760 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
761 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
762 MapReadSource[0x80+i] = MV_RAM;
763 MapReadSource[0xA0+i] = MV_RAM;
764 MapReadSource[0xE0+i] = MV_RAM;
765 }
766 for(int i=0;i<16;++i)
767 {
768 CPUReadProcTbl[0xD0+i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
769 MapReadSource[0xD0+i] = MV_RAM;
770 }
771
772 /// WRITE
773 for(int i=0;i<32;++i)
774 {
775 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
776 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
777 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
778 MapWriteDestination[0x80+i] = MV_RAM;
779 MapWriteDestination[0xA0+i] = MV_RAM;
780 MapWriteDestination[0xE0+i] = MV_RAM;
781 }
782 for(int i=0;i<16;++i)
783 {
784 CPUWriteProcTbl[0xD0+i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
785 MapWriteDestination[0xD0+i] = MV_RAM;
786 }
787 }break;
788
789 /// ULTIMAX Modus !!! ///
790 case 2: case 18: case 10: case 6: case 26: case 22: case 14: case 30:
791 {
792 /// READ
793 for(int i=0;i<112;i++)
794 {
795 CPUReadProcTbl[0x10+i] = bind(&MMU::ReadOpenAdress,this,std::placeholders::_1);
796 MapReadSource[0x10+i] = MV_OPEN;
797 }
798 for(int i=0;i<16;i++)
799 {
800 CPUReadProcTbl[0xC0+i] = bind(&MMU::ReadOpenAdress,this,std::placeholders::_1);
801 MapReadSource[0xC0+i] = MV_OPEN;
802 }
803 for(int i=0;i<32;++i)
804 {
805 CPUReadProcTbl[0x80+i] = bind(&MMU::ReadCRT1,this,std::placeholders::_1);
806 CPUReadProcTbl[0xA0+i] = bind(&MMU::ReadOpenAdress,this,std::placeholders::_1);
807 CPUReadProcTbl[0xE0+i] = bind(&MMU::ReadCRT3,this,std::placeholders::_1);
808 MapReadSource[0x80+i] = MV_CRT_1;
809 MapReadSource[0xA0+i] = MV_OPEN;
810 MapReadSource[0xE0+i] = MV_CRT_3;
811 }
812 for(int i=0;i<4;++i)
813 {
814 CPUReadProcTbl[0xD0+i] = VicIOReadProc;
815 CPUReadProcTbl[0xD4+i] = SidIOReadProc;
816 CPUReadProcTbl[0xD8+i] = bind(&MMU::ReadFarbRam,this,std::placeholders::_1);
817 MapReadSource[0xD0+i] = MV_VIC;
818 MapReadSource[0xD4+i] = MV_SID;
819 MapReadSource[0xD8+i] = MV_FARB_RAM;
820 }
821 CPUReadProcTbl[0xDC] = Cia1IOReadProc;
822 CPUReadProcTbl[0xDD] = Cia2IOReadProc;
823 CPUReadProcTbl[0xDE] = IO1ReadProc;
824 CPUReadProcTbl[0xDF] = IO2ReadProc;
825 MapReadSource[0xDC] = MV_CIA1;
826 MapReadSource[0xDD] = MV_CIA2;
827 MapReadSource[0xDE] = MV_IO1;
828 MapReadSource[0xDF] = MV_IO2;
829
830 /// WRITE
831 for(int i=0;i<112;i++)
832 {
833 CPUWriteProcTbl[0x10+i] = bind(&MMU::WriteOpenAdress,this,std::placeholders::_1,std::placeholders::_2);
834 MapWriteDestination[0x10+i] = MV_OPEN;
835 }
836 for(int i=0;i<16;i++)
837 {
838 CPUWriteProcTbl[0xC0+i] = bind(&MMU::WriteOpenAdress,this,std::placeholders::_1,std::placeholders::_2);
839 MapWriteDestination[0xC0+i] = MV_OPEN;
840 }
841 for(int i=0;i<32;++i)
842 {
843 CPUWriteProcTbl[0x80+i] = bind(&MMU::WriteCRT1,this,std::placeholders::_1,std::placeholders::_2);
844 CPUWriteProcTbl[0xA0+i] = bind(&MMU::WriteOpenAdress,this,std::placeholders::_1,std::placeholders::_2);
845 CPUWriteProcTbl[0xE0+i] = bind(&MMU::WriteCRT3,this,std::placeholders::_1,std::placeholders::_2);
846 MapWriteDestination[0x80+i] = MV_CRT_1;
847 MapWriteDestination[0xA0+i] = MV_OPEN;
848 MapWriteDestination[0xE0+i] = MV_CRT_3;
849 }
850 for(int i=0;i<4;++i)
851 {
852 CPUWriteProcTbl[0xD0+i] = VicIOWriteProc;
853 CPUWriteProcTbl[0xD4+i] = SidIOWriteProc;
854 CPUWriteProcTbl[0xD8+i] = bind(&MMU::WriteFarbRam,this,std::placeholders::_1,std::placeholders::_2);
855 MapWriteDestination[0xD0+i] = MV_VIC;
856 MapWriteDestination[0xD4+i] = MV_SID;
857 MapWriteDestination[0xD8+i] = MV_FARB_RAM;
858 }
859 CPUWriteProcTbl[0xDC] = Cia1IOWriteProc;
860 CPUWriteProcTbl[0xDD] = Cia2IOWriteProc;
861 CPUWriteProcTbl[0xDE] = IO1WriteProc;
862 CPUWriteProcTbl[0xDF] = IO2WriteProc;
863 MapWriteDestination[0xDC] = MV_CIA1;
864 MapWriteDestination[0xDD] = MV_CIA2;
865 MapWriteDestination[0xDE] = MV_IO1;
866 MapWriteDestination[0xDF] = MV_IO2;
867 }break;
868 }
869 MEMORY_MAP_OLD = MEMORY_MAP;
870 }
871
InitProcTables(void)872 inline void MMU::InitProcTables(void)
873 {
874 for(int i=0;i<256;++i)
875 {
876 CPUReadProcTbl[i] = bind(&MMU::ReadRam,this,std::placeholders::_1);
877 CPUWriteProcTbl[i] = bind(&MMU::WriteRam,this,std::placeholders::_1,std::placeholders::_2);
878 VICReadProcTbl[i] = bind(&MMU::ReadVicRam,this,std::placeholders::_1);
879 MapReadSource[i] = MV_RAM;
880 MapWriteDestination[i] = MV_RAM;
881 }
882
883 for(int i=0;i<16;++i)
884 {
885 VICReadProcTbl[0x10+i] = bind(&MMU::ReadVicCharRomBank0,this,std::placeholders::_1);
886 VICReadProcTbl[0x90+i] = bind(&MMU::ReadVicCharRomBank2,this,std::placeholders::_1);
887 }
888
889 CPUReadProcTbl[0] = bind(&MMU::ReadZeroPage,this,std::placeholders::_1);
890 CPUWriteProcTbl[0] = bind(&MMU::WriteZeroPage,this,std::placeholders::_1,std::placeholders::_2);
891 }
892
ReadZeroPage(unsigned short adresse)893 unsigned char MMU::ReadZeroPage(unsigned short adresse)
894 {
895 switch (adresse)
896 {
897 case 0:
898 return CPU_PORT->DIR_READ;
899 case 1:
900 return (CPU_PORT->DATA_READ & (0xFF - (((!CPU_PORT->DATA_SET_BIT6)<<6)+((!CPU_PORT->DATA_SET_BIT7)<<7))));
901 default:
902 return RAM[adresse];
903 }
904 }
905
WriteZeroPage(unsigned short adresse,unsigned char wert)906 void MMU::WriteZeroPage(unsigned short adresse, unsigned char wert)
907 {
908 switch (adresse)
909 {
910 case 0:
911 if (CPU_PORT->DATA_SET_BIT7 && ((wert & 0x80) == 0) && CPU_PORT->DATA_FALLOFF_BIT7 == 0)
912 {
913 CPU_PORT->DATA_FALLOFF_BIT7 = 1;
914 }
915 if (CPU_PORT->DATA_SET_BIT6 && ((wert & 0x40) == 0) && CPU_PORT->DATA_FALLOFF_BIT6 == 0)
916 {
917 CPU_PORT->DATA_FALLOFF_BIT6 = 1;
918 }
919 if (CPU_PORT->DATA_SET_BIT7 && (wert & 0x80) && CPU_PORT->DATA_FALLOFF_BIT7)
920 {
921 CPU_PORT->DATA_FALLOFF_BIT7 = 0;
922 }
923 if (CPU_PORT->DATA_SET_BIT6 && (wert & 0x40) && CPU_PORT->DATA_FALLOFF_BIT6)
924 {
925 CPU_PORT->DATA_FALLOFF_BIT6 = 0;
926 }
927 if (CPU_PORT->DIR != wert)
928 {
929 CPU_PORT->DIR = wert;
930 ChangeMemMap();
931 }
932 break;
933
934 case 1:
935 if ((CPU_PORT->DIR & 0x80) && (wert & 0x80))
936 {
937 CPU_PORT->DATA_SET_BIT7 = 1;
938 }
939 if ((CPU_PORT->DIR & 0x40) && (wert & 0x40))
940 {
941 CPU_PORT->DATA_SET_BIT6 = 1;
942 }
943
944 if (CPU_PORT->DATA != wert)
945 {
946 CPU_PORT->DATA = wert;
947 ChangeMemMap();
948 }
949 break;
950
951 default:
952 RAM[adresse] = wert;
953 }
954 }
955
ReadBasicRom(unsigned short adresse)956 unsigned char MMU::ReadBasicRom(unsigned short adresse)
957 {
958 return BASIC_ROM[adresse-0xA000];
959 }
960
ReadKernalRom(unsigned short adresse)961 unsigned char MMU::ReadKernalRom(unsigned short adresse)
962 {
963 return KERNAL_ROM[adresse-0xE000];
964 }
965
ReadCharRom(unsigned short adresse)966 unsigned char MMU::ReadCharRom(unsigned short adresse)
967 {
968 return CHAR_ROM[adresse-0xD000];
969 }
970
ReadRam(unsigned short adresse)971 unsigned char MMU::ReadRam(unsigned short adresse)
972 {
973 return RAM[adresse];
974 }
975
WriteRam(unsigned short adresse,unsigned char wert)976 void MMU::WriteRam(unsigned short adresse, unsigned char wert)
977 {
978 RAM[adresse] = wert;
979 }
980
ReadFarbRam(unsigned short adresse)981 unsigned char MMU::ReadFarbRam(unsigned short adresse)
982 {
983 return FARB_RAM[adresse-0xD800];
984 }
985
WriteFarbRam(unsigned short adresse,unsigned char wert)986 void MMU::WriteFarbRam(unsigned short adresse, unsigned char wert)
987 {
988 FARB_RAM[adresse-0xD800] = wert;
989 }
990
ReadCRT1(unsigned short adresse)991 unsigned char MMU::ReadCRT1(unsigned short adresse)
992 {
993 return CRTRom1ReadProc(adresse);
994 }
995
WriteCRT1(unsigned short adresse,unsigned char wert)996 void MMU::WriteCRT1(unsigned short adresse, unsigned char wert)
997 {
998 CRTRom1WriteProc(adresse,wert);
999 }
1000
ReadCRT2(unsigned short adresse)1001 unsigned char MMU::ReadCRT2(unsigned short adresse)
1002 {
1003 return CRTRom2ReadProc(adresse);
1004 }
1005
WriteCRT2(unsigned short adresse,unsigned char wert)1006 void MMU::WriteCRT2(unsigned short adresse, unsigned char wert)
1007 {
1008 CRTRom2WriteProc(adresse,wert);
1009 }
1010
ReadCRT3(unsigned short adresse)1011 unsigned char MMU::ReadCRT3(unsigned short adresse)
1012 {
1013 return CRTRom3ReadProc(adresse);
1014 }
1015
WriteCRT3(unsigned short adresse,unsigned char wert)1016 void MMU::WriteCRT3(unsigned short adresse, unsigned char wert)
1017 {
1018 CRTRom3WriteProc(adresse,wert);
1019 }
1020
ReadVicCharRomBank0(unsigned short adresse)1021 unsigned char MMU::ReadVicCharRomBank0(unsigned short adresse)
1022 {
1023 if(*EasyFlashDirty1)
1024 {
1025 *EasyFlashDirty1 = false;
1026 return *EasyFlashByte1;
1027 }
1028 return CHAR_ROM[adresse-0x1000];
1029 }
1030
ReadVicCharRomBank2(unsigned short adresse)1031 unsigned char MMU::ReadVicCharRomBank2(unsigned short adresse)
1032 {
1033 if(*EasyFlashDirty2 )
1034 {
1035 *EasyFlashDirty2 = false;
1036 return *EasyFlashByte2;
1037 }
1038 return CHAR_ROM[adresse-0x9000];
1039 }
1040
ReadVicRam(unsigned short adresse)1041 unsigned char MMU::ReadVicRam(unsigned short adresse)
1042 {
1043 switch(MEMORY_MAP)
1044 {
1045 case 2: case 18: case 10: case 6: case 26: case 22: case 14: case 30:
1046 if(adresse >= 0xE000) return CRTRom3ReadProc(adresse);
1047 break;
1048 }
1049 return RAM[adresse];
1050 }
1051
ReadOpenAdress(unsigned short)1052 unsigned char MMU::ReadOpenAdress(unsigned short)
1053 {
1054 return 0x88; // evtl. auf Zufallszahlen !? (steht eigtl. in der Doku)
1055 }
1056
WriteOpenAdress(unsigned short,unsigned char)1057 void MMU::WriteOpenAdress(unsigned short, unsigned char)
1058 {
1059 return;
1060 }
1061