1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2022 MediaTek Inc. */
3 
4 #ifndef __MT76_CONNAC2_MAC_H
5 #define __MT76_CONNAC2_MAC_H
6 
7 enum tx_header_format {
8 	MT_HDR_FORMAT_802_3,
9 	MT_HDR_FORMAT_CMD,
10 	MT_HDR_FORMAT_802_11,
11 	MT_HDR_FORMAT_802_11_EXT,
12 };
13 
14 enum tx_pkt_type {
15 	MT_TX_TYPE_CT,
16 	MT_TX_TYPE_SF,
17 	MT_TX_TYPE_CMD,
18 	MT_TX_TYPE_FW,
19 };
20 
21 enum {
22 	MT_CTX0,
23 	MT_HIF0 = 0x0,
24 
25 	MT_LMAC_AC00 = 0x0,
26 	MT_LMAC_AC01,
27 	MT_LMAC_AC02,
28 	MT_LMAC_AC03,
29 	MT_LMAC_ALTX0 = 0x10,
30 	MT_LMAC_BMC0,
31 	MT_LMAC_BCN0,
32 	MT_LMAC_PSMP0,
33 };
34 
35 #define MT_TX_FREE_MSDU_CNT		GENMASK(9, 0)
36 #define MT_TX_FREE_WLAN_ID		GENMASK(23, 14)
37 #define MT_TX_FREE_COUNT		GENMASK(12, 0)
38 /* 0: success, others: dropped */
39 #define MT_TX_FREE_STATUS		GENMASK(14, 13)
40 #define MT_TX_FREE_MSDU_ID		GENMASK(30, 16)
41 #define MT_TX_FREE_PAIR			BIT(31)
42 /* will support this field in further revision */
43 #define MT_TX_FREE_RATE			GENMASK(13, 0)
44 
45 #define MT_TXD0_Q_IDX			GENMASK(31, 25)
46 #define MT_TXD0_PKT_FMT			GENMASK(24, 23)
47 #define MT_TXD0_ETH_TYPE_OFFSET		GENMASK(22, 16)
48 #define MT_TXD0_TX_BYTES		GENMASK(15, 0)
49 
50 #define MT_TXD1_LONG_FORMAT		BIT(31)
51 #define MT_TXD1_TGID			BIT(30)
52 #define MT_TXD1_OWN_MAC			GENMASK(29, 24)
53 #define MT_TXD1_AMSDU			BIT(23)
54 #define MT_TXD1_TID			GENMASK(22, 20)
55 #define MT_TXD1_HDR_PAD			GENMASK(19, 18)
56 #define MT_TXD1_HDR_FORMAT		GENMASK(17, 16)
57 #define MT_TXD1_HDR_INFO		GENMASK(15, 11)
58 #define MT_TXD1_ETH_802_3		BIT(15)
59 #define MT_TXD1_VTA			BIT(10)
60 #define MT_TXD1_WLAN_IDX		GENMASK(9, 0)
61 
62 #define MT_TXD2_FIX_RATE		BIT(31)
63 #define MT_TXD2_FIXED_RATE		BIT(30)
64 #define MT_TXD2_POWER_OFFSET		GENMASK(29, 24)
65 #define MT_TXD2_MAX_TX_TIME		GENMASK(23, 16)
66 #define MT_TXD2_FRAG			GENMASK(15, 14)
67 #define MT_TXD2_HTC_VLD			BIT(13)
68 #define MT_TXD2_DURATION		BIT(12)
69 #define MT_TXD2_BIP			BIT(11)
70 #define MT_TXD2_MULTICAST		BIT(10)
71 #define MT_TXD2_RTS			BIT(9)
72 #define MT_TXD2_SOUNDING		BIT(8)
73 #define MT_TXD2_NDPA			BIT(7)
74 #define MT_TXD2_NDP			BIT(6)
75 #define MT_TXD2_FRAME_TYPE		GENMASK(5, 4)
76 #define MT_TXD2_SUB_TYPE		GENMASK(3, 0)
77 
78 #define MT_TXD3_SN_VALID		BIT(31)
79 #define MT_TXD3_PN_VALID		BIT(30)
80 #define MT_TXD3_SW_POWER_MGMT		BIT(29)
81 #define MT_TXD3_BA_DISABLE		BIT(28)
82 #define MT_TXD3_SEQ			GENMASK(27, 16)
83 #define MT_TXD3_REM_TX_COUNT		GENMASK(15, 11)
84 #define MT_TXD3_TX_COUNT		GENMASK(10, 6)
85 #define MT_TXD3_TIMING_MEASURE		BIT(5)
86 #define MT_TXD3_DAS			BIT(4)
87 #define MT_TXD3_EEOSP			BIT(3)
88 #define MT_TXD3_EMRD			BIT(2)
89 #define MT_TXD3_PROTECT_FRAME		BIT(1)
90 #define MT_TXD3_NO_ACK			BIT(0)
91 
92 #define MT_TXD4_PN_LOW			GENMASK(31, 0)
93 
94 #define MT_TXD5_PN_HIGH			GENMASK(31, 16)
95 #define MT_TXD5_MD			BIT(15)
96 #define MT_TXD5_ADD_BA			BIT(14)
97 #define MT_TXD5_TX_STATUS_HOST		BIT(10)
98 #define MT_TXD5_TX_STATUS_MCU		BIT(9)
99 #define MT_TXD5_TX_STATUS_FMT		BIT(8)
100 #define MT_TXD5_PID			GENMASK(7, 0)
101 
102 #define MT_TXD6_TX_IBF			BIT(31)
103 #define MT_TXD6_TX_EBF			BIT(30)
104 #define MT_TXD6_TX_RATE			GENMASK(29, 16)
105 #define MT_TXD6_SGI			GENMASK(15, 14)
106 #define MT_TXD6_HELTF			GENMASK(13, 12)
107 #define MT_TXD6_LDPC			BIT(11)
108 #define MT_TXD6_SPE_ID_IDX		BIT(10)
109 #define MT_TXD6_ANT_ID			GENMASK(7, 4)
110 #define MT_TXD6_DYN_BW			BIT(3)
111 #define MT_TXD6_FIXED_BW		BIT(2)
112 #define MT_TXD6_BW			GENMASK(1, 0)
113 
114 #define MT_TXD7_TXD_LEN			GENMASK(31, 30)
115 #define MT_TXD7_UDP_TCP_SUM		BIT(29)
116 #define MT_TXD7_IP_SUM			BIT(28)
117 #define MT_TXD7_TYPE			GENMASK(21, 20)
118 #define MT_TXD7_SUB_TYPE		GENMASK(19, 16)
119 
120 #define MT_TXD7_PSE_FID			GENMASK(27, 16)
121 #define MT_TXD7_SPE_IDX			GENMASK(15, 11)
122 #define MT_TXD7_HW_AMSDU		BIT(10)
123 #define MT_TXD7_TX_TIME			GENMASK(9, 0)
124 
125 #define MT_TXD8_L_TYPE			GENMASK(5, 4)
126 #define MT_TXD8_L_SUB_TYPE		GENMASK(3, 0)
127 
128 #define MT_TX_RATE_STBC			BIT(13)
129 #define MT_TX_RATE_NSS			GENMASK(12, 10)
130 #define MT_TX_RATE_MODE			GENMASK(9, 6)
131 #define MT_TX_RATE_SU_EXT_TONE		BIT(5)
132 #define MT_TX_RATE_DCM			BIT(4)
133 /* VHT/HE only use bits 0-3 */
134 #define MT_TX_RATE_IDX			GENMASK(5, 0)
135 
136 #define MT_TXS0_FIXED_RATE		BIT(31)
137 #define MT_TXS0_BW			GENMASK(30, 29)
138 #define MT_TXS0_TID			GENMASK(28, 26)
139 #define MT_TXS0_AMPDU			BIT(25)
140 #define MT_TXS0_TXS_FORMAT		GENMASK(24, 23)
141 #define MT_TXS0_BA_ERROR		BIT(22)
142 #define MT_TXS0_PS_FLAG			BIT(21)
143 #define MT_TXS0_TXOP_TIMEOUT		BIT(20)
144 #define MT_TXS0_BIP_ERROR		BIT(19)
145 
146 #define MT_TXS0_QUEUE_TIMEOUT		BIT(18)
147 #define MT_TXS0_RTS_TIMEOUT		BIT(17)
148 #define MT_TXS0_ACK_TIMEOUT		BIT(16)
149 #define MT_TXS0_ACK_ERROR_MASK		GENMASK(18, 16)
150 
151 #define MT_TXS0_TX_STATUS_HOST		BIT(15)
152 #define MT_TXS0_TX_STATUS_MCU		BIT(14)
153 #define MT_TXS0_TX_RATE			GENMASK(13, 0)
154 
155 #define MT_TXS1_SEQNO			GENMASK(31, 20)
156 #define MT_TXS1_RESP_RATE		GENMASK(19, 16)
157 #define MT_TXS1_RXV_SEQNO		GENMASK(15, 8)
158 #define MT_TXS1_TX_POWER_DBM		GENMASK(7, 0)
159 
160 #define MT_TXS2_BF_STATUS		GENMASK(31, 30)
161 #define MT_TXS2_LAST_TX_RATE		GENMASK(29, 27)
162 #define MT_TXS2_SHARED_ANTENNA		BIT(26)
163 #define MT_TXS2_WCID			GENMASK(25, 16)
164 #define MT_TXS2_TX_DELAY		GENMASK(15, 0)
165 
166 #define MT_TXS3_PID			GENMASK(31, 24)
167 #define MT_TXS3_ANT_ID			GENMASK(23, 0)
168 
169 #define MT_TXS4_TIMESTAMP		GENMASK(31, 0)
170 
171 /* PPDU based TXS */
172 #define MT_TXS5_MPDU_TX_BYTE		GENMASK(22, 0)
173 #define MT_TXS5_MPDU_TX_CNT		GENMASK(31, 23)
174 
175 #define MT_TXS6_MPDU_FAIL_CNT		GENMASK(31, 23)
176 #define MT_TXS7_MPDU_RETRY_BYTE		GENMASK(22, 0)
177 #define MT_TXS7_MPDU_RETRY_CNT		GENMASK(31, 23)
178 
179 /* RXD DW0 */
180 #define MT_RXD0_LENGTH			GENMASK(15, 0)
181 #define MT_RXD0_PKT_FLAG                GENMASK(19, 16)
182 #define MT_RXD0_PKT_TYPE		GENMASK(31, 27)
183 
184 #define MT_RXD0_NORMAL_ETH_TYPE_OFS	GENMASK(22, 16)
185 #define MT_RXD0_NORMAL_IP_SUM		BIT(23)
186 #define MT_RXD0_NORMAL_UDP_TCP_SUM	BIT(24)
187 
188 /* RXD DW1 */
189 #define MT_RXD1_NORMAL_WLAN_IDX		GENMASK(9, 0)
190 #define MT_RXD1_NORMAL_GROUP_1		BIT(11)
191 #define MT_RXD1_NORMAL_GROUP_2		BIT(12)
192 #define MT_RXD1_NORMAL_GROUP_3		BIT(13)
193 #define MT_RXD1_NORMAL_GROUP_4		BIT(14)
194 #define MT_RXD1_NORMAL_GROUP_5		BIT(15)
195 #define MT_RXD1_NORMAL_SEC_MODE		GENMASK(20, 16)
196 #define MT_RXD1_NORMAL_KEY_ID		GENMASK(22, 21)
197 #define MT_RXD1_NORMAL_CM		BIT(23)
198 #define MT_RXD1_NORMAL_CLM		BIT(24)
199 #define MT_RXD1_NORMAL_ICV_ERR		BIT(25)
200 #define MT_RXD1_NORMAL_TKIP_MIC_ERR	BIT(26)
201 #define MT_RXD1_NORMAL_FCS_ERR		BIT(27)
202 #define MT_RXD1_NORMAL_BAND_IDX		BIT(28)
203 #define MT_RXD1_NORMAL_SPP_EN		BIT(29)
204 #define MT_RXD1_NORMAL_ADD_OM		BIT(30)
205 #define MT_RXD1_NORMAL_SEC_DONE		BIT(31)
206 
207 /* RXD DW2 */
208 #define MT_RXD2_NORMAL_BSSID		GENMASK(5, 0)
209 #define MT_RXD2_NORMAL_CO_ANT		BIT(6)
210 #define MT_RXD2_NORMAL_BF_CQI		BIT(7)
211 #define MT_RXD2_NORMAL_MAC_HDR_LEN	GENMASK(12, 8)
212 #define MT_RXD2_NORMAL_HDR_TRANS	BIT(13)
213 #define MT_RXD2_NORMAL_HDR_OFFSET	GENMASK(15, 14)
214 #define MT_RXD2_NORMAL_TID		GENMASK(19, 16)
215 #define MT_RXD2_NORMAL_MU_BAR		BIT(21)
216 #define MT_RXD2_NORMAL_SW_BIT		BIT(22)
217 #define MT_RXD2_NORMAL_AMSDU_ERR	BIT(23)
218 #define MT_RXD2_NORMAL_MAX_LEN_ERROR	BIT(24)
219 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR	BIT(25)
220 #define MT_RXD2_NORMAL_INT_FRAME	BIT(26)
221 #define MT_RXD2_NORMAL_FRAG		BIT(27)
222 #define MT_RXD2_NORMAL_NULL_FRAME	BIT(28)
223 #define MT_RXD2_NORMAL_NDATA		BIT(29)
224 #define MT_RXD2_NORMAL_NON_AMPDU	BIT(30)
225 #define MT_RXD2_NORMAL_BF_REPORT	BIT(31)
226 
227 /* RXD DW4 */
228 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT	GENMASK(1, 0)
229 #define MT_RXD4_FIRST_AMSDU_FRAME	GENMASK(1, 0)
230 #define MT_RXD4_MID_AMSDU_FRAME		BIT(1)
231 #define MT_RXD4_LAST_AMSDU_FRAME	BIT(0)
232 #define MT_RXD4_NORMAL_PATTERN_DROP	BIT(9)
233 #define MT_RXD4_NORMAL_CLS		BIT(10)
234 #define MT_RXD4_NORMAL_OFLD		GENMASK(12, 11)
235 #define MT_RXD4_NORMAL_MAGIC_PKT	BIT(13)
236 #define MT_RXD4_NORMAL_WOL		GENMASK(18, 14)
237 #define MT_RXD4_NORMAL_CLS_BITMAP	GENMASK(28, 19)
238 #define MT_RXD3_NORMAL_PF_MODE		BIT(29)
239 #define MT_RXD3_NORMAL_PF_STS		GENMASK(31, 30)
240 
241 #define MT_RXV_HDR_BAND_IDX		BIT(24)
242 
243 /* RXD DW3 */
244 #define MT_RXD3_NORMAL_RXV_SEQ		GENMASK(7, 0)
245 #define MT_RXD3_NORMAL_CH_FREQ		GENMASK(15, 8)
246 #define MT_RXD3_NORMAL_ADDR_TYPE	GENMASK(17, 16)
247 #define MT_RXD3_NORMAL_U2M		BIT(0)
248 #define MT_RXD3_NORMAL_HTC_VLD		BIT(0)
249 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS	BIT(19)
250 #define MT_RXD3_NORMAL_BEACON_MC	BIT(20)
251 #define MT_RXD3_NORMAL_BEACON_UC	BIT(21)
252 #define MT_RXD3_NORMAL_AMSDU		BIT(22)
253 #define MT_RXD3_NORMAL_MESH		BIT(23)
254 #define MT_RXD3_NORMAL_MHCP		BIT(24)
255 #define MT_RXD3_NORMAL_NO_INFO_WB	BIT(25)
256 #define MT_RXD3_NORMAL_DISABLE_RX_HDR_TRANS	BIT(26)
257 #define MT_RXD3_NORMAL_POWER_SAVE_STAT	BIT(27)
258 #define MT_RXD3_NORMAL_MORE		BIT(28)
259 #define MT_RXD3_NORMAL_UNWANT		BIT(29)
260 #define MT_RXD3_NORMAL_RX_DROP		BIT(30)
261 #define MT_RXD3_NORMAL_VLAN2ETH		BIT(31)
262 
263 /* RXD GROUP4 */
264 #define MT_RXD6_FRAME_CONTROL		GENMASK(15, 0)
265 #define MT_RXD6_TA_LO			GENMASK(31, 16)
266 
267 #define MT_RXD7_TA_HI			GENMASK(31, 0)
268 
269 #define MT_RXD8_SEQ_CTRL		GENMASK(15, 0)
270 #define MT_RXD8_QOS_CTL			GENMASK(31, 16)
271 
272 #define MT_RXD9_HT_CONTROL		GENMASK(31, 0)
273 
274 /* P-RXV DW0 */
275 #define MT_PRXV_TX_RATE			GENMASK(6, 0)
276 #define MT_PRXV_TX_DCM			BIT(4)
277 #define MT_PRXV_TX_ER_SU_106T		BIT(5)
278 #define MT_PRXV_NSTS			GENMASK(9, 7)
279 #define MT_PRXV_TXBF			BIT(10)
280 #define MT_PRXV_HT_AD_CODE		BIT(11)
281 #define MT_PRXV_HE_RU_ALLOC_L		GENMASK(31, 28)
282 
283 #define MT_PRXV_FRAME_MODE		GENMASK(14, 12)
284 #define MT_PRXV_HT_SGI			GENMASK(16, 15)
285 #define MT_PRXV_HT_STBC			GENMASK(23, 22)
286 #define MT_PRXV_TX_MODE			GENMASK(27, 24)
287 #define MT_PRXV_DCM			BIT(17)
288 #define MT_PRXV_NUM_RX			BIT(20, 18)
289 
290 /* P-RXV DW1 */
291 #define MT_PRXV_RCPI3			GENMASK(31, 24)
292 #define MT_PRXV_RCPI2			GENMASK(23, 16)
293 #define MT_PRXV_RCPI1			GENMASK(15, 8)
294 #define MT_PRXV_RCPI0			GENMASK(7, 0)
295 #define MT_PRXV_HE_RU_ALLOC_H		GENMASK(3, 0)
296 
297 /* C-RXV */
298 #define MT_CRXV_HT_STBC			GENMASK(1, 0)
299 #define MT_CRXV_TX_MODE			GENMASK(7, 4)
300 #define MT_CRXV_FRAME_MODE		GENMASK(10, 8)
301 #define MT_CRXV_HT_SHORT_GI		GENMASK(14, 13)
302 #define MT_CRXV_HE_LTF_SIZE		GENMASK(18, 17)
303 #define MT_CRXV_HE_LDPC_EXT_SYM		BIT(20)
304 #define MT_CRXV_HE_PE_DISAMBIG		BIT(23)
305 #define MT_CRXV_HE_NUM_USER		GENMASK(30, 24)
306 #define MT_CRXV_HE_UPLINK		BIT(31)
307 
308 #define MT_CRXV_HE_RU0			GENMASK(7, 0)
309 #define MT_CRXV_HE_RU1			GENMASK(15, 8)
310 #define MT_CRXV_HE_RU2			GENMASK(23, 16)
311 #define MT_CRXV_HE_RU3			GENMASK(31, 24)
312 
313 #define MT_CRXV_HE_MU_AID		GENMASK(30, 20)
314 
315 #define MT_CRXV_HE_SR_MASK		GENMASK(11, 8)
316 #define MT_CRXV_HE_SR1_MASK		GENMASK(16, 12)
317 #define MT_CRXV_HE_SR2_MASK             GENMASK(20, 17)
318 #define MT_CRXV_HE_SR3_MASK             GENMASK(24, 21)
319 
320 #define MT_CRXV_HE_BSS_COLOR		GENMASK(5, 0)
321 #define MT_CRXV_HE_TXOP_DUR		GENMASK(12, 6)
322 #define MT_CRXV_HE_BEAM_CHNG		BIT(13)
323 #define MT_CRXV_HE_DOPPLER		BIT(16)
324 
325 #define MT_CRXV_SNR		GENMASK(18, 13)
326 #define MT_CRXV_FOE_LO		GENMASK(31, 19)
327 #define MT_CRXV_FOE_HI		GENMASK(6, 0)
328 #define MT_CRXV_FOE_SHIFT	13
329 
330 #define MT_CT_PARSE_LEN			72
331 #define MT_CT_DMA_BUF_NUM		2
332 
333 #define MT_CT_INFO_APPLY_TXD		BIT(0)
334 #define MT_CT_INFO_COPY_HOST_TXD_ALL	BIT(1)
335 #define MT_CT_INFO_MGMT_FRAME		BIT(2)
336 #define MT_CT_INFO_NONE_CIPHER_FRAME	BIT(3)
337 #define MT_CT_INFO_HSR2_TX		BIT(4)
338 #define MT_CT_INFO_FROM_HOST		BIT(7)
339 
340 enum tx_mcu_port_q_idx {
341 	MT_TX_MCU_PORT_RX_Q0 = 0x20,
342 	MT_TX_MCU_PORT_RX_Q1,
343 	MT_TX_MCU_PORT_RX_Q2,
344 	MT_TX_MCU_PORT_RX_Q3,
345 	MT_TX_MCU_PORT_RX_FWDL = 0x3e
346 };
347 
348 enum tx_port_idx {
349 	MT_TX_PORT_IDX_LMAC,
350 	MT_TX_PORT_IDX_MCU
351 };
352 
353 #endif /* __MT76_CONNAC2_MAC_H */
354