1 /* $OpenBSD: pciide_sis_reg.h,v 1.8 2010/07/23 07:47:13 jsg Exp $ */ 2 /* $NetBSD: pciide_sis_reg.h,v 1.6 2000/05/15 08:46:01 bouyer Exp $ */ 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef _DEV_PCI_PCIIDE_SIS_REG_H_ 30 #define _DEV_PCI_PCIIDE_SIS_REG_H_ 31 32 /* 33 * Registers definitions for SiS SiS5597/98 PCI IDE controller. 34 * Available from http://www.sis.com.tw/html/databook.html 35 */ 36 37 /* IDE timing control registers (32 bits), for all but 96x */ 38 #define SIS_TIM(channel) (0x40 + (channel * 4)) 39 /* for 730, 630 and older (66, 100OLD) */ 40 #define SIS_TIM66_REC_OFF(drive) (16 * (drive)) 41 #define SIS_TIM66_ACT_OFF(drive) (8 + 16 * (drive)) 42 #define SIS_TIM66_UDMA_TIME_OFF(drive) (12 + 16 * (drive)) 43 /* for older than 96x (100NEW, 133OLD) */ 44 #define SIS_TIM100_REC_OFF(drive) (16 * (drive)) 45 #define SIS_TIM100_ACT_OFF(drive) (4 + 16 * (drive)) 46 #define SIS_TIM100_UDMA_TIME_OFF(drive) (8 + 16 * (drive)) 47 48 /* 49 * From FreeBSD: on 96x, the timing registers may start from 0x40 or 0x70 50 * depending on the value from register 0x57. 32bits of timing info for 51 * each drive. 52 */ 53 #define SIS_TIM133(reg57, channel, drive) \ 54 ((((reg57) & 0x40) ? 0x70 : 0x40) + ((channel) << 3) + ((drive) << 2)) 55 56 /* IDE general control register 0 (8 bits) */ 57 #define SIS_CTRL0 0x4a 58 #define SIS_CTRL0_PCIBURST 0x80 59 #define SIS_CTRL0_FAST_PW 0x20 60 #define SIS_CTRL0_BO 0x08 61 #define SIS_CTRL0_CHAN0_EN 0x02 /* manual (v2.0) is wrong!!! */ 62 #define SIS_CTRL0_CHAN1_EN 0x04 /* manual (v2.0) is wrong!!! */ 63 64 /* IDE general control register 1 (8 bits) */ 65 #define SIS_CTRL1 0x4b 66 #define SIS_CTRL1_POSTW_EN(chan, drv) (0x10 << ((drv) + 2 * (chan))) 67 #define SIS_CTRL1_PREFETCH_EN(chan, drv) (0x01 << ((drv) + 2 * (chan))) 68 69 /* IDE misc control register (8 bit) */ 70 #define SIS_MISC 0x52 71 #define SIS_MISC_TIM_SEL 0x08 72 #define SIS_MISC_GTC 0x04 73 #define SIS_MISC_FIFO_SIZE 0x01 74 75 /* following are from FreeBSD (sorry, no description) */ 76 #define SIS_REG_49 0x49 77 #define SIS_REG_50 0x50 78 #define SIS_REG_51 0x51 79 #define SIS_REG_52 0x52 80 #define SIS_REG_53 0x53 81 #define SIS_REG_57 0x57 82 83 #define SIS_REG_CBL 0x48 84 #define SIS_REG_CBL_33(channel) (0x10 << (channel)) 85 #define SIS96x_REG_CBL(channel) (0x51 + (channel) * 2) 86 #define SIS96x_REG_CBL_33 0x80 87 88 #define SIS_PRODUCT_5518 0x5518 89 90 /* Private data */ 91 struct pciide_sis { 92 u_int8_t sis_type; 93 }; 94 95 /* timings values, mostly from FreeBSD */ 96 /* PIO timings, for all up to 133NEW */ 97 static const u_int8_t sis_pio_act[] = 98 {12, 6, 4, 3, 3}; 99 static const u_int8_t sis_pio_rec[] = 100 {11, 7, 4, 3, 1}; 101 /* DMA timings for 66 and 100OLD */ 102 static const u_int8_t sis_udma66_tim[] = 103 {15, 13, 11, 10, 9, 8}; 104 /* DMA timings for 100NEW */ 105 static const u_int8_t sis_udma100new_tim[] = 106 {0x8b, 0x87, 0x85, 0x84, 0x82, 0x81}; 107 /* DMA timings for 133OLD */ 108 static const u_int8_t sis_udma133old_tim[] = 109 {0x8f, 0x8a, 0x87, 0x85, 0x83, 0x82, 0x81}; 110 /* PIO, DMA and UDMA timings for 133NEW */ 111 static const u_int32_t sis_pio133new_tim[] = 112 {0x28269008, 0x0c266008, 0x4263008, 0x0c0a3008, 0x05093008}; 113 static const u_int32_t sis_dma133new_tim[] = 114 {0x22196008, 0x0c0a3008, 0x05093008}; 115 static const u_int32_t sis_udma133new_tim[] = 116 {0x9f4, 0x64a, 0x474, 0x254, 0x234, 0x224, 0x214}; 117 118 #endif /* !_DEV_PCI_PCIIDE_SIS_REG_H_ */ 119