1 /* pdp10_tim.c: PDP-10 tim subsystem simulator
2
3 Copyright (c) 1993-2012, Robert M Supnik
4
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
11
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
14
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 used in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
25
26 tim timer subsystem
27
28 18-Apr-12 RMS Removed absolute scheduling on reset
29 18-Jun-07 RMS Added UNIT_IDLE flag
30 03-Nov-06 RMS Rewritten to support idling
31 29-Oct-06 RMS Added clock coscheduling function
32 02-Feb-04 RMS Exported variables needed by Ethernet simulator
33 29-Jan-02 RMS New data structures
34 06-Jan-02 RMS Added enable/disable support
35 02-Dec-01 RMS Fixed bug in ITS PC sampling (found by Dave Conroy)
36 31-Aug-01 RMS Changed int64 to t_int64 for Windoze
37 17-Jul-01 RMS Moved function prototype
38 04-Jul-01 RMS Added DZ11 support
39 */
40
41 #include "pdp10_defs.h"
42 #include <time.h>
43
44 /* Invariants */
45
46 #define TIM_HW_FREQ 4100000 /* 4.1Mhz */
47 #define TIM_HWRE_MASK 07777
48 #define UNIT_V_Y2K (UNIT_V_UF + 0) /* Y2K compliant OS */
49 #define UNIT_Y2K (1u << UNIT_V_Y2K)
50
51 /* Clock mode TOPS-10/ITS */
52
53 #define TIM_TPS_T10 60
54 #define TIM_WAIT_T10 8000
55 #define TIM_MULT_T10 1
56 #define TIM_ITS_QUANT (TIM_HW_FREQ / TIM_TPS_T10)
57
58 /* Clock mode TOPS-20/KLAD */
59
60 #define TIM_TPS_T20 1001
61 #define TIM_WAIT_T20 500
62 #define TIM_MULT_T20 16
63
64 /* Probability function for TOPS-20 idlelock */
65
66 #define PROB(x) (((rand() * 100) / RAND_MAX) >= (x))
67
68 d10 tim_base[2] = { 0, 0 }; /* 71b timebase */
69 d10 tim_ttg = 0; /* time to go */
70 d10 tim_period = 0; /* period */
71 d10 quant = 0; /* ITS quantum */
72 int32 tim_mult = TIM_MULT_T10; /* tmxr poll mult */
73 int32 tim_t20_prob = 33; /* TOPS-20 prob */
74
75 /* Exported variables */
76
77 int32 clk_tps = TIM_TPS_T10; /* clock ticks/sec */
78 int32 tmr_poll = TIM_WAIT_T10; /* clock poll */
79 int32 tmxr_poll = TIM_WAIT_T10 * TIM_MULT_T10; /* term mux poll */
80
81 extern int32 apr_flg, pi_act;
82 extern UNIT cpu_unit;
83 extern d10 pcst;
84 extern a10 pager_PC;
85 extern int32 t20_idlelock;
86
87 DEVICE tim_dev;
88 t_stat tcu_rd (int32 *data, int32 PA, int32 access);
89 t_stat tim_svc (UNIT *uptr);
90 t_stat tim_reset (DEVICE *dptr);
91 void tim_incr_base (d10 *base, d10 incr);
92
93 extern d10 Read (a10 ea, int32 prv);
94 extern d10 ReadM (a10 ea, int32 prv);
95 extern void Write (a10 ea, d10 val, int32 prv);
96 extern void WriteP (a10 ea, d10 val);
97 extern int32 pi_eval (void);
98 extern t_stat wr_nop (int32 data, int32 PA, int32 access);
99
100 /* TIM data structures
101
102 tim_dev TIM device descriptor
103 tim_unit TIM unit descriptor
104 tim_reg TIM register list
105 */
106
107 DIB tcu_dib = { IOBA_TCU, IOLN_TCU, &tcu_rd, &wr_nop, 0 };
108
109 UNIT tim_unit = { UDATA (&tim_svc, UNIT_IDLE, 0), TIM_WAIT_T10 };
110
111 REG tim_reg[] = {
112 { BRDATA (TIMEBASE, tim_base, 8, 36, 2) },
113 { ORDATA (TTG, tim_ttg, 36) },
114 { ORDATA (PERIOD, tim_period, 36) },
115 { ORDATA (QUANT, quant, 36) },
116 { DRDATA (TIME, tim_unit.wait, 24), REG_NZ + PV_LEFT },
117 { DRDATA (PROB, tim_t20_prob, 6), REG_NZ + PV_LEFT + REG_HIDDEN },
118 { DRDATA (POLL, tmr_poll, 32), REG_HRO + PV_LEFT },
119 { DRDATA (MUXPOLL, tmxr_poll, 32), REG_HRO + PV_LEFT },
120 { DRDATA (MULT, tim_mult, 6), REG_HRO + PV_LEFT },
121 { DRDATA (TPS, clk_tps, 12), REG_HRO + PV_LEFT },
122 { NULL }
123 };
124
125 MTAB tim_mod[] = {
126 { UNIT_Y2K, 0, "non Y2K OS", "NOY2K", NULL },
127 { UNIT_Y2K, UNIT_Y2K, "Y2K OS", "Y2K", NULL },
128 { MTAB_XTD|MTAB_VDV, 000, "ADDRESS", NULL,
129 NULL, &show_addr, NULL },
130 { 0 }
131 };
132
133 DEVICE tim_dev = {
134 "TIM", &tim_unit, tim_reg, tim_mod,
135 1, 0, 0, 0, 0, 0,
136 NULL, NULL, &tim_reset,
137 NULL, NULL, NULL,
138 &tcu_dib, DEV_UBUS
139 };
140
141 /* Timer instructions */
142
143 /* Timer - if the timer is running at less than hardware frequency,
144 need to interpolate the value by calculating how much of the current
145 clock tick has elapsed, and what that equates to in msec. */
146
rdtim(a10 ea,int32 prv)147 t_bool rdtim (a10 ea, int32 prv)
148 {
149 d10 tempbase[2];
150
151 ReadM (INCA (ea), prv); /* check 2nd word */
152 tempbase[0] = tim_base[0]; /* copy time base */
153 tempbase[1] = tim_base[1];
154 if (tim_mult != TIM_MULT_T20) { /* interpolate? */
155 int32 used;
156 d10 incr;
157 used = tmr_poll - (sim_is_active (&tim_unit) - 1);
158 incr = (d10) (((double) used * TIM_HW_FREQ) /
159 ((double) tmr_poll * (double) clk_tps));
160 tim_incr_base (tempbase, incr);
161 }
162 tempbase[0] = tempbase[0] & ~((d10) TIM_HWRE_MASK); /* clear low 12b */
163 Write (ea, tempbase[0], prv);
164 Write (INCA(ea), tempbase[1], prv);
165 return FALSE;
166 }
167
wrtim(a10 ea,int32 prv)168 t_bool wrtim (a10 ea, int32 prv)
169 {
170 tim_base[0] = Read (ea, prv);
171 tim_base[1] = CLRS (Read (INCA (ea), prv));
172 return FALSE;
173 }
174
rdint(a10 ea,int32 prv)175 t_bool rdint (a10 ea, int32 prv)
176 {
177 Write (ea, tim_period, prv);
178 return FALSE;
179 }
180
wrint(a10 ea,int32 prv)181 t_bool wrint (a10 ea, int32 prv)
182 {
183 tim_period = Read (ea, prv);
184 tim_ttg = tim_period;
185 return FALSE;
186 }
187
188 /* Timer service - the timer is only serviced when the 'ttg' register
189 has reached 0 based on the expected frequency of clock interrupts. */
190
tim_svc(UNIT * uptr)191 t_stat tim_svc (UNIT *uptr)
192 {
193 if (cpu_unit.flags & UNIT_KLAD) /* diags? */
194 tmr_poll = uptr->wait; /* fixed clock */
195 else tmr_poll = sim_rtc_calb (clk_tps); /* else calibrate */
196 sim_activate (uptr, tmr_poll); /* reactivate unit */
197 tmxr_poll = tmr_poll * tim_mult; /* set mux poll */
198 tim_incr_base (tim_base, tim_period); /* incr time base */
199 tim_ttg = tim_period; /* reload */
200 apr_flg = apr_flg | APRF_TIM; /* request interrupt */
201 if (Q_ITS) { /* ITS? */
202 if (pi_act == 0)
203 quant = (quant + TIM_ITS_QUANT) & DMASK;
204 if (TSTS (pcst)) { /* PC sampling? */
205 WriteP ((a10) pcst & AMASK, pager_PC); /* store sample */
206 pcst = AOB (pcst); /* add 1,,1 */
207 }
208 } /* end ITS */
209 else if (t20_idlelock && PROB (100 - tim_t20_prob))
210 t20_idlelock = 0;
211 return SCPE_OK;
212 }
213
214 /* Clock coscheduling routine */
215
clk_cosched(int32 wait)216 int32 clk_cosched (int32 wait)
217 {
218 int32 t;
219
220 if (tim_mult == TIM_MULT_T20)
221 return wait;
222 t = sim_is_active (&tim_unit);
223 return (t? t - 1: wait);
224 }
225
tim_incr_base(d10 * base,d10 incr)226 void tim_incr_base (d10 *base, d10 incr)
227 {
228 base[1] = base[1] + incr; /* add on incr */
229 base[0] = base[0] + (base[1] >> 35); /* carry to high */
230 base[0] = base[0] & DMASK; /* mask high */
231 base[1] = base[1] & MMASK; /* mask low */
232 return;
233 }
234
235 /* Timer reset */
236
tim_reset(DEVICE * dptr)237 t_stat tim_reset (DEVICE *dptr)
238 {
239 tim_period = 0; /* clear timer */
240 tim_ttg = 0;
241 apr_flg = apr_flg & ~APRF_TIM; /* clear interrupt */
242 tmr_poll = sim_rtc_init (tim_unit.wait); /* init timer */
243 sim_activate (&tim_unit, tmr_poll); /* activate unit */
244 tmxr_poll = tmr_poll * tim_mult; /* set mux poll */
245 return SCPE_OK;
246 }
247
248 /* Set timer parameters from CPU model */
249
tim_set_mod(UNIT * uptr,int32 val,char * cptr,void * desc)250 t_stat tim_set_mod (UNIT *uptr, int32 val, char *cptr, void *desc)
251 {
252 if (val & (UNIT_T20|UNIT_KLAD)) {
253 clk_tps = TIM_TPS_T20;
254 uptr->wait = TIM_WAIT_T20;
255 tmr_poll = TIM_WAIT_T20;
256 tim_mult = TIM_MULT_T20;
257 uptr->flags = uptr->flags | UNIT_Y2K;
258 }
259 else {
260 clk_tps = TIM_TPS_T10;
261 uptr->wait = TIM_WAIT_T10;
262 tmr_poll = TIM_WAIT_T10;
263 tim_mult = TIM_MULT_T10;
264 if (Q_ITS)
265 uptr->flags = uptr->flags | UNIT_Y2K;
266 else uptr->flags = uptr->flags & ~UNIT_Y2K;
267 }
268 tmxr_poll = tmr_poll * tim_mult;
269 return SCPE_OK;
270 }
271
272 /* Time of year clock */
273
tcu_rd(int32 * data,int32 PA,int32 access)274 t_stat tcu_rd (int32 *data, int32 PA, int32 access)
275 {
276 time_t curtim;
277 struct tm *tptr;
278
279 curtim = time (NULL); /* get time */
280 tptr = localtime (&curtim); /* decompose */
281 if (tptr == NULL)
282 return SCPE_NXM;
283 if ((tptr->tm_year > 99) && !(tim_unit.flags & UNIT_Y2K))
284 tptr->tm_year = 99; /* Y2K prob? */
285
286 switch ((PA >> 1) & 03) { /* decode PA<3:1> */
287
288 case 0: /* year/month/day */
289 *data = (((tptr->tm_year) & 0177) << 9) |
290 (((tptr->tm_mon + 1) & 017) << 5) |
291 ((tptr->tm_mday) & 037);
292 return SCPE_OK;
293
294 case 1: /* hour/minute */
295 *data = (((tptr->tm_hour) & 037) << 8) |
296 ((tptr->tm_min) & 077);
297 return SCPE_OK;
298
299 case 2: /* second */
300 *data = (tptr->tm_sec) & 077;
301 return SCPE_OK;
302
303 case 3: /* status */
304 *data = CSR_DONE;
305 return SCPE_OK;
306 }
307
308 return SCPE_NXM; /* can't get here */
309 }
310