1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon.h"
30 #include "radeon_asic.h"
31 #include "atom.h"
32 #include <linux/delay.h>
33
radeon_legacy_encoder_disable(struct drm_encoder * encoder)34 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
35 {
36 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
37 const struct drm_encoder_helper_funcs *encoder_funcs;
38
39 encoder_funcs = encoder->helper_private;
40 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
41 radeon_encoder->active_device = 0;
42 }
43
radeon_legacy_lvds_update(struct drm_encoder * encoder,int mode)44 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
45 {
46 struct drm_device *dev = encoder->dev;
47 struct radeon_device *rdev = dev->dev_private;
48 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
49 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
50 int panel_pwr_delay = 2000;
51 bool is_mac = false;
52 uint8_t backlight_level;
53 DRM_DEBUG_KMS("\n");
54
55 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
56 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
57
58 if (radeon_encoder->enc_priv) {
59 if (rdev->is_atom_bios) {
60 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
61 panel_pwr_delay = lvds->panel_pwr_delay;
62 if (lvds->bl_dev)
63 backlight_level = lvds->backlight_level;
64 } else {
65 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
66 panel_pwr_delay = lvds->panel_pwr_delay;
67 if (lvds->bl_dev)
68 backlight_level = lvds->backlight_level;
69 }
70 }
71
72 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
73 * Taken from radeonfb.
74 */
75 if ((rdev->mode_info.connector_table == CT_IBOOK) ||
76 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
77 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
78 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
79 is_mac = true;
80
81 switch (mode) {
82 case DRM_MODE_DPMS_ON:
83 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
84 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
85 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
86 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
87 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
88 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
89 mdelay(1);
90
91 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
92 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
93 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
94
95 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
96 RADEON_LVDS_BL_MOD_LEVEL_MASK);
97 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
98 RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
99 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
100 if (is_mac)
101 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
102 mdelay(panel_pwr_delay);
103 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
104 break;
105 case DRM_MODE_DPMS_STANDBY:
106 case DRM_MODE_DPMS_SUSPEND:
107 case DRM_MODE_DPMS_OFF:
108 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
109 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
110 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
111 if (is_mac) {
112 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
113 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
114 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
115 } else {
116 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
117 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
118 }
119 mdelay(panel_pwr_delay);
120 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
121 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
122 mdelay(panel_pwr_delay);
123 break;
124 }
125
126 if (rdev->is_atom_bios)
127 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
128 else
129 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
130
131 }
132
radeon_legacy_lvds_dpms(struct drm_encoder * encoder,int mode)133 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
134 {
135 struct radeon_device *rdev = encoder->dev->dev_private;
136 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
137 DRM_DEBUG("\n");
138
139 if (radeon_encoder->enc_priv) {
140 if (rdev->is_atom_bios) {
141 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
142 lvds->dpms_mode = mode;
143 } else {
144 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
145 lvds->dpms_mode = mode;
146 }
147 }
148
149 radeon_legacy_lvds_update(encoder, mode);
150 }
151
radeon_legacy_lvds_prepare(struct drm_encoder * encoder)152 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
153 {
154 struct radeon_device *rdev = encoder->dev->dev_private;
155
156 if (rdev->is_atom_bios)
157 radeon_atom_output_lock(encoder, true);
158 else
159 radeon_combios_output_lock(encoder, true);
160 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
161 }
162
radeon_legacy_lvds_commit(struct drm_encoder * encoder)163 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
164 {
165 struct radeon_device *rdev = encoder->dev->dev_private;
166
167 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
168 if (rdev->is_atom_bios)
169 radeon_atom_output_lock(encoder, false);
170 else
171 radeon_combios_output_lock(encoder, false);
172 }
173
radeon_legacy_lvds_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)174 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
175 struct drm_display_mode *mode,
176 struct drm_display_mode *adjusted_mode)
177 {
178 struct drm_device *dev = encoder->dev;
179 struct radeon_device *rdev = dev->dev_private;
180 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
181 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
182 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
183
184 DRM_DEBUG_KMS("\n");
185
186 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
187 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
188
189 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
190 if (rdev->is_atom_bios) {
191 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
192 * need to call that on resume to set up the reg properly.
193 */
194 radeon_encoder->pixel_clock = adjusted_mode->clock;
195 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
196 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
197 } else {
198 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
199 if (lvds) {
200 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
201 lvds_gen_cntl = lvds->lvds_gen_cntl;
202 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
203 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
204 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
205 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
206 } else
207 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
208 }
209 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
210 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
211 RADEON_LVDS_BLON |
212 RADEON_LVDS_EN |
213 RADEON_LVDS_RST_FM);
214
215 if (ASIC_IS_R300(rdev))
216 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
217
218 if (radeon_crtc->crtc_id == 0) {
219 if (ASIC_IS_R300(rdev)) {
220 if (radeon_encoder->rmx_type != RMX_OFF)
221 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
222 } else
223 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
224 } else {
225 if (ASIC_IS_R300(rdev))
226 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
227 else
228 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
229 }
230
231 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
232 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
233 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
234
235 if (rdev->family == CHIP_RV410)
236 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
237
238 if (rdev->is_atom_bios)
239 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
240 else
241 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
242 }
243
radeon_legacy_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)244 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
245 const struct drm_display_mode *mode,
246 struct drm_display_mode *adjusted_mode)
247 {
248 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
249
250 /* set the active encoder to connector routing */
251 radeon_encoder_set_active_device(encoder);
252 drm_mode_set_crtcinfo(adjusted_mode, 0);
253
254 /* get the native mode for LVDS */
255 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
256 radeon_panel_mode_fixup(encoder, adjusted_mode);
257
258 return true;
259 }
260
261 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
262 .dpms = radeon_legacy_lvds_dpms,
263 .mode_fixup = radeon_legacy_mode_fixup,
264 .prepare = radeon_legacy_lvds_prepare,
265 .mode_set = radeon_legacy_lvds_mode_set,
266 .commit = radeon_legacy_lvds_commit,
267 .disable = radeon_legacy_encoder_disable,
268 };
269
270 u8
radeon_legacy_get_backlight_level(struct radeon_encoder * radeon_encoder)271 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
272 {
273 struct drm_device *dev = radeon_encoder->base.dev;
274 struct radeon_device *rdev = dev->dev_private;
275 u8 backlight_level;
276
277 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
278 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
279
280 return backlight_level;
281 }
282
283 void
radeon_legacy_set_backlight_level(struct radeon_encoder * radeon_encoder,u8 level)284 radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
285 {
286 struct drm_device *dev = radeon_encoder->base.dev;
287 struct radeon_device *rdev = dev->dev_private;
288 int dpms_mode = DRM_MODE_DPMS_ON;
289
290 if (radeon_encoder->enc_priv) {
291 if (rdev->is_atom_bios) {
292 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
293 if (lvds->backlight_level > 0)
294 dpms_mode = lvds->dpms_mode;
295 else
296 dpms_mode = DRM_MODE_DPMS_OFF;
297 lvds->backlight_level = level;
298 } else {
299 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
300 if (lvds->backlight_level > 0)
301 dpms_mode = lvds->dpms_mode;
302 else
303 dpms_mode = DRM_MODE_DPMS_OFF;
304 lvds->backlight_level = level;
305 }
306 }
307
308 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
309 }
310
311 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
312
313 #if 0
314 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
315 {
316 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
317 uint8_t level;
318
319 /* Convert brightness to hardware level */
320 if (bd->props.brightness < 0)
321 level = 0;
322 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
323 level = RADEON_MAX_BL_LEVEL;
324 else
325 level = bd->props.brightness;
326
327 if (pdata->negative)
328 level = RADEON_MAX_BL_LEVEL - level;
329
330 return level;
331 }
332
333 static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
334 {
335 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
336 struct radeon_encoder *radeon_encoder = pdata->encoder;
337
338 radeon_legacy_set_backlight_level(radeon_encoder,
339 radeon_legacy_lvds_level(bd));
340
341 return 0;
342 }
343
344 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
345 {
346 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
347 struct radeon_encoder *radeon_encoder = pdata->encoder;
348 struct drm_device *dev = radeon_encoder->base.dev;
349 struct radeon_device *rdev = dev->dev_private;
350 uint8_t backlight_level;
351
352 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
353 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
354
355 return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
356 }
357
358 static const struct backlight_ops radeon_backlight_ops = {
359 .get_brightness = radeon_legacy_backlight_get_brightness,
360 .update_status = radeon_legacy_backlight_update_status,
361 };
362 #endif
363
radeon_legacy_backlight_init(struct radeon_encoder * radeon_encoder,struct drm_connector * drm_connector)364 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
365 struct drm_connector *drm_connector)
366 {
367 #if 0
368 struct drm_device *dev = radeon_encoder->base.dev;
369 struct radeon_device *rdev = dev->dev_private;
370 struct backlight_device *bd;
371 struct backlight_properties props;
372 struct radeon_backlight_privdata *pdata;
373 uint8_t backlight_level;
374 char bl_name[16];
375
376 if (!radeon_encoder->enc_priv)
377 return;
378
379 #ifdef CONFIG_PMAC_BACKLIGHT
380 if (!pmac_has_backlight_type("ati") &&
381 !pmac_has_backlight_type("mnca"))
382 return;
383 #endif
384
385 pdata = kmalloc(sizeof(struct radeon_backlight_privdata),
386 M_DRM, M_WAITOK);
387 if (!pdata) {
388 DRM_ERROR("Memory allocation failed\n");
389 goto error;
390 }
391
392 memset(&props, 0, sizeof(props));
393 props.max_brightness = RADEON_MAX_BL_LEVEL;
394 props.type = BACKLIGHT_RAW;
395 ksnprintf(bl_name, sizeof(bl_name),
396 "radeon_bl%d", dev->primary->index);
397 bd = backlight_device_register(bl_name, drm_connector->kdev,
398 pdata, &radeon_backlight_ops, &props);
399 if (IS_ERR(bd)) {
400 DRM_ERROR("Backlight registration failed\n");
401 goto error;
402 }
403
404 pdata->encoder = radeon_encoder;
405
406 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
407 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
408
409 /* First, try to detect backlight level sense based on the assumption
410 * that firmware set it up at full brightness
411 */
412 if (backlight_level == 0)
413 pdata->negative = true;
414 else if (backlight_level == 0xff)
415 pdata->negative = false;
416 else {
417 /* XXX hack... maybe some day we can figure out in what direction
418 * backlight should work on a given panel?
419 */
420 pdata->negative = (rdev->family != CHIP_RV200 &&
421 rdev->family != CHIP_RV250 &&
422 rdev->family != CHIP_RV280 &&
423 rdev->family != CHIP_RV350);
424
425 #ifdef CONFIG_PMAC_BACKLIGHT
426 pdata->negative = (pdata->negative ||
427 of_machine_is_compatible("PowerBook4,3") ||
428 of_machine_is_compatible("PowerBook6,3") ||
429 of_machine_is_compatible("PowerBook6,5"));
430 #endif
431 }
432
433 if (rdev->is_atom_bios) {
434 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
435 lvds->bl_dev = bd;
436 } else {
437 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
438 lvds->bl_dev = bd;
439 }
440
441 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
442 bd->props.power = FB_BLANK_UNBLANK;
443 backlight_update_status(bd);
444
445 DRM_INFO("radeon legacy LVDS backlight initialized\n");
446 rdev->mode_info.bl_encoder = radeon_encoder;
447
448 return;
449
450 error:
451 kfree(pdata);
452 return;
453 #endif
454 }
455
radeon_legacy_backlight_exit(struct radeon_encoder * radeon_encoder)456 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
457 {
458 #if 0
459 struct drm_device *dev = radeon_encoder->base.dev;
460 struct radeon_device *rdev = dev->dev_private;
461 struct backlight_device *bd = NULL;
462
463 if (!radeon_encoder->enc_priv)
464 return;
465
466 if (rdev->is_atom_bios) {
467 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
468 bd = lvds->bl_dev;
469 lvds->bl_dev = NULL;
470 } else {
471 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
472 bd = lvds->bl_dev;
473 lvds->bl_dev = NULL;
474 }
475
476 if (bd) {
477 struct radeon_backlight_privdata *pdata;
478
479 pdata = bl_get_data(bd);
480 backlight_device_unregister(bd);
481 kfree(pdata);
482
483 DRM_INFO("radeon legacy LVDS backlight unloaded\n");
484 }
485 #endif
486 }
487
488 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
489
radeon_legacy_backlight_init(struct radeon_encoder * encoder,struct drm_connector * drm_connector)490 void radeon_legacy_backlight_init(struct radeon_encoder *encoder,
491 struct drm_connector *drm_connector)
492 {
493 }
494
radeon_legacy_backlight_exit(struct radeon_encoder * encoder)495 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
496 {
497 }
498
499 #endif
500
501
radeon_lvds_enc_destroy(struct drm_encoder * encoder)502 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
503 {
504 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
505
506 if (radeon_encoder->enc_priv) {
507 radeon_legacy_backlight_exit(radeon_encoder);
508 kfree(radeon_encoder->enc_priv);
509 }
510 drm_encoder_cleanup(encoder);
511 kfree(radeon_encoder);
512 }
513
514 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
515 .destroy = radeon_lvds_enc_destroy,
516 };
517
radeon_legacy_primary_dac_dpms(struct drm_encoder * encoder,int mode)518 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
519 {
520 struct drm_device *dev = encoder->dev;
521 struct radeon_device *rdev = dev->dev_private;
522 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
523 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
524 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
525
526 DRM_DEBUG_KMS("\n");
527
528 switch (mode) {
529 case DRM_MODE_DPMS_ON:
530 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
531 dac_cntl &= ~RADEON_DAC_PDWN;
532 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
533 RADEON_DAC_PDWN_G |
534 RADEON_DAC_PDWN_B);
535 break;
536 case DRM_MODE_DPMS_STANDBY:
537 case DRM_MODE_DPMS_SUSPEND:
538 case DRM_MODE_DPMS_OFF:
539 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
540 dac_cntl |= RADEON_DAC_PDWN;
541 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
542 RADEON_DAC_PDWN_G |
543 RADEON_DAC_PDWN_B);
544 break;
545 }
546
547 /* handled in radeon_crtc_dpms() */
548 if (!(rdev->flags & RADEON_SINGLE_CRTC))
549 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
550 WREG32(RADEON_DAC_CNTL, dac_cntl);
551 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
552
553 if (rdev->is_atom_bios)
554 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
555 else
556 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
557
558 }
559
radeon_legacy_primary_dac_prepare(struct drm_encoder * encoder)560 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
561 {
562 struct radeon_device *rdev = encoder->dev->dev_private;
563
564 if (rdev->is_atom_bios)
565 radeon_atom_output_lock(encoder, true);
566 else
567 radeon_combios_output_lock(encoder, true);
568 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
569 }
570
radeon_legacy_primary_dac_commit(struct drm_encoder * encoder)571 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
572 {
573 struct radeon_device *rdev = encoder->dev->dev_private;
574
575 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
576
577 if (rdev->is_atom_bios)
578 radeon_atom_output_lock(encoder, false);
579 else
580 radeon_combios_output_lock(encoder, false);
581 }
582
radeon_legacy_primary_dac_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)583 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
584 struct drm_display_mode *mode,
585 struct drm_display_mode *adjusted_mode)
586 {
587 struct drm_device *dev = encoder->dev;
588 struct radeon_device *rdev = dev->dev_private;
589 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
590 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
591 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
592
593 DRM_DEBUG_KMS("\n");
594
595 if (radeon_crtc->crtc_id == 0) {
596 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
597 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
598 ~(RADEON_DISP_DAC_SOURCE_MASK);
599 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
600 } else {
601 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
602 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
603 }
604 } else {
605 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
606 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
607 ~(RADEON_DISP_DAC_SOURCE_MASK);
608 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
609 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
610 } else {
611 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
612 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
613 }
614 }
615
616 dac_cntl = (RADEON_DAC_MASK_ALL |
617 RADEON_DAC_VGA_ADR_EN |
618 /* TODO 6-bits */
619 RADEON_DAC_8BIT_EN);
620
621 WREG32_P(RADEON_DAC_CNTL,
622 dac_cntl,
623 RADEON_DAC_RANGE_CNTL |
624 RADEON_DAC_BLANKING);
625
626 if (radeon_encoder->enc_priv) {
627 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
628 dac_macro_cntl = p_dac->ps2_pdac_adj;
629 } else
630 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
631 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
632 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
633
634 if (rdev->is_atom_bios)
635 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
636 else
637 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
638 }
639
radeon_legacy_primary_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)640 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
641 struct drm_connector *connector)
642 {
643 struct drm_device *dev = encoder->dev;
644 struct radeon_device *rdev = dev->dev_private;
645 uint32_t vclk_ecp_cntl, crtc_ext_cntl;
646 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
647 enum drm_connector_status found = connector_status_disconnected;
648 bool color = true;
649
650 /* just don't bother on RN50 those chip are often connected to remoting
651 * console hw and often we get failure to load detect those. So to make
652 * everyone happy report the encoder as always connected.
653 */
654 if (ASIC_IS_RN50(rdev)) {
655 return connector_status_connected;
656 }
657
658 /* save the regs we need */
659 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
660 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
661 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
662 dac_cntl = RREG32(RADEON_DAC_CNTL);
663 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
664
665 tmp = vclk_ecp_cntl &
666 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
667 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
668
669 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
670 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
671
672 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
673 RADEON_DAC_FORCE_DATA_EN;
674
675 if (color)
676 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
677 else
678 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
679
680 if (ASIC_IS_R300(rdev))
681 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
682 else if (ASIC_IS_RV100(rdev))
683 tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
684 else
685 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
686
687 WREG32(RADEON_DAC_EXT_CNTL, tmp);
688
689 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
690 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
691 WREG32(RADEON_DAC_CNTL, tmp);
692
693 tmp = dac_macro_cntl;
694 tmp &= ~(RADEON_DAC_PDWN_R |
695 RADEON_DAC_PDWN_G |
696 RADEON_DAC_PDWN_B);
697
698 WREG32(RADEON_DAC_MACRO_CNTL, tmp);
699
700 mdelay(2);
701
702 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
703 found = connector_status_connected;
704
705 /* restore the regs we used */
706 WREG32(RADEON_DAC_CNTL, dac_cntl);
707 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
708 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
709 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
710 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
711
712 return found;
713 }
714
715 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
716 .dpms = radeon_legacy_primary_dac_dpms,
717 .mode_fixup = radeon_legacy_mode_fixup,
718 .prepare = radeon_legacy_primary_dac_prepare,
719 .mode_set = radeon_legacy_primary_dac_mode_set,
720 .commit = radeon_legacy_primary_dac_commit,
721 .detect = radeon_legacy_primary_dac_detect,
722 .disable = radeon_legacy_encoder_disable,
723 };
724
725
726 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
727 .destroy = radeon_enc_destroy,
728 };
729
radeon_legacy_tmds_int_dpms(struct drm_encoder * encoder,int mode)730 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
731 {
732 struct drm_device *dev = encoder->dev;
733 struct radeon_device *rdev = dev->dev_private;
734 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
735 DRM_DEBUG_KMS("\n");
736
737 switch (mode) {
738 case DRM_MODE_DPMS_ON:
739 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
740 break;
741 case DRM_MODE_DPMS_STANDBY:
742 case DRM_MODE_DPMS_SUSPEND:
743 case DRM_MODE_DPMS_OFF:
744 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
745 break;
746 }
747
748 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
749
750 if (rdev->is_atom_bios)
751 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
752 else
753 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
754
755 }
756
radeon_legacy_tmds_int_prepare(struct drm_encoder * encoder)757 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
758 {
759 struct radeon_device *rdev = encoder->dev->dev_private;
760
761 if (rdev->is_atom_bios)
762 radeon_atom_output_lock(encoder, true);
763 else
764 radeon_combios_output_lock(encoder, true);
765 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
766 }
767
radeon_legacy_tmds_int_commit(struct drm_encoder * encoder)768 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
769 {
770 struct radeon_device *rdev = encoder->dev->dev_private;
771
772 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
773
774 if (rdev->is_atom_bios)
775 radeon_atom_output_lock(encoder, true);
776 else
777 radeon_combios_output_lock(encoder, true);
778 }
779
radeon_legacy_tmds_int_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)780 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
781 struct drm_display_mode *mode,
782 struct drm_display_mode *adjusted_mode)
783 {
784 struct drm_device *dev = encoder->dev;
785 struct radeon_device *rdev = dev->dev_private;
786 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
787 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
788 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
789 int i;
790
791 DRM_DEBUG_KMS("\n");
792
793 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
794 tmp &= 0xfffff;
795 if (rdev->family == CHIP_RV280) {
796 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
797 tmp ^= (1 << 22);
798 tmds_pll_cntl ^= (1 << 22);
799 }
800
801 if (radeon_encoder->enc_priv) {
802 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
803
804 for (i = 0; i < 4; i++) {
805 if (tmds->tmds_pll[i].freq == 0)
806 break;
807 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
808 tmp = tmds->tmds_pll[i].value ;
809 break;
810 }
811 }
812 }
813
814 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
815 if (tmp & 0xfff00000)
816 tmds_pll_cntl = tmp;
817 else {
818 tmds_pll_cntl &= 0xfff00000;
819 tmds_pll_cntl |= tmp;
820 }
821 } else
822 tmds_pll_cntl = tmp;
823
824 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
825 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
826
827 if (rdev->family == CHIP_R200 ||
828 rdev->family == CHIP_R100 ||
829 ASIC_IS_R300(rdev))
830 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
831 else /* RV chips got this bit reversed */
832 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
833
834 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
835 (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
836 RADEON_FP_CRTC_DONT_SHADOW_HEND));
837
838 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
839
840 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
841 RADEON_FP_DFP_SYNC_SEL |
842 RADEON_FP_CRT_SYNC_SEL |
843 RADEON_FP_CRTC_LOCK_8DOT |
844 RADEON_FP_USE_SHADOW_EN |
845 RADEON_FP_CRTC_USE_SHADOW_VEND |
846 RADEON_FP_CRT_SYNC_ALT);
847
848 if (1) /* FIXME rgbBits == 8 */
849 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
850 else
851 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
852
853 if (radeon_crtc->crtc_id == 0) {
854 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
855 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
856 if (radeon_encoder->rmx_type != RMX_OFF)
857 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
858 else
859 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
860 } else
861 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
862 } else {
863 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
864 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
865 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
866 } else
867 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
868 }
869
870 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
871 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
872 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
873
874 if (rdev->is_atom_bios)
875 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
876 else
877 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
878 }
879
880 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
881 .dpms = radeon_legacy_tmds_int_dpms,
882 .mode_fixup = radeon_legacy_mode_fixup,
883 .prepare = radeon_legacy_tmds_int_prepare,
884 .mode_set = radeon_legacy_tmds_int_mode_set,
885 .commit = radeon_legacy_tmds_int_commit,
886 .disable = radeon_legacy_encoder_disable,
887 };
888
889
890 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
891 .destroy = radeon_enc_destroy,
892 };
893
radeon_legacy_tmds_ext_dpms(struct drm_encoder * encoder,int mode)894 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
895 {
896 struct drm_device *dev = encoder->dev;
897 struct radeon_device *rdev = dev->dev_private;
898 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
899 DRM_DEBUG_KMS("\n");
900
901 switch (mode) {
902 case DRM_MODE_DPMS_ON:
903 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
904 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
905 break;
906 case DRM_MODE_DPMS_STANDBY:
907 case DRM_MODE_DPMS_SUSPEND:
908 case DRM_MODE_DPMS_OFF:
909 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
910 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
911 break;
912 }
913
914 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
915
916 if (rdev->is_atom_bios)
917 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
918 else
919 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
920
921 }
922
radeon_legacy_tmds_ext_prepare(struct drm_encoder * encoder)923 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
924 {
925 struct radeon_device *rdev = encoder->dev->dev_private;
926
927 if (rdev->is_atom_bios)
928 radeon_atom_output_lock(encoder, true);
929 else
930 radeon_combios_output_lock(encoder, true);
931 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
932 }
933
radeon_legacy_tmds_ext_commit(struct drm_encoder * encoder)934 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
935 {
936 struct radeon_device *rdev = encoder->dev->dev_private;
937 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
938
939 if (rdev->is_atom_bios)
940 radeon_atom_output_lock(encoder, false);
941 else
942 radeon_combios_output_lock(encoder, false);
943 }
944
radeon_legacy_tmds_ext_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)945 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
946 struct drm_display_mode *mode,
947 struct drm_display_mode *adjusted_mode)
948 {
949 struct drm_device *dev = encoder->dev;
950 struct radeon_device *rdev = dev->dev_private;
951 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
952 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
953 uint32_t fp2_gen_cntl;
954
955 DRM_DEBUG_KMS("\n");
956
957 if (rdev->is_atom_bios) {
958 radeon_encoder->pixel_clock = adjusted_mode->clock;
959 atombios_dvo_setup(encoder, ATOM_ENABLE);
960 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
961 } else {
962 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
963
964 if (1) /* FIXME rgbBits == 8 */
965 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
966 else
967 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
968
969 fp2_gen_cntl &= ~(RADEON_FP2_ON |
970 RADEON_FP2_DVO_EN |
971 RADEON_FP2_DVO_RATE_SEL_SDR);
972
973 /* XXX: these are oem specific */
974 if (ASIC_IS_R300(rdev)) {
975 if ((dev->pdev->device == 0x4850) &&
976 (dev->pdev->subsystem_vendor == 0x1028) &&
977 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
978 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
979 else
980 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
981
982 /*if (mode->clock > 165000)
983 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
984 }
985 if (!radeon_combios_external_tmds_setup(encoder))
986 radeon_external_tmds_setup(encoder);
987 }
988
989 if (radeon_crtc->crtc_id == 0) {
990 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
991 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
992 if (radeon_encoder->rmx_type != RMX_OFF)
993 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
994 else
995 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
996 } else
997 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
998 } else {
999 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
1000 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
1001 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1002 } else
1003 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
1004 }
1005
1006 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1007
1008 if (rdev->is_atom_bios)
1009 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1010 else
1011 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1012 }
1013
radeon_ext_tmds_enc_destroy(struct drm_encoder * encoder)1014 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
1015 {
1016 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1017 /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
1018 kfree(radeon_encoder->enc_priv);
1019 drm_encoder_cleanup(encoder);
1020 kfree(radeon_encoder);
1021 }
1022
1023 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
1024 .dpms = radeon_legacy_tmds_ext_dpms,
1025 .mode_fixup = radeon_legacy_mode_fixup,
1026 .prepare = radeon_legacy_tmds_ext_prepare,
1027 .mode_set = radeon_legacy_tmds_ext_mode_set,
1028 .commit = radeon_legacy_tmds_ext_commit,
1029 .disable = radeon_legacy_encoder_disable,
1030 };
1031
1032
1033 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1034 .destroy = radeon_ext_tmds_enc_destroy,
1035 };
1036
radeon_legacy_tv_dac_dpms(struct drm_encoder * encoder,int mode)1037 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1038 {
1039 struct drm_device *dev = encoder->dev;
1040 struct radeon_device *rdev = dev->dev_private;
1041 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1042 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1043 uint32_t tv_master_cntl = 0;
1044 bool is_tv;
1045 DRM_DEBUG_KMS("\n");
1046
1047 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1048
1049 if (rdev->family == CHIP_R200)
1050 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1051 else {
1052 if (is_tv)
1053 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1054 else
1055 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1056 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1057 }
1058
1059 switch (mode) {
1060 case DRM_MODE_DPMS_ON:
1061 if (rdev->family == CHIP_R200) {
1062 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1063 } else {
1064 if (is_tv)
1065 tv_master_cntl |= RADEON_TV_ON;
1066 else
1067 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1068
1069 if (rdev->family == CHIP_R420 ||
1070 rdev->family == CHIP_R423 ||
1071 rdev->family == CHIP_RV410)
1072 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1073 R420_TV_DAC_GDACPD |
1074 R420_TV_DAC_BDACPD |
1075 RADEON_TV_DAC_BGSLEEP);
1076 else
1077 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1078 RADEON_TV_DAC_GDACPD |
1079 RADEON_TV_DAC_BDACPD |
1080 RADEON_TV_DAC_BGSLEEP);
1081 }
1082 break;
1083 case DRM_MODE_DPMS_STANDBY:
1084 case DRM_MODE_DPMS_SUSPEND:
1085 case DRM_MODE_DPMS_OFF:
1086 if (rdev->family == CHIP_R200)
1087 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1088 else {
1089 if (is_tv)
1090 tv_master_cntl &= ~RADEON_TV_ON;
1091 else
1092 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1093
1094 if (rdev->family == CHIP_R420 ||
1095 rdev->family == CHIP_R423 ||
1096 rdev->family == CHIP_RV410)
1097 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1098 R420_TV_DAC_GDACPD |
1099 R420_TV_DAC_BDACPD |
1100 RADEON_TV_DAC_BGSLEEP);
1101 else
1102 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1103 RADEON_TV_DAC_GDACPD |
1104 RADEON_TV_DAC_BDACPD |
1105 RADEON_TV_DAC_BGSLEEP);
1106 }
1107 break;
1108 }
1109
1110 if (rdev->family == CHIP_R200) {
1111 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1112 } else {
1113 if (is_tv)
1114 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1115 /* handled in radeon_crtc_dpms() */
1116 else if (!(rdev->flags & RADEON_SINGLE_CRTC))
1117 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1118 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1119 }
1120
1121 if (rdev->is_atom_bios)
1122 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1123 else
1124 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1125
1126 }
1127
radeon_legacy_tv_dac_prepare(struct drm_encoder * encoder)1128 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1129 {
1130 struct radeon_device *rdev = encoder->dev->dev_private;
1131
1132 if (rdev->is_atom_bios)
1133 radeon_atom_output_lock(encoder, true);
1134 else
1135 radeon_combios_output_lock(encoder, true);
1136 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1137 }
1138
radeon_legacy_tv_dac_commit(struct drm_encoder * encoder)1139 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1140 {
1141 struct radeon_device *rdev = encoder->dev->dev_private;
1142
1143 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1144
1145 if (rdev->is_atom_bios)
1146 radeon_atom_output_lock(encoder, true);
1147 else
1148 radeon_combios_output_lock(encoder, true);
1149 }
1150
radeon_legacy_tv_dac_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1151 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1152 struct drm_display_mode *mode,
1153 struct drm_display_mode *adjusted_mode)
1154 {
1155 struct drm_device *dev = encoder->dev;
1156 struct radeon_device *rdev = dev->dev_private;
1157 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1158 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1159 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1160 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1161 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1162 bool is_tv = false;
1163
1164 DRM_DEBUG_KMS("\n");
1165
1166 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1167
1168 if (rdev->family != CHIP_R200) {
1169 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1170 if (rdev->family == CHIP_R420 ||
1171 rdev->family == CHIP_R423 ||
1172 rdev->family == CHIP_RV410) {
1173 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1174 RADEON_TV_DAC_BGADJ_MASK |
1175 R420_TV_DAC_DACADJ_MASK |
1176 R420_TV_DAC_RDACPD |
1177 R420_TV_DAC_GDACPD |
1178 R420_TV_DAC_BDACPD |
1179 R420_TV_DAC_TVENABLE);
1180 } else {
1181 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1182 RADEON_TV_DAC_BGADJ_MASK |
1183 RADEON_TV_DAC_DACADJ_MASK |
1184 RADEON_TV_DAC_RDACPD |
1185 RADEON_TV_DAC_GDACPD |
1186 RADEON_TV_DAC_BDACPD);
1187 }
1188
1189 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1190
1191 if (is_tv) {
1192 if (tv_dac->tv_std == TV_STD_NTSC ||
1193 tv_dac->tv_std == TV_STD_NTSC_J ||
1194 tv_dac->tv_std == TV_STD_PAL_M ||
1195 tv_dac->tv_std == TV_STD_PAL_60)
1196 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1197 else
1198 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1199
1200 if (tv_dac->tv_std == TV_STD_NTSC ||
1201 tv_dac->tv_std == TV_STD_NTSC_J)
1202 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1203 else
1204 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1205 } else
1206 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1207 tv_dac->ps2_tvdac_adj);
1208
1209 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1210 }
1211
1212 if (ASIC_IS_R300(rdev)) {
1213 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1214 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1215 } else if (rdev->family != CHIP_R200)
1216 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1217 else if (rdev->family == CHIP_R200)
1218 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1219
1220 if (rdev->family >= CHIP_R200)
1221 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1222
1223 if (is_tv) {
1224 uint32_t dac_cntl;
1225
1226 dac_cntl = RREG32(RADEON_DAC_CNTL);
1227 dac_cntl &= ~RADEON_DAC_TVO_EN;
1228 WREG32(RADEON_DAC_CNTL, dac_cntl);
1229
1230 if (ASIC_IS_R300(rdev))
1231 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1232
1233 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1234 if (radeon_crtc->crtc_id == 0) {
1235 if (ASIC_IS_R300(rdev)) {
1236 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1237 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1238 RADEON_DISP_TV_SOURCE_CRTC);
1239 }
1240 if (rdev->family >= CHIP_R200) {
1241 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1242 } else {
1243 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1244 }
1245 } else {
1246 if (ASIC_IS_R300(rdev)) {
1247 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1248 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1249 }
1250 if (rdev->family >= CHIP_R200) {
1251 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1252 } else {
1253 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1254 }
1255 }
1256 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1257 } else {
1258
1259 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1260
1261 if (radeon_crtc->crtc_id == 0) {
1262 if (ASIC_IS_R300(rdev)) {
1263 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1264 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1265 } else if (rdev->family == CHIP_R200) {
1266 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1267 RADEON_FP2_DVO_RATE_SEL_SDR);
1268 } else
1269 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1270 } else {
1271 if (ASIC_IS_R300(rdev)) {
1272 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1273 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1274 } else if (rdev->family == CHIP_R200) {
1275 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1276 RADEON_FP2_DVO_RATE_SEL_SDR);
1277 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1278 } else
1279 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1280 }
1281 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1282 }
1283
1284 if (ASIC_IS_R300(rdev)) {
1285 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1286 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1287 } else if (rdev->family != CHIP_R200)
1288 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1289 else if (rdev->family == CHIP_R200)
1290 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1291
1292 if (rdev->family >= CHIP_R200)
1293 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1294
1295 if (is_tv)
1296 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1297
1298 if (rdev->is_atom_bios)
1299 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1300 else
1301 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1302
1303 }
1304
r300_legacy_tv_detect(struct drm_encoder * encoder,struct drm_connector * connector)1305 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1306 struct drm_connector *connector)
1307 {
1308 struct drm_device *dev = encoder->dev;
1309 struct radeon_device *rdev = dev->dev_private;
1310 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1311 uint32_t disp_output_cntl, gpiopad_a, tmp;
1312 bool found = false;
1313
1314 /* save regs needed */
1315 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1316 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1317 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1318 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1319 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1320 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1321
1322 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1323
1324 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1325
1326 WREG32(RADEON_CRTC2_GEN_CNTL,
1327 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1328
1329 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1330 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1331 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1332
1333 WREG32(RADEON_DAC_EXT_CNTL,
1334 RADEON_DAC2_FORCE_BLANK_OFF_EN |
1335 RADEON_DAC2_FORCE_DATA_EN |
1336 RADEON_DAC_FORCE_DATA_SEL_RGB |
1337 (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1338
1339 WREG32(RADEON_TV_DAC_CNTL,
1340 RADEON_TV_DAC_STD_NTSC |
1341 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1342 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1343
1344 RREG32(RADEON_TV_DAC_CNTL);
1345 mdelay(4);
1346
1347 WREG32(RADEON_TV_DAC_CNTL,
1348 RADEON_TV_DAC_NBLANK |
1349 RADEON_TV_DAC_NHOLD |
1350 RADEON_TV_MONITOR_DETECT_EN |
1351 RADEON_TV_DAC_STD_NTSC |
1352 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1353 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1354
1355 RREG32(RADEON_TV_DAC_CNTL);
1356 mdelay(6);
1357
1358 tmp = RREG32(RADEON_TV_DAC_CNTL);
1359 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1360 found = true;
1361 DRM_DEBUG_KMS("S-video TV connection detected\n");
1362 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1363 found = true;
1364 DRM_DEBUG_KMS("Composite TV connection detected\n");
1365 }
1366
1367 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1368 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1369 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1370 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1371 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1372 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1373 return found;
1374 }
1375
radeon_legacy_tv_detect(struct drm_encoder * encoder,struct drm_connector * connector)1376 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1377 struct drm_connector *connector)
1378 {
1379 struct drm_device *dev = encoder->dev;
1380 struct radeon_device *rdev = dev->dev_private;
1381 uint32_t tv_dac_cntl, dac_cntl2;
1382 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1383 bool found = false;
1384
1385 if (ASIC_IS_R300(rdev))
1386 return r300_legacy_tv_detect(encoder, connector);
1387
1388 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1389 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1390 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1391 config_cntl = RREG32(RADEON_CONFIG_CNTL);
1392 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1393
1394 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1395 WREG32(RADEON_DAC_CNTL2, tmp);
1396
1397 tmp = tv_master_cntl | RADEON_TV_ON;
1398 tmp &= ~(RADEON_TV_ASYNC_RST |
1399 RADEON_RESTART_PHASE_FIX |
1400 RADEON_CRT_FIFO_CE_EN |
1401 RADEON_TV_FIFO_CE_EN |
1402 RADEON_RE_SYNC_NOW_SEL_MASK);
1403 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1404 WREG32(RADEON_TV_MASTER_CNTL, tmp);
1405
1406 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1407 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1408 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1409
1410 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1411 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1412 else
1413 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1414 WREG32(RADEON_TV_DAC_CNTL, tmp);
1415
1416 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1417 RADEON_RED_MX_FORCE_DAC_DATA |
1418 RADEON_GRN_MX_FORCE_DAC_DATA |
1419 RADEON_BLU_MX_FORCE_DAC_DATA |
1420 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1421 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1422
1423 mdelay(3);
1424 tmp = RREG32(RADEON_TV_DAC_CNTL);
1425 if (tmp & RADEON_TV_DAC_GDACDET) {
1426 found = true;
1427 DRM_DEBUG_KMS("S-video TV connection detected\n");
1428 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1429 found = true;
1430 DRM_DEBUG_KMS("Composite TV connection detected\n");
1431 }
1432
1433 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1434 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1435 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1436 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1437 return found;
1438 }
1439
radeon_legacy_ext_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)1440 static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
1441 struct drm_connector *connector)
1442 {
1443 struct drm_device *dev = encoder->dev;
1444 struct radeon_device *rdev = dev->dev_private;
1445 uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
1446 uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
1447 uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
1448 uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
1449 uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
1450 bool found = false;
1451 int i;
1452
1453 /* save the regs we need */
1454 gpio_monid = RREG32(RADEON_GPIO_MONID);
1455 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1456 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1457 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1458 disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
1459 disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
1460 disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
1461 disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
1462 disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
1463 disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
1464 crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
1465 crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
1466 crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
1467 crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
1468
1469 tmp = RREG32(RADEON_GPIO_MONID);
1470 tmp &= ~RADEON_GPIO_A_0;
1471 WREG32(RADEON_GPIO_MONID, tmp);
1472
1473 WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |
1474 RADEON_FP2_PANEL_FORMAT |
1475 R200_FP2_SOURCE_SEL_TRANS_UNIT |
1476 RADEON_FP2_DVO_EN |
1477 R200_FP2_DVO_RATE_SEL_SDR));
1478
1479 WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |
1480 RADEON_DISP_TRANS_MATRIX_GRAPHICS));
1481
1482 WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |
1483 RADEON_CRTC2_DISP_REQ_EN_B));
1484
1485 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
1486 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
1487 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
1488 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
1489 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
1490 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
1491
1492 WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
1493 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
1494 WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
1495 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
1496
1497 for (i = 0; i < 200; i++) {
1498 tmp = RREG32(RADEON_GPIO_MONID);
1499 if (tmp & RADEON_GPIO_Y_0)
1500 found = true;
1501
1502 if (found)
1503 break;
1504
1505 mdelay(1);
1506 if (!drm_can_sleep())
1507 mdelay(1);
1508 else
1509 msleep(1);
1510 }
1511
1512 /* restore the regs we used */
1513 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
1514 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
1515 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
1516 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
1517 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
1518 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
1519 WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
1520 WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
1521 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
1522 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
1523 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1524 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1525 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1526 WREG32(RADEON_GPIO_MONID, gpio_monid);
1527
1528 return found;
1529 }
1530
radeon_legacy_tv_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)1531 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1532 struct drm_connector *connector)
1533 {
1534 struct drm_device *dev = encoder->dev;
1535 struct radeon_device *rdev = dev->dev_private;
1536 uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1537 uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
1538 uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;
1539 enum drm_connector_status found = connector_status_disconnected;
1540 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1541 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1542 bool color = true;
1543 struct drm_crtc *crtc;
1544
1545 /* find out if crtc2 is in use or if this encoder is using it */
1546 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1547 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1548 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1549 if (encoder->crtc != crtc) {
1550 return connector_status_disconnected;
1551 }
1552 }
1553 }
1554
1555 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1556 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1557 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1558 bool tv_detect;
1559
1560 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1561 return connector_status_disconnected;
1562
1563 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1564 if (tv_detect && tv_dac)
1565 found = connector_status_connected;
1566 return found;
1567 }
1568
1569 /* don't probe if the encoder is being used for something else not CRT related */
1570 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1571 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1572 return connector_status_disconnected;
1573 }
1574
1575 /* R200 uses an external DAC for secondary DAC */
1576 if (rdev->family == CHIP_R200) {
1577 if (radeon_legacy_ext_dac_detect(encoder, connector))
1578 found = connector_status_connected;
1579 return found;
1580 }
1581
1582 /* save the regs we need */
1583 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1584
1585 if (rdev->flags & RADEON_SINGLE_CRTC) {
1586 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
1587 } else {
1588 if (ASIC_IS_R300(rdev)) {
1589 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1590 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1591 } else {
1592 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1593 }
1594 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1595 }
1596 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1597 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1598 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1599
1600 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1601 | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1602 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1603
1604 if (rdev->flags & RADEON_SINGLE_CRTC) {
1605 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
1606 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
1607 } else {
1608 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1609 tmp |= RADEON_CRTC2_CRT2_ON |
1610 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1611 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1612
1613 if (ASIC_IS_R300(rdev)) {
1614 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1615 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1616 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1617 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1618 } else {
1619 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1620 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1621 }
1622 }
1623
1624 tmp = RADEON_TV_DAC_NBLANK |
1625 RADEON_TV_DAC_NHOLD |
1626 RADEON_TV_MONITOR_DETECT_EN |
1627 RADEON_TV_DAC_STD_PS2;
1628
1629 WREG32(RADEON_TV_DAC_CNTL, tmp);
1630
1631 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1632 RADEON_DAC2_FORCE_DATA_EN;
1633
1634 if (color)
1635 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1636 else
1637 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1638
1639 if (ASIC_IS_R300(rdev))
1640 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1641 else
1642 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1643
1644 WREG32(RADEON_DAC_EXT_CNTL, tmp);
1645
1646 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1647 WREG32(RADEON_DAC_CNTL2, tmp);
1648
1649 mdelay(10);
1650
1651 if (ASIC_IS_R300(rdev)) {
1652 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1653 found = connector_status_connected;
1654 } else {
1655 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1656 found = connector_status_connected;
1657 }
1658
1659 /* restore regs we used */
1660 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1661 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1662 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1663
1664 if (rdev->flags & RADEON_SINGLE_CRTC) {
1665 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
1666 } else {
1667 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1668 if (ASIC_IS_R300(rdev)) {
1669 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1670 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1671 } else {
1672 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1673 }
1674 }
1675
1676 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1677
1678 return found;
1679
1680 }
1681
1682 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1683 .dpms = radeon_legacy_tv_dac_dpms,
1684 .mode_fixup = radeon_legacy_mode_fixup,
1685 .prepare = radeon_legacy_tv_dac_prepare,
1686 .mode_set = radeon_legacy_tv_dac_mode_set,
1687 .commit = radeon_legacy_tv_dac_commit,
1688 .detect = radeon_legacy_tv_dac_detect,
1689 .disable = radeon_legacy_encoder_disable,
1690 };
1691
1692
1693 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1694 .destroy = radeon_enc_destroy,
1695 };
1696
1697
radeon_legacy_get_tmds_info(struct radeon_encoder * encoder)1698 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1699 {
1700 struct drm_device *dev = encoder->base.dev;
1701 struct radeon_device *rdev = dev->dev_private;
1702 struct radeon_encoder_int_tmds *tmds = NULL;
1703 bool ret;
1704
1705 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1706
1707 if (!tmds)
1708 return NULL;
1709
1710 if (rdev->is_atom_bios)
1711 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1712 else
1713 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1714
1715 if (ret == false)
1716 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1717
1718 return tmds;
1719 }
1720
radeon_legacy_get_ext_tmds_info(struct radeon_encoder * encoder)1721 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1722 {
1723 struct drm_device *dev = encoder->base.dev;
1724 struct radeon_device *rdev = dev->dev_private;
1725 struct radeon_encoder_ext_tmds *tmds = NULL;
1726 bool ret;
1727
1728 if (rdev->is_atom_bios)
1729 return NULL;
1730
1731 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1732
1733 if (!tmds)
1734 return NULL;
1735
1736 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1737
1738 if (ret == false)
1739 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1740
1741 return tmds;
1742 }
1743
1744 void
radeon_add_legacy_encoder(struct drm_device * dev,uint32_t encoder_enum,uint32_t supported_device)1745 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1746 {
1747 struct radeon_device *rdev = dev->dev_private;
1748 struct drm_encoder *encoder;
1749 struct radeon_encoder *radeon_encoder;
1750
1751 /* see if we already added it */
1752 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1753 radeon_encoder = to_radeon_encoder(encoder);
1754 if (radeon_encoder->encoder_enum == encoder_enum) {
1755 radeon_encoder->devices |= supported_device;
1756 return;
1757 }
1758
1759 }
1760
1761 /* add a new one */
1762 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1763 if (!radeon_encoder)
1764 return;
1765
1766 encoder = &radeon_encoder->base;
1767 if (rdev->flags & RADEON_SINGLE_CRTC)
1768 encoder->possible_crtcs = 0x1;
1769 else
1770 encoder->possible_crtcs = 0x3;
1771
1772 radeon_encoder->enc_priv = NULL;
1773
1774 radeon_encoder->encoder_enum = encoder_enum;
1775 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1776 radeon_encoder->devices = supported_device;
1777 radeon_encoder->rmx_type = RMX_OFF;
1778
1779 switch (radeon_encoder->encoder_id) {
1780 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1781 encoder->possible_crtcs = 0x1;
1782 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
1783 DRM_MODE_ENCODER_LVDS, NULL);
1784 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1785 if (rdev->is_atom_bios)
1786 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1787 else
1788 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1789 radeon_encoder->rmx_type = RMX_FULL;
1790 break;
1791 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1792 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs,
1793 DRM_MODE_ENCODER_TMDS, NULL);
1794 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1795 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1796 break;
1797 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1798 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs,
1799 DRM_MODE_ENCODER_DAC, NULL);
1800 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1801 if (rdev->is_atom_bios)
1802 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1803 else
1804 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1805 break;
1806 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1807 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs,
1808 DRM_MODE_ENCODER_TVDAC, NULL);
1809 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1810 if (rdev->is_atom_bios)
1811 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1812 else
1813 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1814 break;
1815 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1816 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs,
1817 DRM_MODE_ENCODER_TMDS, NULL);
1818 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1819 if (!rdev->is_atom_bios)
1820 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1821 break;
1822 }
1823 }
1824