1 /* $NetBSD: s3c2800.c,v 1.16 2021/08/07 16:18:45 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2002, 2003 Fujitsu Component Limited
5 * Copyright (c) 2002, 2003 Genetec Corporation
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of The Fujitsu Component Limited nor the name of
17 * Genetec corporation may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0, "$NetBSD: s3c2800.c,v 1.16 2021/08/07 16:18:45 thorpej Exp $");
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/device.h>
41 #include <sys/kernel.h>
42 #include <sys/reboot.h>
43
44 #include <machine/cpu.h>
45 #include <sys/bus.h>
46
47 #include <arm/cpufunc.h>
48 #include <arm/mainbus/mainbus.h>
49 #include <arm/s3c2xx0/s3c2800reg.h>
50 #include <arm/s3c2xx0/s3c2800var.h>
51
52 #include "locators.h"
53 #include "opt_cpuoptions.h"
54
55 /* prototypes */
56 static int s3c2800_match(device_t, cfdata_t, void *);
57 static void s3c2800_attach(device_t, device_t, void *);
58 static int s3c2800_search(device_t, cfdata_t, const int *, void *);
59
60 /* attach structures */
61 CFATTACH_DECL_NEW(ssio, sizeof(struct s3c2800_softc), s3c2800_match, s3c2800_attach,
62 NULL, NULL);
63
64 extern struct bus_space s3c2xx0_bs_tag;
65
66 struct s3c2xx0_softc *s3c2xx0_softc;
67
68 static int
s3c2800_print(void * aux,const char * name)69 s3c2800_print(void *aux, const char *name)
70 {
71 struct s3c2xx0_attach_args *sa = (struct s3c2xx0_attach_args *) aux;
72
73 if (sa->sa_size)
74 aprint_normal(" addr 0x%lx", sa->sa_addr);
75 if (sa->sa_size > 1)
76 aprint_normal("-0x%lx", sa->sa_addr + sa->sa_size - 1);
77 if (sa->sa_intr != SSIOCF_INTR_DEFAULT)
78 aprint_normal(" intr %d", sa->sa_intr);
79 if (sa->sa_index != SSIOCF_INDEX_DEFAULT)
80 aprint_normal(" unit %d", sa->sa_index);
81
82 return (UNCONF);
83 }
84
85 int
s3c2800_match(device_t parent,cfdata_t match,void * aux)86 s3c2800_match(device_t parent, cfdata_t match, void *aux)
87 {
88 return 1;
89 }
90
91 void
s3c2800_attach(device_t parent,device_t self,void * aux)92 s3c2800_attach(device_t parent, device_t self, void *aux)
93 {
94 struct s3c2800_softc *sc = device_private(self);
95 bus_space_tag_t iot;
96 const char *which_registers; /* for panic message */
97
98 #define FAIL(which) do { \
99 which_registers=(which); goto abort; }while(/*CONSTCOND*/0)
100
101 s3c2xx0_softc = &(sc->sc_sx);
102 sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag;
103
104 if (bus_space_map(iot,
105 S3C2800_INTCTL_BASE, S3C2800_INTCTL_SIZE,
106 BUS_SPACE_MAP_LINEAR, &sc->sc_sx.sc_intctl_ioh))
107 FAIL("intc");
108 /* tell register addresses to interrupt handler */
109 s3c2800_intr_init(sc);
110
111 /* Map the GPIO registers */
112 if (bus_space_map(iot, S3C2800_GPIO_BASE, S3C2800_GPIO_SIZE,
113 0, &sc->sc_sx.sc_gpio_ioh))
114 FAIL("GPIO");
115
116 #if 0
117 /* Map the DMA controller registers */
118 if (bus_space_map(iot, S3C2800_DMAC_BASE, S3C2800_DMAC_SIZE,
119 0, &sc->sc_sx.sc_dmach))
120 FAIL("DMAC");
121 #endif
122
123 /* Memory controller */
124 if (bus_space_map(iot, S3C2800_MEMCTL_BASE,
125 S3C2800_MEMCTL_SIZE, 0, &sc->sc_sx.sc_memctl_ioh))
126 FAIL("MEMC");
127 /* Clock manager */
128 if (bus_space_map(iot, S3C2800_CLKMAN_BASE,
129 S3C2800_CLKMAN_SIZE, 0, &sc->sc_sx.sc_clkman_ioh))
130 FAIL("CLK");
131
132 #if 0
133 /* Real time clock */
134 if (bus_space_map(iot, S3C2800_RTC_BASE,
135 S3C2800_RTC_SIZE, 0, &sc->sc_sx.sc_rtc_ioh))
136 FAIL("RTC");
137 #endif
138
139 if (bus_space_map(iot, S3C2800_TIMER0_BASE,
140 S3C2800_TIMER_SIZE, 0, &sc->sc_tmr0_ioh))
141 FAIL("TIMER0");
142
143 if (bus_space_map(iot, S3C2800_TIMER1_BASE,
144 S3C2800_TIMER_SIZE, 0, &sc->sc_tmr1_ioh))
145 FAIL("TIMER1");
146
147 /* calculate current clock frequency */
148 s3c2800_clock_freq(&sc->sc_sx);
149 aprint_normal(": fclk %d MHz hclk %d MHz pclk %d MHz\n",
150 sc->sc_sx.sc_fclk / 1000000, sc->sc_sx.sc_hclk / 1000000,
151 sc->sc_sx.sc_pclk / 1000000);
152 aprint_naive("\n");
153
154 /*
155 * Attach devices.
156 */
157 config_search(self, NULL,
158 CFARGS(.search = s3c2800_search));
159 return;
160
161 abort:
162 panic("%s: unable to map %s registers",
163 device_xname(self), which_registers);
164
165 #undef FAIL
166 }
167
168 int
s3c2800_search(device_t parent,cfdata_t cf,const int * ldesc,void * aux)169 s3c2800_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
170 {
171 struct s3c2800_softc *sc = device_private(parent);
172 struct s3c2xx0_attach_args aa;
173
174 aa.sa_sc = sc;
175 aa.sa_iot = sc->sc_sx.sc_iot;
176 aa.sa_addr = cf->cf_loc[SSIOCF_ADDR];
177 aa.sa_size = cf->cf_loc[SSIOCF_SIZE];
178 aa.sa_index = cf->cf_loc[SSIOCF_INDEX];
179 aa.sa_intr = cf->cf_loc[SSIOCF_INTR];
180
181 if (config_probe(parent, cf, &aa))
182 config_attach(parent, cf, &aa, s3c2800_print, CFARGS_NONE);
183
184 return 0;
185 }
186
187 /*
188 * Issue software reset command.
189 * called with MMU off.
190 */
191 void
s3c2800_softreset(void)192 s3c2800_softreset(void)
193 {
194 *(volatile unsigned int *)(S3C2800_CLKMAN_BASE + CLKMAN_SWRCON)
195 = SWRCON_SWR;
196 }
197
198 /*
199 * fill sc_pclk, sc_hclk, sc_fclk from values of clock controller register.
200 *
201 * s3c2800_clock_freq2() is meant to be called from kernel startup routines.
202 * s3c2800_clock_freq() is for after kernel initialization is done.
203 */
204 void
s3c2800_clock_freq2(vaddr_t clkman_base,int * fclk,int * hclk,int * pclk)205 s3c2800_clock_freq2(vaddr_t clkman_base, int *fclk, int *hclk, int *pclk)
206 {
207 uint32_t pllcon, clkcon;
208 int mdiv, pdiv, sdiv;
209 int f, h, p;
210
211 pllcon = *(volatile uint32_t *)(clkman_base + CLKMAN_PLLCON);
212 clkcon = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKCON);
213
214 mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT;
215 pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT;
216 sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT;
217
218 f = ((mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv));
219 h = f;
220 if (clkcon & CLKCON_HCLK)
221 h /= 2;
222 p = h;
223 if (clkcon & CLKCON_PCLK)
224 p /= 2;
225
226 if (fclk) *fclk = f;
227 if (hclk) *hclk = h;
228 if (pclk) *pclk = p;
229 }
230
231 void
s3c2800_clock_freq(struct s3c2xx0_softc * sc)232 s3c2800_clock_freq(struct s3c2xx0_softc *sc)
233 {
234 s3c2800_clock_freq2(
235 (vaddr_t)bus_space_vaddr(sc->sc_iot, sc->sc_clkman_ioh),
236 &sc->sc_fclk, &sc->sc_hclk, &sc->sc_pclk);
237 }
238
239