1entity e is 2 port ( 3 p : in bit ); 4end entity; 5 6architecture a of e is 7 signal v : bit_vector(1 to 3); 8 signal x, y, z : bit; 9begin 10 11 process is 12 begin 13 (x, y, z) <= v; -- OK 14 (x, y, z) <= x; -- Error 15 (x, y, z) <= "101"; -- Error 16 ('1', y, z) <= v; -- Error 17 (others => x) <= v; -- Error 18 (p, y, z) <= v; -- Error 19 end process; 20 21 (x, y, z) <= v; -- OK 22 (x, y, z) <= x; -- Error 23 ('1', y, z) <= v; -- Error 24 (others => x) <= v; -- Error 25 (p, y, z) <= v; -- Error 26 27 process is 28 variable i : integer; 29 begin 30 (v(i), v(1), v(2)) <= v; -- Error 31 end process; 32 33end architecture; 34