xref: /openbsd/sys/arch/sh/include/trap.h (revision 2fa72412)
1 /*	$OpenBSD: trap.h,v 1.4 2011/03/23 16:54:37 pirofti Exp $	*/
2 /*	$NetBSD: exception.h,v 1.9 2006/07/22 21:58:29 uwe Exp $	*/
3 
4 /*-
5  * Copyright (c) 2002 The NetBSD Foundation, Inc.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27  * POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #ifndef _SH_TRAP_H_
31 #define	_SH_TRAP_H_
32 /*
33  * SH3/SH4 Exception handling.
34  */
35 #include <sh/devreg.h>
36 
37 #ifdef _KERNEL
38 #define	SH3_TRA			0xffffffd0	/* 32bit */
39 #define	SH3_EXPEVT		0xffffffd4	/* 32bit */
40 #define	SH3_INTEVT		0xffffffd8	/* 32bit */
41 #define	SH7709_INTEVT2		0xa4000000	/* 32bit */
42 
43 #define	SH4_TRA			0xff000020	/* 32bit */
44 #define	SH4_EXPEVT		0xff000024	/* 32bit */
45 #define	SH4_INTEVT		0xff000028	/* 32bit */
46 
47 /*
48  * EXPEVT
49  */
50 /* Reset exception */
51 #define	EXPEVT_RESET_POWER	0x000	/* Power-On reset */
52 #define	EXPEVT_RESET_MANUAL	0x020	/* Manual reset */
53 #define	EXPEVT_RESET_TLB_MULTI_HIT	0x140	/* SH4 only */
54 
55 /* General exception */
56 #define	EXPEVT_TLB_MISS_LD	0x040	/* TLB miss (load) */
57 #define	EXPEVT_TLB_MISS_ST	0x060	/* TLB miss (store) */
58 #define	EXPEVT_TLB_MOD		0x080	/* Initial page write */
59 #define	EXPEVT_TLB_PROT_LD	0x0a0	/* Protection violation (load) */
60 #define	EXPEVT_TLB_PROT_ST	0x0c0	/* Protection violation (store)*/
61 #define	EXPEVT_ADDR_ERR_LD	0x0e0	/* Address error (load) */
62 #define	EXPEVT_ADDR_ERR_ST	0x100	/* Address error (store) */
63 #define	EXPEVT_FPU		0x120	/* FPU exception */
64 #define	EXPEVT_TRAPA		0x160	/* Unconditional trap (TRAPA) */
65 #define	EXPEVT_RES_INST		0x180	/* Illegal instruction */
66 #define	EXPEVT_SLOT_INST	0x1a0	/* Illegal slot instruction */
67 #define	EXPEVT_BREAK		0x1e0	/* User break */
68 #define	EXPEVT_FPU_DISABLE	0x800	/* FPU disabled */
69 #define	EXPEVT_FPU_SLOT_DISABLE	0x820	/* Slot FPU disabled */
70 
71 /* Software bit */
72 #define	EXP_USER		0x001	/* exception from user-mode */
73 
74 #define	_SH_TRA_SYSCALL		0x80	/* syscall trapa number */
75 #define	_SH_TRA_CACHECTL	0x81	/* cachectl trapa number */
76 #define	_SH_TRA_BREAK		0xc3	/* magic number for debugger */
77 
78 /*
79  * INTEVT/INTEVT2
80  */
81 /* External interrupt */
82 #define	SH_INTEVT_NMI		0x1c0
83 
84 #define	SH_INTEVT_TMU0_TUNI0	0x400
85 #define	SH_INTEVT_TMU1_TUNI1	0x420
86 #define	SH_INTEVT_TMU2_TUNI2	0x440
87 #define	SH_INTEVT_TMU2_TICPI2	0x460
88 
89 #define	SH_INTEVT_SCI_ERI	0x4e0
90 #define	SH_INTEVT_SCI_RXI	0x500
91 #define	SH_INTEVT_SCI_TXI	0x520
92 #define	SH_INTEVT_SCI_TEI	0x540
93 
94 #define	SH_INTEVT_WDT_ITI	0x560
95 
96 #define	SH_INTEVT_IRL9		0x320
97 #define	SH_INTEVT_IRL11		0x360
98 #define	SH_INTEVT_IRL13		0x3a0
99 
100 #define	SH4_INTEVT_SCIF_ERI	0x700
101 #define	SH4_INTEVT_SCIF_RXI	0x720
102 #define	SH4_INTEVT_SCIF_BRI	0x740
103 #define	SH4_INTEVT_SCIF_TXI	0x760
104 
105 #define	SH7709_INTEVT2_IRQ0	0x600
106 #define	SH7709_INTEVT2_IRQ1	0x620
107 #define	SH7709_INTEVT2_IRQ2	0x640
108 #define	SH7709_INTEVT2_IRQ3	0x660
109 #define	SH7709_INTEVT2_IRQ4	0x680
110 #define	SH7709_INTEVT2_IRQ5	0x6a0
111 
112 #define	SH7709_INTEVT2_PINT07	0x700
113 #define	SH7709_INTEVT2_PINT8F	0x720
114 
115 #define SH7709_INTEVT2_DEI0	0x800
116 #define SH7709_INTEVT2_DEI1	0x820
117 #define SH7709_INTEVT2_DEI2	0x840
118 #define SH7709_INTEVT2_DEI3	0x860
119 
120 #define	SH7709_INTEVT2_IRDA_ERI	0x880
121 #define	SH7709_INTEVT2_IRDA_RXI	0x8a0
122 #define	SH7709_INTEVT2_IRDA_BRI	0x8c0
123 #define	SH7709_INTEVT2_IRDA_TXI	0x8e0
124 
125 #define	SH7709_INTEVT2_SCIF_ERI	0x900
126 #define	SH7709_INTEVT2_SCIF_RXI	0x920
127 #define	SH7709_INTEVT2_SCIF_BRI	0x940
128 #define	SH7709_INTEVT2_SCIF_TXI	0x960
129 
130 #define	SH7709_INTEVT2_ADC	0x980
131 
132 /* SH7750R, SH7751, SH7751R */
133 #define	SH4_INTEVT_IRL0		0x240
134 #define	SH4_INTEVT_IRL1		0x2a0
135 #define	SH4_INTEVT_IRL2		0x300
136 #define	SH4_INTEVT_IRL3		0x360
137 
138 #define	SH4_INTEVT_IRQ0		0x200
139 #define	SH4_INTEVT_IRQ1		0x220
140 #define	SH4_INTEVT_IRQ2		0x240
141 #define	SH4_INTEVT_IRQ3		0x260
142 #define	SH4_INTEVT_IRQ4		0x280
143 #define	SH4_INTEVT_IRQ5		0x2a0
144 #define	SH4_INTEVT_IRQ6		0x2c0
145 #define	SH4_INTEVT_IRQ7		0x2e0
146 #define	SH4_INTEVT_IRQ8		0x300
147 #define	SH4_INTEVT_IRQ9		0x320
148 #define	SH4_INTEVT_IRQ10	0x340
149 #define	SH4_INTEVT_IRQ11	0x360
150 #define	SH4_INTEVT_IRQ12	0x380
151 #define	SH4_INTEVT_IRQ13	0x3a0
152 #define	SH4_INTEVT_IRQ14	0x3c0
153 #define	SH4_INTEVT_IRQ15	0x3e0
154 
155 #define	SH4_INTEVT_TMU3		0xb00
156 #define	SH4_INTEVT_TMU4		0xb80
157 
158 #define	SH4_INTEVT_PCISERR	0xa00
159 #define	SH4_INTEVT_PCIERR	0xae0
160 #define	SH4_INTEVT_PCIPWDWN	0xac0
161 #define	SH4_INTEVT_PCIPWON	0xaa0
162 #define	SH4_INTEVT_PCIDMA0	0xa80
163 #define	SH4_INTEVT_PCIDMA1	0xa60
164 #define	SH4_INTEVT_PCIDMA2	0xa40
165 #define	SH4_INTEVT_PCIDMA3	0xa20
166 
167 #ifndef _LOCORE
168 
169 #if defined(SH3) && defined(SH4)
170 extern uint32_t __sh_TRA;
171 extern uint32_t __sh_EXPEVT;
172 extern uint32_t __sh_INTEVT;
173 #endif /* SH3 && SH4 */
174 
175 extern const char * const exp_type[];
176 extern const int exp_types;
177 
178 #endif /* !_LOCORE */
179 
180 #endif /* _KERNEL */
181 #endif /* !_SH_TRAP_H_ */
182