1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16 #ifndef _SH_CSS_INTERNAL_H_
17 #define _SH_CSS_INTERNAL_H_
18
19 #include <linux/build_bug.h>
20 #include <linux/stdarg.h>
21
22 #include <system_global.h>
23 #include <math_support.h>
24 #include <type_support.h>
25 #include <platform_support.h>
26
27 #include "input_formatter.h"
28 #include "input_system.h"
29
30 #include "ia_css_types.h"
31 #include "ia_css_acc_types.h"
32 #include "ia_css_buffer.h"
33
34 #include "ia_css_binary.h"
35 #include "sh_css_firmware.h" /* not needed/desired on SP/ISP */
36 #include "sh_css_legacy.h"
37 #include "sh_css_defs.h"
38 #include "sh_css_uds.h"
39 #include "dma.h" /* N_DMA_CHANNEL_ID */
40 #include "ia_css_circbuf_comm.h" /* Circular buffer */
41 #include "ia_css_frame_comm.h"
42 #include "ia_css_3a.h"
43 #include "ia_css_dvs.h"
44 #include "ia_css_metadata.h"
45 #include "runtime/bufq/interface/ia_css_bufq.h"
46 #include "ia_css_timer.h"
47
48 /* TODO: Move to a more suitable place when sp pipeline design is done. */
49 #define IA_CSS_NUM_CB_SEM_READ_RESOURCE 2
50 #define IA_CSS_NUM_CB_SEM_WRITE_RESOURCE 1
51 #define IA_CSS_NUM_CBS 2
52 #define IA_CSS_CB_MAX_ELEMS 2
53
54 /* Use case specific. index limited to IA_CSS_NUM_CB_SEM_READ_RESOURCE or
55 * IA_CSS_NUM_CB_SEM_WRITE_RESOURCE for read and write respectively.
56 * TODO: Enforce the limitation above.
57 */
58 #define IA_CSS_COPYSINK_SEM_INDEX 0
59 #define IA_CSS_TAGGER_SEM_INDEX 1
60
61 /* Force generation of output event. Used by acceleration pipe. */
62 #define IA_CSS_POST_OUT_EVENT_FORCE 2
63
64 #define SH_CSS_MAX_BINARY_NAME 64
65
66 #define SP_DEBUG_NONE (0)
67 #define SP_DEBUG_DUMP (1)
68 #define SP_DEBUG_COPY (2)
69 #define SP_DEBUG_TRACE (3)
70 #define SP_DEBUG_MINIMAL (4)
71
72 #define SP_DEBUG SP_DEBUG_NONE
73 #define SP_DEBUG_MINIMAL_OVERWRITE 1
74
75 #define SH_CSS_TNR_BIT_DEPTH 8
76 #define SH_CSS_REF_BIT_DEPTH 8
77
78 /* keep next up to date with the definition for MAX_CB_ELEMS_FOR_TAGGER in tagger.sp.c */
79 #define NUM_CONTINUOUS_FRAMES 15
80 #define NUM_MIPI_FRAMES_PER_STREAM 2
81
82 #define NUM_ONLINE_INIT_CONTINUOUS_FRAMES 2
83
84 #define NR_OF_PIPELINES IA_CSS_PIPE_ID_NUM /* Must match with IA_CSS_PIPE_ID_NUM */
85
86 #define SH_CSS_MAX_IF_CONFIGS 3 /* Must match with IA_CSS_NR_OF_CONFIGS (not defined yet).*/
87 #define SH_CSS_IF_CONFIG_NOT_NEEDED 0xFF
88
89 #define SH_CSS_MAX_SP_THREADS 5
90
91 /**
92 * The C99 standard does not specify the exact object representation of structs;
93 * the representation is compiler dependent.
94 *
95 * The structs that are communicated between host and SP/ISP should have the
96 * exact same object representation. The compiler that is used to compile the
97 * firmware is hivecc.
98 *
99 * To check if a different compiler, used to compile a host application, uses
100 * another object representation, macros are defined specifying the size of
101 * the structs as expected by the firmware.
102 *
103 * A host application shall verify that a sizeof( ) of the struct is equal to
104 * the SIZE_OF_XXX macro of the corresponding struct. If they are not
105 * equal, functionality will break.
106 */
107 #define CALC_ALIGNMENT_MEMBER(x, y) (CEIL_MUL(x, y) - x)
108 #define SIZE_OF_HRT_VADDRESS sizeof(hive_uint32)
109
110 /* Number of SP's */
111 #define NUM_OF_SPS 1
112
113 #define NUM_OF_BLS 0
114
115 /* Enum for order of Binaries */
116 enum sh_css_order_binaries {
117 SP_FIRMWARE = 0,
118 ISP_FIRMWARE
119 };
120
121 /*
122 * JB: keep next enum in sync with thread id's
123 * and pipe id's
124 */
125 enum sh_css_pipe_config_override {
126 SH_CSS_PIPE_CONFIG_OVRD_NONE = 0,
127 SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD = 0xffff
128 };
129
130 enum host2sp_commands {
131 host2sp_cmd_error = 0,
132 /*
133 * The host2sp_cmd_ready command is the only command written by the SP
134 * It acknowledges that is previous command has been received.
135 * (this does not mean that the command has been executed)
136 * It also indicates that a new command can be send (it is a queue
137 * with depth 1).
138 */
139 host2sp_cmd_ready = 1,
140 /* Command written by the Host */
141 host2sp_cmd_dummy, /* No action, can be used as watchdog */
142 host2sp_cmd_start_flash, /* Request SP to start the flash */
143 host2sp_cmd_terminate, /* SP should terminate itself */
144 N_host2sp_cmd
145 };
146
147 /* Enumeration used to indicate the events that are produced by
148 * the SP and consumed by the Host.
149 *
150 * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC:
151 * 1) "enum ia_css_event_type" (ia_css_event_public.h)
152 * 2) "enum sh_css_sp_event_type" (sh_css_internal.h)
153 * 3) "enum ia_css_event_type event_id_2_event_mask" (event_handler.sp.c)
154 * 4) "enum ia_css_event_type convert_event_sp_to_host_domain" (sh_css.c)
155 */
156 enum sh_css_sp_event_type {
157 SH_CSS_SP_EVENT_OUTPUT_FRAME_DONE,
158 SH_CSS_SP_EVENT_SECOND_OUTPUT_FRAME_DONE,
159 SH_CSS_SP_EVENT_VF_OUTPUT_FRAME_DONE,
160 SH_CSS_SP_EVENT_SECOND_VF_OUTPUT_FRAME_DONE,
161 SH_CSS_SP_EVENT_3A_STATISTICS_DONE,
162 SH_CSS_SP_EVENT_DIS_STATISTICS_DONE,
163 SH_CSS_SP_EVENT_PIPELINE_DONE,
164 SH_CSS_SP_EVENT_FRAME_TAGGED,
165 SH_CSS_SP_EVENT_INPUT_FRAME_DONE,
166 SH_CSS_SP_EVENT_METADATA_DONE,
167 SH_CSS_SP_EVENT_LACE_STATISTICS_DONE,
168 SH_CSS_SP_EVENT_ACC_STAGE_COMPLETE,
169 SH_CSS_SP_EVENT_TIMER,
170 SH_CSS_SP_EVENT_PORT_EOF,
171 SH_CSS_SP_EVENT_FW_WARNING,
172 SH_CSS_SP_EVENT_FW_ASSERT,
173 SH_CSS_SP_EVENT_NR_OF_TYPES /* must be last */
174 };
175
176 /* xmem address map allocation per pipeline, css pointers */
177 /* Note that the struct below should only consist of ia_css_ptr-es
178 Otherwise this will cause a fail in the function ref_sh_css_ddr_address_map
179 */
180 struct sh_css_ddr_address_map {
181 ia_css_ptr isp_param;
182 ia_css_ptr isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES];
183 ia_css_ptr macc_tbl;
184 ia_css_ptr fpn_tbl;
185 ia_css_ptr sc_tbl;
186 ia_css_ptr tetra_r_x;
187 ia_css_ptr tetra_r_y;
188 ia_css_ptr tetra_gr_x;
189 ia_css_ptr tetra_gr_y;
190 ia_css_ptr tetra_gb_x;
191 ia_css_ptr tetra_gb_y;
192 ia_css_ptr tetra_b_x;
193 ia_css_ptr tetra_b_y;
194 ia_css_ptr tetra_ratb_x;
195 ia_css_ptr tetra_ratb_y;
196 ia_css_ptr tetra_batr_x;
197 ia_css_ptr tetra_batr_y;
198 ia_css_ptr dvs_6axis_params_y;
199 };
200
201 #define SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT \
202 (SIZE_OF_HRT_VADDRESS + \
203 (SH_CSS_MAX_STAGES * IA_CSS_NUM_MEMORIES * SIZE_OF_HRT_VADDRESS) + \
204 (16 * SIZE_OF_HRT_VADDRESS))
205
206 static_assert(sizeof(struct sh_css_ddr_address_map) == SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT);
207
208 /* xmem address map allocation per pipeline */
209 struct sh_css_ddr_address_map_size {
210 size_t isp_param;
211 size_t isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES];
212 size_t macc_tbl;
213 size_t fpn_tbl;
214 size_t sc_tbl;
215 size_t tetra_r_x;
216 size_t tetra_r_y;
217 size_t tetra_gr_x;
218 size_t tetra_gr_y;
219 size_t tetra_gb_x;
220 size_t tetra_gb_y;
221 size_t tetra_b_x;
222 size_t tetra_b_y;
223 size_t tetra_ratb_x;
224 size_t tetra_ratb_y;
225 size_t tetra_batr_x;
226 size_t tetra_batr_y;
227 size_t dvs_6axis_params_y;
228 };
229
230 struct sh_css_ddr_address_map_compound {
231 struct sh_css_ddr_address_map map;
232 struct sh_css_ddr_address_map_size size;
233 };
234
235 struct ia_css_isp_parameter_set_info {
236 struct sh_css_ddr_address_map
237 mem_map;/** pointers to Parameters in ISP format IMPT:
238 This should be first member of this struct */
239 u32
240 isp_parameters_id;/** Unique ID to track which config was actually applied to a particular frame */
241 ia_css_ptr
242 output_frame_ptr;/** Output frame to which this config has to be applied (optional) */
243 };
244
245 /* this struct contains all arguments that can be passed to
246 a binary. It depends on the binary which ones are used. */
247 struct sh_css_binary_args {
248 struct ia_css_frame *in_frame; /* input frame */
249 const struct ia_css_frame
250 *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; /* reference input frame */
251 const struct ia_css_frame *tnr_frames[NUM_VIDEO_TNR_FRAMES]; /* tnr frames */
252 struct ia_css_frame
253 *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; /* output frame */
254 struct ia_css_frame *out_vf_frame; /* viewfinder output frame */
255 bool copy_vf;
256 bool copy_output;
257 unsigned int vf_downscale_log2;
258 };
259
260 #if SP_DEBUG == SP_DEBUG_DUMP
261
262 #define SH_CSS_NUM_SP_DEBUG 48
263
264 struct sh_css_sp_debug_state {
265 unsigned int error;
266 unsigned int debug[SH_CSS_NUM_SP_DEBUG];
267 };
268
269 #elif SP_DEBUG == SP_DEBUG_COPY
270
271 #define SH_CSS_SP_DBG_TRACE_DEPTH (40)
272
273 struct sh_css_sp_debug_trace {
274 u16 frame;
275 u16 line;
276 u16 pixel_distance;
277 u16 mipi_used_dword;
278 u16 sp_index;
279 };
280
281 struct sh_css_sp_debug_state {
282 u16 if_start_line;
283 u16 if_start_column;
284 u16 if_cropped_height;
285 u16 if_cropped_width;
286 unsigned int index;
287 struct sh_css_sp_debug_trace
288 trace[SH_CSS_SP_DBG_TRACE_DEPTH];
289 };
290
291 #elif SP_DEBUG == SP_DEBUG_TRACE
292
293 /* Example of just one global trace */
294 #define SH_CSS_SP_DBG_NR_OF_TRACES (1)
295 #define SH_CSS_SP_DBG_TRACE_DEPTH (40)
296
297 #define SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS (13)
298
299 struct sh_css_sp_debug_trace {
300 u16 time_stamp;
301 u16 location; /* bit 15..13 = file_id, 12..0 = line nr. */
302 u32 data;
303 };
304
305 struct sh_css_sp_debug_state {
306 struct sh_css_sp_debug_trace
307 trace[SH_CSS_SP_DBG_NR_OF_TRACES][SH_CSS_SP_DBG_TRACE_DEPTH];
308 u16 index_last[SH_CSS_SP_DBG_NR_OF_TRACES];
309 u8 index[SH_CSS_SP_DBG_NR_OF_TRACES];
310 };
311
312 #elif SP_DEBUG == SP_DEBUG_MINIMAL
313
314 #define SH_CSS_NUM_SP_DEBUG 128
315
316 struct sh_css_sp_debug_state {
317 unsigned int error;
318 unsigned int debug[SH_CSS_NUM_SP_DEBUG];
319 };
320
321 #endif
322
323 struct sh_css_sp_debug_command {
324 /*
325 * The DMA software-mask,
326 * Bit 31...24: unused.
327 * Bit 23...16: unused.
328 * Bit 15...08: reading-request enabling bits for DMA channel 7..0
329 * Bit 07...00: writing-request enabling bits for DMA channel 7..0
330 *
331 * For example, "0...0 0...0 11111011 11111101" indicates that the
332 * writing request through DMA Channel 1 and the reading request
333 * through DMA channel 2 are both disabled. The others are enabled.
334 */
335 u32 dma_sw_reg;
336 };
337
338 /* SP input formatter configuration.*/
339 struct sh_css_sp_input_formatter_set {
340 u32 stream_format;
341 input_formatter_cfg_t config_a;
342 input_formatter_cfg_t config_b;
343 };
344
345 #define IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT (3)
346
347 /*
348 * SP configuration information
349 *
350 * This struct is part of the atomisp firmware ABI and is directly copied
351 * to ISP DRAM by sh_css_store_sp_group_to_ddr()
352 *
353 * Do NOT change this struct's layout or remove seemingly unused fields!
354 */
355 struct sh_css_sp_config {
356 u8 no_isp_sync; /* Signal host immediately after start */
357 u8 enable_raw_pool_locking; /** Enable Raw Buffer Locking for HALv3 Support */
358 u8 lock_all;
359 /** If raw buffer locking is enabled, this flag indicates whether raw
360 frames are locked when their EOF event is successfully sent to the
361 host (true) or when they are passed to the preview/video pipe
362 (false). */
363
364 /*
365 * Note the fields below are only used on the ISP2400 not on the ISP2401,
366 * sh_css_store_sp_group_to_ddr() skip copying these when run on the ISP2401.
367 */
368 struct {
369 u8 a_changed;
370 u8 b_changed;
371 u8 isp_2ppc;
372 struct sh_css_sp_input_formatter_set
373 set[SH_CSS_MAX_IF_CONFIGS]; /* CSI-2 port is used as index. */
374 } input_formatter;
375
376 sync_generator_cfg_t sync_gen;
377 tpg_cfg_t tpg;
378 prbs_cfg_t prbs;
379 input_system_cfg_t input_circuit;
380 u8 input_circuit_cfg_changed;
381 u32 mipi_sizes_for_check[N_CSI_PORTS][IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT];
382 /* These last 2 fields are used on both the ISP2400 and the ISP2401 */
383 u8 enable_isys_event_queue;
384 u8 disable_cont_vf;
385 };
386
387 enum sh_css_stage_type {
388 SH_CSS_SP_STAGE_TYPE = 0,
389 SH_CSS_ISP_STAGE_TYPE = 1
390 };
391
392 #define SH_CSS_NUM_STAGE_TYPES 2
393
394 #define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS BIT(0)
395 #define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS_MASK \
396 ((SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << SH_CSS_MAX_SP_THREADS) - 1)
397
398 struct sh_css_sp_pipeline_terminal {
399 union {
400 /* Input System 2401 */
401 virtual_input_system_stream_t
402 virtual_input_system_stream[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH];
403 } context;
404 /*
405 * TODO
406 * - Remove "virtual_input_system_cfg" when the ISYS2401 DLI is ready.
407 */
408 union {
409 /* Input System 2401 */
410 virtual_input_system_stream_cfg_t
411 virtual_input_system_stream_cfg[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH];
412 } ctrl;
413 };
414
415 struct sh_css_sp_pipeline_io {
416 struct sh_css_sp_pipeline_terminal input;
417 /* pqiao: comment out temporarily to save dmem */
418 /*struct sh_css_sp_pipeline_terminal output;*/
419 };
420
421 /* This struct tracks how many streams are registered per CSI port.
422 * This is used to track which streams have already been configured.
423 * Only when all streams are configured, the CSI RX is started for that port.
424 */
425 struct sh_css_sp_pipeline_io_status {
426 u32 active[N_INPUT_SYSTEM_CSI_PORT]; /** registered streams */
427 u32 running[N_INPUT_SYSTEM_CSI_PORT]; /** configured streams */
428 };
429
430 enum sh_css_port_dir {
431 SH_CSS_PORT_INPUT = 0,
432 SH_CSS_PORT_OUTPUT = 1
433 };
434
435 enum sh_css_port_type {
436 SH_CSS_HOST_TYPE = 0,
437 SH_CSS_COPYSINK_TYPE = 1,
438 SH_CSS_TAGGERSINK_TYPE = 2
439 };
440
441 /* Pipe inout settings: output port on 7-4bits, input port on 3-0bits */
442 #define SH_CSS_PORT_FLD_WIDTH_IN_BITS (4)
443 #define SH_CSS_PORT_TYPE_BIT_FLD(pt) (0x1 << (pt))
444 #define SH_CSS_PORT_FLD(pd) ((pd) ? SH_CSS_PORT_FLD_WIDTH_IN_BITS : 0)
445 #define SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) ((p) |= (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd)))
446 #define SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt) ((p) &= ~(SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd)))
447 #define SH_CSS_PIPE_PORT_CONFIG_SET(p, pd, pt, val) ((val) ? \
448 SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) : SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt))
449 #define SH_CSS_PIPE_PORT_CONFIG_GET(p, pd, pt) ((p) & (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd)))
450 #define SH_CSS_PIPE_PORT_CONFIG_IS_CONTINUOUS(p) \
451 (!(SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_INPUT, SH_CSS_HOST_TYPE) && \
452 SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_OUTPUT, SH_CSS_HOST_TYPE)))
453
454 #define IA_CSS_ACQUIRE_ISP_POS 31
455
456 /* Flags for metadata processing */
457 #define SH_CSS_METADATA_ENABLED 0x01
458 #define SH_CSS_METADATA_PROCESSED 0x02
459 #define SH_CSS_METADATA_OFFLINE_MODE 0x04
460 #define SH_CSS_METADATA_WAIT_INPUT 0x08
461
462 /* @brief Free an array of metadata buffers.
463 *
464 * @param[in] num_bufs Number of metadata buffers to be freed.
465 * @param[in] bufs Pointer of array of metadata buffers.
466 *
467 * This function frees an array of metadata buffers.
468 */
469 void
470 ia_css_metadata_free_multiple(unsigned int num_bufs,
471 struct ia_css_metadata **bufs);
472
473 /* Macro for handling pipe_qos_config */
474 #define QOS_INVALID (~0U)
475
476 /* Information for a pipeline */
477 struct sh_css_sp_pipeline {
478 u32 pipe_id; /* the pipe ID */
479 u32 pipe_num; /* the dynamic pipe number */
480 u32 thread_id; /* the sp thread ID */
481 u32 pipe_config; /* the pipe config */
482 u32 pipe_qos_config; /* Bitmap of multiple QOS extension fw state.
483 (0xFFFFFFFF) indicates non QOS pipe.*/
484 u32 inout_port_config;
485 u32 required_bds_factor;
486 u32 dvs_frame_delay;
487 u32 input_system_mode; /* enum ia_css_input_mode */
488 u32 port_id; /* port_id for input system */
489 u32 num_stages; /* the pipe config */
490 u32 running; /* needed for pipe termination */
491 ia_css_ptr sp_stage_addr[SH_CSS_MAX_STAGES];
492 ia_css_ptr scaler_pp_lut; /* Early bound LUT */
493 u32 dummy; /* stage ptr is only used on sp but lives in
494 this struct; needs cleanup */
495 s32 num_execs; /* number of times to run if this is
496 an acceleration pipe. */
497 struct {
498 u32 format; /* Metadata format in hrt format */
499 u32 width; /* Width of a line */
500 u32 height; /* Number of lines */
501 u32 stride; /* Stride (in bytes) per line */
502 u32 size; /* Total size (in bytes) */
503 ia_css_ptr cont_buf; /* Address of continuous buffer */
504 } metadata;
505 u32 output_frame_queue_id;
506 union {
507 struct {
508 u32 bytes_available;
509 } bin;
510 struct {
511 u32 height;
512 u32 width;
513 u32 padded_width;
514 u32 max_input_width;
515 u32 raw_bit_depth;
516 } raw;
517 } copy;
518 };
519
520 /*
521 * The first frames (with comment Dynamic) can be dynamic or static
522 * The other frames (ref_in and below) can only be static
523 * Static means that the data address will not change during the life time
524 * of the associated pipe. Dynamic means that the data address can
525 * change with every (frame) iteration of the associated pipe
526 *
527 * s3a and dis are now also dynamic but (still) handled separately
528 */
529 #define SH_CSS_NUM_DYNAMIC_FRAME_IDS (3)
530
531 struct ia_css_frames_sp {
532 struct ia_css_frame_sp in;
533 struct ia_css_frame_sp out[IA_CSS_BINARY_MAX_OUTPUT_PORTS];
534 struct ia_css_resolution effective_in_res;
535 struct ia_css_frame_sp out_vf;
536 struct ia_css_frame_sp_info internal_frame_info;
537 struct ia_css_buffer_sp s3a_buf;
538 struct ia_css_buffer_sp dvs_buf;
539 struct ia_css_buffer_sp metadata_buf;
540 };
541
542 /* Information for a single pipeline stage for an ISP */
543 struct sh_css_isp_stage {
544 /*
545 * For compatibility and portabilty, only types
546 * from "stdint.h" are allowed
547 *
548 * Use of "enum" and "bool" is prohibited
549 * Multiple boolean flags can be stored in an
550 * integer
551 */
552 struct ia_css_blob_info blob_info;
553 struct ia_css_binary_info binary_info;
554 char binary_name[SH_CSS_MAX_BINARY_NAME];
555 struct ia_css_isp_param_css_segments mem_initializers;
556 };
557
558 /* Information for a single pipeline stage */
559 struct sh_css_sp_stage {
560 /*
561 * For compatibility and portabilty, only types
562 * from "stdint.h" are allowed
563 *
564 * Use of "enum" and "bool" is prohibited
565 * Multiple boolean flags can be stored in an
566 * integer
567 */
568 u8 num; /* Stage number */
569 u8 isp_online;
570 u8 isp_copy_vf;
571 u8 isp_copy_output;
572 u8 sp_enable_xnr;
573 u8 isp_deci_log_factor;
574 u8 isp_vf_downscale_bits;
575 u8 deinterleaved;
576 /*
577 * NOTE: Programming the input circuit can only be done at the
578 * start of a session. It is illegal to program it during execution
579 * The input circuit defines the connectivity
580 */
581 u8 program_input_circuit;
582 /* enum ia_css_pipeline_stage_sp_func func; */
583 u8 func;
584 /* The type of the pipe-stage */
585 /* enum sh_css_stage_type stage_type; */
586 u8 stage_type;
587 u8 num_stripes;
588 u8 isp_pipe_version;
589 struct {
590 u8 vf_output;
591 u8 s3a;
592 u8 sdis;
593 u8 dvs_stats;
594 u8 lace_stats;
595 } enable;
596 /* Add padding to come to a word boundary */
597 /* unsigned char padding[0]; */
598
599 struct sh_css_crop_pos sp_out_crop_pos;
600 struct ia_css_frames_sp frames;
601 struct ia_css_resolution dvs_envelope;
602 struct sh_css_uds_info uds;
603 ia_css_ptr isp_stage_addr;
604 ia_css_ptr xmem_bin_addr;
605 ia_css_ptr xmem_map_addr;
606
607 u16 top_cropping;
608 u16 row_stripes_height;
609 u16 row_stripes_overlap_lines;
610 u8 if_config_index; /* Which should be applied by this stage. */
611 };
612
613 /*
614 * Time: 2012-07-19, 17:40.
615 * Note: Add a new data member "debug" in "sh_css_sp_group". This
616 * data member is used to pass the debugging command from the
617 * Host to the SP.
618 *
619 * Time: Before 2012-07-19.
620 * Note:
621 * Group all host initialized SP variables into this struct.
622 * This is initialized every stage through dma.
623 * The stage part itself is transferred through sh_css_sp_stage.
624 */
625 struct sh_css_sp_group {
626 struct sh_css_sp_config config;
627 struct sh_css_sp_pipeline pipe[SH_CSS_MAX_SP_THREADS];
628 struct sh_css_sp_pipeline_io pipe_io[SH_CSS_MAX_SP_THREADS];
629 struct sh_css_sp_pipeline_io_status pipe_io_status;
630 struct sh_css_sp_debug_command debug;
631 };
632
633 /* Data in SP dmem that is set from the host every stage. */
634 struct sh_css_sp_per_frame_data {
635 /* ddr address of sp_group and sp_stage */
636 ia_css_ptr sp_group_addr;
637 };
638
639 #define SH_CSS_NUM_SDW_IRQS 3
640
641 /* Output data from SP to css */
642 struct sh_css_sp_output {
643 unsigned int bin_copy_bytes_copied;
644 #if SP_DEBUG != SP_DEBUG_NONE
645 struct sh_css_sp_debug_state debug;
646 #endif
647 unsigned int sw_interrupt_value[SH_CSS_NUM_SDW_IRQS];
648 };
649
650 /**
651 * @brief Data structure for the circular buffer.
652 * The circular buffer is empty if "start == end". The
653 * circular buffer is full if "(end + 1) % size == start".
654 */
655 /* Variable Sized Buffer Queue Elements */
656
657 #define IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE 6
658 #define IA_CSS_NUM_ELEMS_HOST2SP_PARAM_QUEUE 3
659 #define IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE 6
660
661 /* sp-to-host queue is expected to be emptied in ISR since
662 * it is used instead of HW interrupts (due to HW design issue).
663 * We need one queue element per CSI port. */
664 #define IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS)
665 /* The host-to-sp queue needs to allow for some delay
666 * in the emptying of this queue in the SP since there is no
667 * separate SP thread for this. */
668 #define IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS)
669
670 #define IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE 13
671 #define IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE 19
672 #define IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE 26 /* holds events for all type of buffers, hence deeper */
673
674 struct sh_css_hmm_buffer {
675 union {
676 struct ia_css_isp_3a_statistics s3a;
677 struct ia_css_isp_dvs_statistics dis;
678 ia_css_ptr skc_dvs_statistics;
679 ia_css_ptr lace_stat;
680 struct ia_css_metadata metadata;
681 struct frame_data_wrapper {
682 ia_css_ptr frame_data;
683 u32 flashed;
684 u32 exp_id;
685 u32 isp_parameters_id; /** Unique ID to track which config was
686 actually applied to a particular frame */
687 } frame;
688 ia_css_ptr ddr_ptrs;
689 } payload;
690 /*
691 * kernel_ptr is present for host administration purposes only.
692 * type is uint64_t in order to be 64-bit host compatible.
693 * uint64_t does not exist on SP/ISP.
694 * Size of the struct is checked by sp.hive.c.
695 */
696 CSS_ALIGN(u64 cookie_ptr, 8); /* TODO: check if this alignment is needed */
697 u64 kernel_ptr;
698 struct ia_css_time_meas timing_data;
699 clock_value_t isys_eof_clock_tick;
700 };
701
702 #define SIZE_OF_FRAME_STRUCT \
703 (SIZE_OF_HRT_VADDRESS + \
704 (3 * sizeof(uint32_t)))
705
706 #define SIZE_OF_PAYLOAD_UNION \
707 (MAX(MAX(MAX(MAX( \
708 SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT, \
709 SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT), \
710 SIZE_OF_IA_CSS_METADATA_STRUCT), \
711 SIZE_OF_FRAME_STRUCT), \
712 SIZE_OF_HRT_VADDRESS))
713
714 /* Do not use sizeof(uint64_t) since that does not exist of SP */
715 #define SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT \
716 (SIZE_OF_PAYLOAD_UNION + \
717 CALC_ALIGNMENT_MEMBER(SIZE_OF_PAYLOAD_UNION, 8) + \
718 8 + \
719 8 + \
720 SIZE_OF_IA_CSS_TIME_MEAS_STRUCT + \
721 SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT + \
722 CALC_ALIGNMENT_MEMBER(SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT, 8))
723
724 static_assert(sizeof(struct sh_css_hmm_buffer) == SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT);
725
726 enum sh_css_queue_type {
727 sh_css_invalid_queue_type = -1,
728 sh_css_host2sp_buffer_queue,
729 sh_css_sp2host_buffer_queue,
730 sh_css_host2sp_psys_event_queue,
731 sh_css_sp2host_psys_event_queue,
732 sh_css_sp2host_isys_event_queue,
733 sh_css_host2sp_isys_event_queue,
734 sh_css_host2sp_tag_cmd_queue,
735 };
736
737 struct sh_css_event_irq_mask {
738 u16 or_mask;
739 u16 and_mask;
740 };
741
742 #define SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT \
743 (2 * sizeof(uint16_t))
744
745 static_assert(sizeof(struct sh_css_event_irq_mask) == SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT);
746
747 struct host_sp_communication {
748 /*
749 * Don't use enum host2sp_commands, because the sizeof an enum is
750 * compiler dependent and thus non-portable
751 */
752 u32 host2sp_command;
753
754 /*
755 * The frame buffers that are reused by the
756 * copy pipe in the offline preview mode.
757 *
758 * host2sp_offline_frames[0]: the input frame of the preview pipe.
759 * host2sp_offline_frames[1]: the output frame of the copy pipe.
760 *
761 * TODO:
762 * Remove it when the Host and the SP is decoupled.
763 */
764 ia_css_ptr host2sp_offline_frames[NUM_CONTINUOUS_FRAMES];
765 ia_css_ptr host2sp_offline_metadata[NUM_CONTINUOUS_FRAMES];
766
767 ia_css_ptr host2sp_mipi_frames[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM];
768 ia_css_ptr host2sp_mipi_metadata[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM];
769 u32 host2sp_num_mipi_frames[N_CSI_PORTS];
770 u32 host2sp_cont_avail_num_raw_frames;
771 u32 host2sp_cont_extra_num_raw_frames;
772 u32 host2sp_cont_target_num_raw_frames;
773 struct sh_css_event_irq_mask host2sp_event_irq_mask[NR_OF_PIPELINES];
774
775 };
776
777 #define SIZE_OF_HOST_SP_COMMUNICATION_STRUCT \
778 (sizeof(uint32_t) + \
779 (NUM_CONTINUOUS_FRAMES * SIZE_OF_HRT_VADDRESS * 2) + \
780 (N_CSI_PORTS * NUM_MIPI_FRAMES_PER_STREAM * SIZE_OF_HRT_VADDRESS * 2) + \
781 ((3 + N_CSI_PORTS) * sizeof(uint32_t)) + \
782 (NR_OF_PIPELINES * SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT))
783
784 static_assert(sizeof(struct host_sp_communication) == SIZE_OF_HOST_SP_COMMUNICATION_STRUCT);
785
786 struct host_sp_queues {
787 /*
788 * Queues for the dynamic frame information,
789 * i.e. the "in_frame" buffer, the "out_frame"
790 * buffer and the "vf_out_frame" buffer.
791 */
792 ia_css_circbuf_desc_t host2sp_buffer_queues_desc
793 [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES];
794 ia_css_circbuf_elem_t host2sp_buffer_queues_elems
795 [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]
796 [IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE];
797 ia_css_circbuf_desc_t sp2host_buffer_queues_desc
798 [SH_CSS_MAX_NUM_QUEUES];
799 ia_css_circbuf_elem_t sp2host_buffer_queues_elems
800 [SH_CSS_MAX_NUM_QUEUES][IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE];
801
802 /*
803 * The queues for the events.
804 */
805 ia_css_circbuf_desc_t host2sp_psys_event_queue_desc;
806
807 ia_css_circbuf_elem_t host2sp_psys_event_queue_elems
808 [IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE];
809 ia_css_circbuf_desc_t sp2host_psys_event_queue_desc;
810
811 ia_css_circbuf_elem_t sp2host_psys_event_queue_elems
812 [IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE];
813
814 /*
815 * The queues for the ISYS events.
816 */
817 ia_css_circbuf_desc_t host2sp_isys_event_queue_desc;
818
819 ia_css_circbuf_elem_t host2sp_isys_event_queue_elems
820 [IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE];
821 ia_css_circbuf_desc_t sp2host_isys_event_queue_desc;
822
823 ia_css_circbuf_elem_t sp2host_isys_event_queue_elems
824 [IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE];
825 /*
826 * The queue for the tagger commands.
827 * CHECK: are these last two present on the 2401 ?
828 */
829 ia_css_circbuf_desc_t host2sp_tag_cmd_queue_desc;
830
831 ia_css_circbuf_elem_t host2sp_tag_cmd_queue_elems
832 [IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE];
833 };
834
835 #define SIZE_OF_QUEUES_ELEMS \
836 (SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT * \
837 ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE) + \
838 (SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE) + \
839 (IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE) + \
840 (IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE) + \
841 (IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE) + \
842 (IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE) + \
843 (IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE)))
844
845 #define IA_CSS_NUM_CIRCBUF_DESCS 5
846
847 #define SIZE_OF_QUEUES_DESC \
848 ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * \
849 SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \
850 (SH_CSS_MAX_NUM_QUEUES * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \
851 (IA_CSS_NUM_CIRCBUF_DESCS * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT))
852
853 #define SIZE_OF_HOST_SP_QUEUES_STRUCT \
854 (SIZE_OF_QUEUES_ELEMS + SIZE_OF_QUEUES_DESC)
855
856 static_assert(sizeof(struct host_sp_queues) == SIZE_OF_HOST_SP_QUEUES_STRUCT);
857
858 extern int __printf(1, 0) (*sh_css_printf)(const char *fmt, va_list args);
859
sh_css_print(const char * fmt,...)860 static inline void __printf(1, 2) sh_css_print(const char *fmt, ...)
861 {
862 va_list ap;
863
864 if (sh_css_printf) {
865 va_start(ap, fmt);
866 sh_css_printf(fmt, ap);
867 va_end(ap);
868 }
869 }
870
sh_css_vprint(const char * fmt,va_list args)871 static inline void __printf(1, 0) sh_css_vprint(const char *fmt, va_list args)
872 {
873 if (sh_css_printf)
874 sh_css_printf(fmt, args);
875 }
876
877 /* The following #if is there because this header file is also included
878 by SP and ISP code but they do not need this data and HIVECC has alignment
879 issue with the firmware struct/union's.
880 More permanent solution will be to refactor this include.
881 */
882 ia_css_ptr sh_css_params_ddr_address_map(void);
883
884 int
885 sh_css_params_init(void);
886
887 void
888 sh_css_params_uninit(void);
889
890 void
891 sh_css_binary_args_reset(struct sh_css_binary_args *args);
892
893 /* Check two frames for equality (format, resolution, bits per element) */
894 bool
895 sh_css_frame_equal_types(const struct ia_css_frame *frame_a,
896 const struct ia_css_frame *frame_b);
897
898 bool
899 sh_css_frame_info_equal_resolution(const struct ia_css_frame_info *info_a,
900 const struct ia_css_frame_info *info_b);
901
902 void
903 sh_css_capture_enable_bayer_downscaling(bool enable);
904
905 void
906 sh_css_binary_print(const struct ia_css_binary *binary);
907
908 /* aligned argument of sh_css_frame_info_set_width can be used for an extra alignment requirement.
909 When 0, no extra alignment is done. */
910 void
911 sh_css_frame_info_set_width(struct ia_css_frame_info *info,
912 unsigned int width,
913 unsigned int aligned);
914
915
916 unsigned int
917 sh_css_get_mipi_sizes_for_check(const unsigned int port,
918 const unsigned int idx);
919
920
921 ia_css_ptr
922 sh_css_store_sp_group_to_ddr(void);
923
924 ia_css_ptr
925 sh_css_store_sp_stage_to_ddr(unsigned int pipe, unsigned int stage);
926
927 ia_css_ptr
928 sh_css_store_isp_stage_to_ddr(unsigned int pipe, unsigned int stage);
929
930 void
931 sh_css_update_uds_and_crop_info(
932 const struct ia_css_binary_info *info,
933 const struct ia_css_frame_info *in_frame_info,
934 const struct ia_css_frame_info *out_frame_info,
935 const struct ia_css_resolution *dvs_env,
936 const struct ia_css_dz_config *zoom,
937 const struct ia_css_vector *motion_vector,
938 struct sh_css_uds_info *uds, /* out */
939 struct sh_css_crop_pos *sp_out_crop_pos, /* out */
940
941 bool enable_zoom
942 );
943
944 void
945 sh_css_invalidate_shading_tables(struct ia_css_stream *stream);
946
947 struct ia_css_pipeline *
948 ia_css_pipe_get_pipeline(const struct ia_css_pipe *pipe);
949
950 unsigned int
951 ia_css_pipe_get_pipe_num(const struct ia_css_pipe *pipe);
952
953 unsigned int
954 ia_css_pipe_get_isp_pipe_version(const struct ia_css_pipe *pipe);
955
956 bool
957 sh_css_continuous_is_enabled(uint8_t pipe_num);
958
959 struct ia_css_pipe *
960 find_pipe_by_num(uint32_t pipe_num);
961
962 void
963 ia_css_get_crop_offsets(
964 struct ia_css_pipe *pipe,
965 struct ia_css_frame_info *in_frame);
966
967 #endif /* _SH_CSS_INTERNAL_H_ */
968