1// This used to be a standard library test. But now that we can implement
2// Memories using arrays, this has become an array test.
3
4module Mem#(
5  parameter ADDR_SIZE = 4,
6  parameter BYTE_SIZE = 8
7)(
8  input  wire clock,
9  input  wire wen,
10  input  wire[ADDR_SIZE-1:0] raddr1,
11  output wire[BYTE_SIZE-1:0] rdata1,
12  input  wire[ADDR_SIZE-1:0] raddr2,
13  output wire[BYTE_SIZE-1:0] rdata2,
14  input  wire[ADDR_SIZE-1:0] waddr,
15  input  wire[BYTE_SIZE-1:0] wdata
16);
17  reg[BYTE_SIZE-1:0] mem[ADDR_SIZE-1:0];
18  assign rdata1 = mem[raddr1];
19  assign rdata2 = mem[raddr2];
20  always @(posedge clock)
21    if (wen)
22      mem[waddr] <= wdata;
23endmodule
24
25reg[3:0] COUNT = 0;
26wire[1:0] raddr = COUNT;
27wire[1:0] waddr = COUNT+1;
28wire[2:0] rd1, rd2;
29
30Mem#(4,3) mem1(
31  .clock(clock.val),
32  .wen(1),
33  .raddr1(raddr),
34  .rdata1(rd1),
35  .raddr2(raddr),
36  .rdata2(rd2),
37  .waddr(waddr),
38  .wdata(COUNT+1)
39);
40
41always @(posedge clock.val) begin
42  COUNT <= COUNT + 1;
43  if (COUNT == 8) begin
44    $finish;
45  end else begin
46    $write("%h%h", rd1, rd2);
47  end
48end
49