1//Original:/testcases/core/c_alu2op_divq/c_alu2op_divq.dsp 2// Spec Reference: alu2op divide q 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10imm32 r0, 0x00000000; 11imm32 r1, 0x12345678; 12imm32 r2, 0x23456789; 13imm32 r3, 0x3456789a; 14imm32 r4, 0x856789ab; 15imm32 r5, 0x96789abc; 16imm32 r6, 0xa789abcd; 17imm32 r7, 0xb89abcde; 18R0.L = 1; 19DIVQ ( R1 , R0 ); 20DIVQ ( R2 , R0 ); 21DIVQ ( R3 , R0 ); 22DIVQ ( R4 , R0 ); 23DIVQ ( R5 , R0 ); 24DIVQ ( R6 , R0 ); 25DIVQ ( R7 , R0 ); 26DIVQ ( R4 , R0 ); 27DIVQ ( R0 , R0 ); 28CHECKREG r1, 0x2466ACF1; 29CHECKREG r2, 0x4688CF13; 30CHECKREG r3, 0x68AAF135; 31CHECKREG r4, 0x159C26AD; 32CHECKREG r5, 0x2CF33578; 33CHECKREG r6, 0x4F15579A; 34CHECKREG r7, 0x713779BC; 35CHECKREG r0, 0xFFFE0002; 36 37imm32 r0, 0x01230002; 38imm32 r1, 0x00000000; 39imm32 r2, 0x93456789; 40imm32 r3, 0xa456789a; 41imm32 r4, 0xb56789ab; 42imm32 r5, 0xc6789abc; 43imm32 r6, 0xd789abcd; 44imm32 r7, 0xe89abcde; 45R1.L = -1; 46DIVQ ( R0 , R1 ); 47DIVQ ( R2 , R1 ); 48DIVQ ( R3 , R1 ); 49DIVQ ( R4 , R1 ); 50DIVQ ( R5 , R1 ); 51DIVQ ( R6 , R1 ); 52DIVQ ( R7 , R1 ); 53DIVQ ( R1 , R1 ); 54CHECKREG r0, 0x02440004; 55CHECKREG r1, 0x0003FFFE; 56CHECKREG r2, 0x2688CF13; 57CHECKREG r3, 0x48AEF135; 58CHECKREG r4, 0x6AD11357; 59CHECKREG r5, 0x8CF33579; 60CHECKREG r6, 0xAF15579B; 61CHECKREG r7, 0xD13779BD; 62 63imm32 r0, 0x51230002; 64imm32 r1, 0x12345678; 65imm32 r2, 0x00000000; 66imm32 r3, 0x3456789a; 67imm32 r4, 0x956789ab; 68imm32 r5, 0x86789abc; 69imm32 r6, 0x6789abcd; 70imm32 r7, 0x789abcde; 71R2.L = 31; 72DIVQ ( R0 , R2 ); 73DIVQ ( R1 , R2 ); 74DIVQ ( R3 , R2 ); 75DIVQ ( R4 , R2 ); 76DIVQ ( R5 , R2 ); 77DIVQ ( R6 , R2 ); 78DIVQ ( R7 , R2 ); 79DIVQ ( R2 , R2 ); 80CHECKREG r0, 0xA2840005; 81CHECKREG r1, 0x242AACF1; 82CHECKREG r2, 0xFFC2003E; 83CHECKREG r3, 0x686EF135; 84CHECKREG r4, 0x2A911356; 85CHECKREG r5, 0x0D2F3578; 86CHECKREG r6, 0xCF51579B; 87CHECKREG r7, 0xF0F779BD; 88 89imm32 r0, 0x01230002; 90imm32 r1, 0x82345678; 91imm32 r2, 0x93456789; 92imm32 r3, 0x00000000; 93imm32 r4, 0xb56789ab; 94imm32 r5, 0xc6789abc; 95imm32 r6, 0xd789abcd; 96imm32 r7, 0xe89abcde; 97R3.L = -31; 98DIVQ ( R0 , R3 ); 99DIVQ ( R1 , R3 ); 100DIVQ ( R2 , R3 ); 101DIVQ ( R4 , R3 ); 102DIVQ ( R5 , R3 ); 103DIVQ ( R6 , R3 ); 104DIVQ ( R7 , R3 ); 105DIVQ ( R3 , R3 ); 106CHECKREG r0, 0x02080004; 107CHECKREG r1, 0x042AACF1; 108CHECKREG r2, 0x26C8CF13; 109CHECKREG r3, 0x003FFFC2; 110CHECKREG r4, 0x6B0D1357; 111CHECKREG r5, 0x8D2F3579; 112CHECKREG r6, 0xAF51579B; 113CHECKREG r7, 0xD17379BD; 114 115imm32 r0, 0x00000001; 116imm32 r1, 0x12345678; 117imm32 r2, 0x23456789; 118imm32 r3, 0x3456789a; 119imm32 r4, 0x00000000; 120imm32 r5, 0x96789abc; 121imm32 r6, 0xa789abcd; 122imm32 r7, 0xb89abcde; 123R4.L = 15; 124DIVQ ( R1 , R4 ); 125DIVQ ( R2 , R4 ); 126DIVQ ( R3 , R4 ); 127DIVQ ( R0 , R4 ); 128DIVQ ( R5 , R4 ); 129DIVQ ( R6 , R4 ); 130DIVQ ( R7 , R4 ); 131DIVQ ( R4 , R4 ); 132CHECKREG r0, 0xFFE20002; 133CHECKREG r1, 0x2486ACF1; 134CHECKREG r2, 0x466CCF13; 135CHECKREG r3, 0x688EF135; 136CHECKREG r4, 0x001E001F; 137CHECKREG r5, 0x2D0F3578; 138CHECKREG r6, 0x4F31579A; 139CHECKREG r7, 0x715379BC; 140 141imm32 r0, 0x01230002; 142imm32 r1, 0x00000000; 143imm32 r2, 0x93456789; 144imm32 r3, 0xa456789a; 145imm32 r4, 0xb56789ab; 146imm32 r5, 0x00000000; 147imm32 r6, 0xd789abcd; 148imm32 r7, 0xe89abcde; 149R5.L = -15; 150DIVQ ( R0 , R5 ); 151DIVQ ( R1 , R5 ); 152DIVQ ( R2 , R5 ); 153DIVQ ( R3 , R5 ); 154DIVQ ( R4 , R5 ); 155DIVQ ( R6 , R5 ); 156DIVQ ( R7 , R5 ); 157DIVQ ( R5 , R5 ); 158CHECKREG r0, 0x02640004; 159CHECKREG r1, 0xFFE20001; 160CHECKREG r2, 0x26A8CF13; 161CHECKREG r3, 0x48CAF135; 162CHECKREG r4, 0x6AED1357; 163CHECKREG r5, 0x001FFFE2; 164CHECKREG r6, 0xAF31579B; 165CHECKREG r7, 0xD15379BD; 166 167imm32 r0, 0x51230002; 168imm32 r1, 0x12345678; 169imm32 r2, 0xb1256790; 170imm32 r3, 0x3456789a; 171imm32 r4, 0x956789ab; 172imm32 r5, 0x86789abc; 173imm32 r6, 0x00000000; 174imm32 r7, 0x789abcde; 175R6.L = 24; 176DIVQ ( R0 , R6 ); 177DIVQ ( R1 , R6 ); 178DIVQ ( R2 , R6 ); 179DIVQ ( R3 , R6 ); 180DIVQ ( R4 , R6 ); 181DIVQ ( R5 , R6 ); 182DIVQ ( R7 , R6 ); 183DIVQ ( R6 , R6 ); 184CHECKREG r0, 0xA2760005; 185CHECKREG r1, 0x2438ACF1; 186CHECKREG r2, 0x621ACF20; 187CHECKREG r3, 0x68DCF135; 188CHECKREG r4, 0x2A9F1356; 189CHECKREG r5, 0x0D213578; 190CHECKREG r6, 0xFFD00030; 191CHECKREG r7, 0xF16579BD; 192 193imm32 r0, 0x01230002; 194imm32 r1, 0x82345678; 195imm32 r2, 0x93456789; 196imm32 r3, 0xa456789a; 197imm32 r4, 0xb56789ab; 198imm32 r5, 0xc6789abc; 199imm32 r6, 0xd789abcd; 200imm32 r7, 0x00000000; 201R7.L = -24; 202DIVQ ( R0 , R7 ); 203DIVQ ( R1 , R7 ); 204DIVQ ( R2 , R7 ); 205DIVQ ( R3 , R7 ); 206DIVQ ( R4 , R7 ); 207DIVQ ( R5 , R7 ); 208DIVQ ( R6 , R7 ); 209DIVQ ( R7 , R7 ); 210CHECKREG r0, 0x02160004; 211CHECKREG r1, 0x0438ACF1; 212CHECKREG r2, 0x26BACF13; 213CHECKREG r3, 0x48DCF135; 214CHECKREG r4, 0x6AFF1357; 215CHECKREG r5, 0x8D213579; 216CHECKREG r6, 0xAF43579B; 217CHECKREG r7, 0x0031FFD0; 218 219 220pass 221