1//Original:/proj/frio/dv/testcases/core/c_alu2op_log_r_sft/c_alu2op_log_r_sft.dsp 2// Spec Reference: alu2op logical right 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 imm32 r0, 0x00000000; 9 imm32 r1, 0x12345678; 10 imm32 r2, 0x23456789; 11 imm32 r3, 0x3456789a; 12 imm32 r4, 0x856789ab; 13 imm32 r5, 0x96789abc; 14 imm32 r6, 0xa789abcd; 15 imm32 r7, 0xb89abcde; 16 R0.L = 1; 17 R1 >>= R0; 18 R2 >>= R0; 19 R3 >>= R0; 20 R4 >>= R0; 21 R5 >>= R0; 22 R6 >>= R0; 23 R7 >>= R0; 24 R4 >>= R0; 25 R0 >>= R0; 26 CHECKREG r1, 0x091A2B3C; 27 CHECKREG r2, 0x11A2B3C4; 28 CHECKREG r3, 0x1A2B3C4D; 29 CHECKREG r4, 0x2159E26A; 30 CHECKREG r5, 0x4B3C4D5E; 31 CHECKREG r6, 0x53C4D5E6; 32 CHECKREG r7, 0x5C4D5E6F; 33 CHECKREG r0, 0x00000000; 34 35 imm32 r0, 0x01230002; 36 imm32 r1, 0x00000000; 37 imm32 r2, 0x93456789; 38 imm32 r3, 0xa456789a; 39 imm32 r4, 0xb56789ab; 40 imm32 r5, 0xc6789abc; 41 imm32 r6, 0xd789abcd; 42 imm32 r7, 0xe89abcde; 43 R1.L = -1; 44 R0 >>= R1; 45 R2 >>= R1; 46 R3 >>= R1; 47 R4 >>= R1; 48 R5 >>= R1; 49 R6 >>= R1; 50 R7 >>= R1; 51 R1 >>= R1; 52 CHECKREG r0, 0x00000000; 53 CHECKREG r1, 0x00000000; 54 CHECKREG r2, 0x00000000; 55 CHECKREG r3, 0x00000000; 56 CHECKREG r4, 0x00000000; 57 CHECKREG r5, 0x00000000; 58 CHECKREG r6, 0x00000000; 59 CHECKREG r7, 0x00000000; 60 61 imm32 r0, 0x51230002; 62 imm32 r1, 0x12345678; 63 imm32 r2, 0x00000000; 64 imm32 r3, 0x3456789a; 65 imm32 r4, 0x956789ab; 66 imm32 r5, 0x86789abc; 67 imm32 r6, 0x6789abcd; 68 imm32 r7, 0x789abcde; 69 R2.L = 31; 70 R0 >>= R2; 71 R1 >>= R2; 72 R3 >>= R2; 73 R4 >>= R2; 74 R5 >>= R2; 75 R6 >>= R2; 76 R7 >>= R2; 77 R2 >>= R2; 78 CHECKREG r0, 0x00000000; 79 CHECKREG r1, 0x00000000; 80 CHECKREG r2, 0x00000000; 81 CHECKREG r3, 0x00000000; 82 CHECKREG r4, 0x00000001; 83 CHECKREG r5, 0x00000001; 84 CHECKREG r6, 0x00000000; 85 CHECKREG r7, 0x00000000; 86 87 imm32 r0, 0x01230002; 88 imm32 r1, 0x82345678; 89 imm32 r2, 0x93456789; 90 imm32 r3, 0x00000000; 91 imm32 r4, 0xb56789ab; 92 imm32 r5, 0xc6789abc; 93 imm32 r6, 0xd789abcd; 94 imm32 r7, 0xe89abcde; 95 R3.L = -31; 96 R0 >>= R3; 97 R1 >>= R3; 98 R2 >>= R3; 99 R4 >>= R3; 100 R5 >>= R3; 101 R6 >>= R3; 102 R7 >>= R3; 103 R3 >>= R3; 104 CHECKREG r0, 0x00; 105 CHECKREG r1, 0x0; 106 CHECKREG r2, 0x0; 107 CHECKREG r3, 0x0; 108 CHECKREG r4, 0x0; 109 CHECKREG r5, 0x0; 110 CHECKREG r6, 0x0; 111 CHECKREG r7, 0x0; 112 113 imm32 r0, 0x00000001; 114 imm32 r1, 0x12345678; 115 imm32 r2, 0x23456789; 116 imm32 r3, 0x3456789a; 117 imm32 r4, 0x00000000; 118 imm32 r5, 0x96789abc; 119 imm32 r6, 0xa789abcd; 120 imm32 r7, 0xb89abcde; 121 R4.L = 15; 122 R1 >>= R4; 123 R2 >>= R4; 124 R3 >>= R4; 125 R0 >>= R4; 126 R5 >>= R4; 127 R6 >>= R4; 128 R7 >>= R4; 129 R4 >>= R4; 130 CHECKREG r0, 0x00000000; 131 CHECKREG r1, 0x00002468; 132 CHECKREG r2, 0x0000468A; 133 CHECKREG r3, 0x000068AC; 134 CHECKREG r4, 0x00000000; 135 CHECKREG r5, 0x00012CF1; 136 CHECKREG r6, 0x00014F13; 137 CHECKREG r7, 0x00017135; 138 139 imm32 r0, 0x01230002; 140 imm32 r1, 0x00000000; 141 imm32 r2, 0x93456789; 142 imm32 r3, 0xa456789a; 143 imm32 r4, 0xb56789ab; 144 imm32 r5, 0x00000000; 145 imm32 r6, 0xd789abcd; 146 imm32 r7, 0xe89abcde; 147 R5.L = -15; 148 R0 >>= R5; 149 R1 >>= R5; 150 R2 >>= R5; 151 R3 >>= R5; 152 R4 >>= R5; 153 R6 >>= R5; 154 R7 >>= R5; 155 R5 >>= R5; 156 CHECKREG r0, 0x000000; 157 CHECKREG r1, 0x00000000; 158 CHECKREG r2, 0x0000; 159 CHECKREG r3, 0x0000; 160 CHECKREG r4, 0x0000; 161 CHECKREG r5, 0x00000000; 162 CHECKREG r6, 0x0000; 163 CHECKREG r7, 0x0000; 164 165 imm32 r0, 0x51230002; 166 imm32 r1, 0x12345678; 167 imm32 r2, 0xb1256790; 168 imm32 r3, 0x3456789a; 169 imm32 r4, 0x956789ab; 170 imm32 r5, 0x86789abc; 171 imm32 r6, 0x00000000; 172 imm32 r7, 0x789abcde; 173 R6.L = 24; 174 R0 >>= R6; 175 R1 >>= R6; 176 R2 >>= R6; 177 R3 >>= R6; 178 R4 >>= R6; 179 R5 >>= R6; 180 R7 >>= R6; 181 R6 >>= R6; 182 CHECKREG r0, 0x00000051; 183 CHECKREG r1, 0x00000012; 184 CHECKREG r2, 0x000000B1; 185 CHECKREG r3, 0x00000034; 186 CHECKREG r4, 0x00000095; 187 CHECKREG r5, 0x00000086; 188 CHECKREG r6, 0x00000000; 189 CHECKREG r7, 0x00000078; 190 191 imm32 r0, 0x01230002; 192 imm32 r1, 0x82345678; 193 imm32 r2, 0x93456789; 194 imm32 r3, 0xa456789a; 195 imm32 r4, 0xb56789ab; 196 imm32 r5, 0xc6789abc; 197 imm32 r6, 0xd789abcd; 198 imm32 r7, 0x00000000; 199 R7.L = -24; 200 R0 >>= R7; 201 R1 >>= R7; 202 R2 >>= R7; 203 R3 >>= R7; 204 R4 >>= R7; 205 R5 >>= R7; 206 R6 >>= R7; 207 R7 >>= R7; 208 CHECKREG r0, 0x00; 209 CHECKREG r1, 0x00; 210 CHECKREG r2, 0x00; 211 CHECKREG r3, 0x00; 212 CHECKREG r4, 0x00; 213 CHECKREG r5, 0x00; 214 CHECKREG r6, 0x00; 215 CHECKREG r7, 0x00; 216 217 pass 218