1//Original:/testcases/seq/c_br_preg_stall_ac/c_br_preg_stall_ac.dsp 2// Spec Reference: brcc kills data cache hits 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 /* This test likes to assume the current [SP] is valid */ 9 SP += -12; 10 11 imm32 r0, 0x00000000; 12 imm32 r1, 0x00000001; 13 imm32 r2, 0x00000002; 14 imm32 r3, 0x00000003; 15 imm32 r4, 0x00000004; 16 imm32 r5, 0x00000005; 17 imm32 r6, 0x00000006; 18 imm32 r7, 0x00000007; 19 imm32 p1, 0x00000011; 20 imm32 p2, 0x00000012; 21.ifndef BFIN_HOST; 22 imm32 p3, 0x00000013; 23.endif 24 imm32 p4, 0x00000014; 25 26 P1 = 4; 27 P2 = 6; 28 loadsym P5, DATA0; 29 loadsym I0, DATA1; 30 31begin: 32 ASTAT = R0; // clear CC 33 R0 = CC; 34 IF CC R1 = R0; 35 [ SP ] = P2; 36 P2 = [ SP ]; 37 JUMP ( PC + P2 ); //brf LABEL1; // (bp); 38 CC = R4 < R5; // CC FLAG killed 39 R1 = 21; 40LABEL1: 41 JUMP ( PC + P1 ); // EX1 relative to 'brf LABEL1' 42 CC = ! CC; 43LABEL2: 44 JUMP ( PC + P1 ); //brf LABEL3; 45 JUMP ( PC + P2 ); //BAD1; // UJUMP killed 46LABEL3: 47 JUMP ( PC + P1 ); //brf LABELCHK1; 48BAD1: 49 R7 = [ P5 ]; // LDST killed 50 51LABELCHK1: 52 CHECKREG r0, 0x00000000; 53 CHECKREG r1, 0x00000001; 54 CHECKREG r2, 0x00000002; 55 CHECKREG r3, 0x00000003; 56 CHECKREG r4, 0x00000004; 57 CHECKREG r5, 0x00000005; 58 CHECKREG r6, 0x00000006; 59 CHECKREG r7, 0x00000007; 60 61 pass 62 63 .data 64DATA0: 65 .dd 0x000a0000 66 .dd 0x000b0001 67 .dd 0x000c0002 68 .dd 0x000d0003 69 .dd 0x000e0004 70 71DATA1: 72 .dd 0x00f00100 73 .dd 0x00e00101 74 .dd 0x00d00102 75 .dd 0x00c00103 76