1//Original:/testcases/core/c_cc2stat_cc_an/c_cc2stat_cc_an.dsp 2// Spec Reference: cc2stat cc an 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10imm32 r0, 0x00000000; 11imm32 r1, 0x00000000; 12imm32 r2, 0x00000000; 13imm32 r3, 0x00000000; 14imm32 r4, 0x00000000; 15imm32 r5, 0x00000000; 16imm32 r6, 0x00000000; 17imm32 r7, 0x00000000; 18 19// test CC = AN 0-0, 0-1, 1-0, 1-1 20R7 = 0x00; 21ASTAT = R7; // cc = 0, AN = 0 22CC = AN; // 23R0 = CC; // 24 25R7 = 0x02; 26ASTAT = R7; // cc = 0, AN = 1 27CC = AN; // 28R1 = CC; // 29 30R7 = 0x20; 31ASTAT = R7; // cc = 1, AN = 0 32CC = AN; // 33R2 = CC; // 34 35R7 = 0x22; 36ASTAT = R7; // cc = 1, AN = 1 37CC = AN; // 38R3 = CC; // 39 40// test cc |= AN (0-0, 0-1, 1-0, 1-1) 41R7 = 0x00; 42ASTAT = R7; // cc = 0, AN = 0 43CC |= AN; // 44R4 = CC; // 45 46R7 = 0x02; 47ASTAT = R7; // cc = 0, AN = 1 48CC |= AN; // 49R5 = CC; // 50 51R7 = 0x22; 52ASTAT = R7; // cc = 1, AN = 0 53CC |= AN; // 54R6 = CC; // 55 56R7 = 0x22; 57ASTAT = R7; // cc = 1, AN = 1 58CC |= AN; // 59R7 = CC; // 60 61CHECKREG r0, 0x00000000; 62CHECKREG r1, 0x00000001; 63CHECKREG r2, 0x00000000; 64CHECKREG r3, 0x00000001; 65CHECKREG r4, 0x00000000; 66CHECKREG r5, 0x00000001; 67CHECKREG r6, 0x00000001; 68CHECKREG r7, 0x00000001; 69 70// test CC &= AN (0-0, 0-1, 1-0, 1-1) 71R7 = 0x00; 72ASTAT = R7; // cc = 0, AN = 0 73CC &= AN; // 74R4 = CC; // 75 76R7 = 0x02; 77ASTAT = R7; // cc = 0, AN = 1 78CC &= AN; // 79R5 = CC; // 80 81R7 = 0x20; 82ASTAT = R7; // cc = 1, AN = 0 83CC &= AN; // 84R6 = CC; // 85 86R7 = 0x22; 87ASTAT = R7; // cc = 1, AN = 1 88CC &= AN; // 89R7 = CC; // 90 91CHECKREG r0, 0x00000000; 92CHECKREG r1, 0x00000001; 93CHECKREG r2, 0x00000000; 94CHECKREG r3, 0x00000001; 95CHECKREG r4, 0x00000000; 96CHECKREG r5, 0x00000000; 97CHECKREG r6, 0x00000000; 98CHECKREG r7, 0x00000001; 99 100// test CC ^= AN (0-0, 0-1, 1-0, 1-1) 101R7 = 0x00; 102ASTAT = R7; // cc = 0, AN = 0 103CC ^= AN; // 104R4 = CC; // 105 106R7 = 0x02; 107ASTAT = R7; // cc = 0, AN = 1 108CC ^= AN; // 109R5 = CC; // 110 111R7 = 0x20; 112ASTAT = R7; // cc = 1, AN = 0 113CC ^= AN; // 114R6 = CC; // 115 116R7 = 0x22; 117ASTAT = R7; // cc = 1, AN = 1 118CC ^= AN; // 119R7 = CC; // 120 121 122CHECKREG r0, 0x00000000; 123CHECKREG r1, 0x00000001; 124CHECKREG r2, 0x00000000; 125CHECKREG r3, 0x00000001; 126CHECKREG r4, 0x00000000; 127CHECKREG r5, 0x00000001; 128CHECKREG r6, 0x00000001; 129CHECKREG r7, 0x00000000; 130 131// test AN = CC 0-0, 0-1, 1-0, 1-1 132R7 = 0x00; 133ASTAT = R7; // cc = 0, AN = 0 134AN = CC; // 135R0 = ASTAT; // 136 137R7 = 0x02; 138ASTAT = R7; // cc = 0, AN = 1 139AN = CC; // 140R1 = ASTAT; // 141 142R7 = 0x20; 143ASTAT = R7; // cc = 1, AN = 0 144AN = CC; // 145R2 = ASTAT; // 146 147R7 = 0x22; 148ASTAT = R7; // cc = 1, AN = 1 149AN = CC; // 150R3 = ASTAT; // 151 152// test AN |= CC (0-0, 0-1, 1-0, 1-1) 153R7 = 0x00; 154ASTAT = R7; // cc = 0, AN = 0 155AN |= CC; // 156R4 = ASTAT; // 157 158R7 = 0x02; 159ASTAT = R7; // cc = 0, AN = 1 160AN |= CC; // 161R5 = ASTAT; // 162 163R7 = 0x20; 164ASTAT = R7; // cc = 1, AN = 0 165AN |= CC; // 166R6 = ASTAT; // 167 168R7 = 0x22; 169ASTAT = R7; // cc = 1, AN = 1 170AN |= CC; // 171R7 = ASTAT; // 172 173CHECKREG r0, 0x00000000; 174CHECKREG r1, 0x00000000; 175CHECKREG r2, 0x00000022; 176CHECKREG r3, 0x00000022; 177CHECKREG r4, 0x00000000; 178CHECKREG r5, 0x00000002; 179CHECKREG r6, 0x00000022; 180CHECKREG r7, 0x00000022; 181 182// test AN &= CC (0-0, 0-1, 1-0, 1-1) 183R7 = 0x00; 184ASTAT = R7; // cc = 0, AN = 0 185AN &= CC; // 186R4 = ASTAT; // 187 188R7 = 0x02; 189ASTAT = R7; // cc = 0, AN = 1 190AN &= CC; // 191R5 = ASTAT; // 192 193R7 = 0x20; 194ASTAT = R7; // cc = 1, AN = 0 195AN &= CC; // 196R6 = ASTAT; // 197 198R7 = 0x22; 199ASTAT = R7; // cc = 1, AN = 1 200AN &= CC; // 201R7 = ASTAT; // 202 203CHECKREG r0, 0x00000000; 204CHECKREG r1, 0x00000000; 205CHECKREG r2, 0x00000022; 206CHECKREG r3, 0x00000022; 207CHECKREG r4, 0x00000000; 208CHECKREG r5, 0x00000000; 209CHECKREG r6, 0x00000020; 210CHECKREG r7, 0x00000022; 211 212// test AN ^= CC (0-0, 0-1, 1-0, 1-1) 213R7 = 0x00; 214ASTAT = R7; // cc = 0, AN = 0 215AN ^= CC; // 216R4 = ASTAT; // 217 218R7 = 0x02; 219ASTAT = R7; // cc = 0, AN = 1 220AN ^= CC; // 221R5 = ASTAT; // 222 223R7 = 0x20; 224ASTAT = R7; // cc = 1, AN = 0 225AN ^= CC; // 226R6 = ASTAT; // 227 228R7 = 0x22; 229ASTAT = R7; // cc = 1, AN = 1 230AN ^= CC; // 231R7 = ASTAT; // 232 233CHECKREG r0, 0x00000000; 234CHECKREG r1, 0x00000000; 235CHECKREG r2, 0x00000022; 236CHECKREG r3, 0x00000022; 237CHECKREG r4, 0x00000000; 238CHECKREG r5, 0x00000002; 239CHECKREG r6, 0x00000022; 240CHECKREG r7, 0x00000020; 241 242 243pass 244