1//Original:/testcases/core/c_cc2stat_cc_av0/c_cc2stat_cc_av0.dsp 2// Spec Reference: cc2stat cc av0 3# mach: bfin 4 5#include "test.h" 6 .include "testutils.inc" 7 8 start 9 10 imm32 r0, 0x00000000; 11 imm32 r1, 0x00000000; 12 imm32 r2, 0x00000000; 13 imm32 r3, 0x00000000; 14 imm32 r4, 0x00000000; 15 imm32 r5, 0x00000000; 16 imm32 r6, 0x00000000; 17 imm32 r7, 0x00000000; 18 19// test CC = AV0 0-0, 0-1, 1-0, 1-1 20 R7 = 0x00; 21 ASTAT = R7; // cc = 0, AV0 = 0 22 CC = AV0; // 23 R0 = CC; // 24 25 imm32 R7, _AV0; 26 ASTAT = R7; // cc = 0, AV0 = 1 27 CC = AV0; // 28 R1 = CC; // 29 30 imm32 R7, _CC; 31 ASTAT = R7; // cc = 1, AV0 = 0 32 CC = AV0; // 33 R2 = CC; // 34 35 imm32 R7, (_CC|_AV0); 36 ASTAT = R7; // cc = 1, AV0 = 1 37 CC = AV0; // 38 R3 = CC; // 39 40// test cc |= AV0 (0-0, 0-1, 1-0, 1-1) 41 R7 = 0x00; 42 ASTAT = R7; // cc = 0, AV0 = 0 43 CC |= AV0; // 44 R4 = CC; // 45 46 imm32 R7, _AV0; 47 ASTAT = R7; // cc = 0, AV0 = 1 48 CC |= AV0; // 49 R5 = CC; // 50 51 imm32 R7, (_CC|_AV0); 52 ASTAT = R7; // cc = 1, AV0 = 0 53 CC |= AV0; // 54 R6 = CC; // 55 56 imm32 R7, (_CC|_AV0); 57 ASTAT = R7; // cc = 1, AV0 = 1 58 CC |= AV0; // 59 R7 = CC; // 60 61 CHECKREG r0, _UNSET; 62 CHECKREG r1, _SET; 63 CHECKREG r2, _UNSET; 64 CHECKREG r3, _SET; 65 CHECKREG r4, _UNSET; 66 CHECKREG r5, _SET; 67 CHECKREG r6, _SET; 68 CHECKREG r7, _SET; 69 70// test CC &= AV0 (0-0, 0-1, 1-0, 1-1) 71 R7 = 0x00; 72 ASTAT = R7; // cc = 0, AV0 = 0 73 CC &= AV0; // 74 R4 = CC; // 75 76 imm32 R7, _AV0; 77 ASTAT = R7; // cc = 0, AV0 = 1 78 CC &= AV0; // 79 R5 = CC; // 80 81 imm32 R7, _CC; 82 ASTAT = R7; // cc = 1, AV0 = 0 83 CC &= AV0; // 84 R6 = CC; // 85 86 imm32 R7, (_CC|_AV0); 87 ASTAT = R7; // cc = 1, AV0 = 1 88 CC &= AV0; // 89 R7 = CC; // 90 91 CHECKREG r0, _UNSET; 92 CHECKREG r1, _SET; 93 CHECKREG r2, _UNSET; 94 CHECKREG r3, _SET; 95 CHECKREG r4, _UNSET; 96 CHECKREG r5, _UNSET; 97 CHECKREG r6, _UNSET; 98 CHECKREG r7, _SET; 99 100// test CC ^= AV0 (0-0, 0-1, 1-0, 1-1) 101 R7 = 0x00; 102 ASTAT = R7; // cc = 0, AV0 = 0 103 CC ^= AV0; // 104 R4 = CC; // 105 106 imm32 R7, _AV0; 107 ASTAT = R7; // cc = 0, AV0 = 1 108 CC ^= AV0; // 109 R5 = CC; // 110 111 imm32 R7, _CC; 112 ASTAT = R7; // cc = 1, AV0 = 0 113 CC ^= AV0; // 114 R6 = CC; // 115 116 imm32 R7, (_CC|_AV0); 117 ASTAT = R7; // cc = 1, AV0 = 1 118 CC ^= AV0; // 119 R7 = CC; // 120 121 CHECKREG r0, _UNSET; 122 CHECKREG r1, _SET; 123 CHECKREG r2, _UNSET; 124 CHECKREG r3, _SET; 125 CHECKREG r4, _UNSET; 126 CHECKREG r5, _SET; 127 CHECKREG r6, _SET; 128 CHECKREG r7, _UNSET; 129 130// test AV0 = CC 0-0, 0-1, 1-0, 1-1 131 R7 = 0x00; 132 ASTAT = R7; // cc = 0, AV0 = 0 133 AV0 = CC; // 134 R0 = ASTAT; // 135 136 imm32 R7, _AV0; 137 ASTAT = R7; // cc = 0, AV0 = 1 138 AV0 = CC; // 139 R1 = ASTAT; // 140 141 imm32 R7, _CC; 142 ASTAT = R7; // cc = 1, AV0 = 0 143 AV0 = CC; // 144 R2 = ASTAT; // 145 146 imm32 R7, (_CC|_AV0); 147 ASTAT = R7; // cc = 1, AV0 = 1 148 AV0 = CC; // 149 R3 = ASTAT; // 150 151// test AV0 |= CC (0-0, 0-1, 1-0, 1-1) 152 R7 = 0x00; 153 ASTAT = R7; // cc = 0, AV0 = 0 154 AV0 |= CC; // 155 R4 = ASTAT; // 156 157 imm32 R7, _AV0; 158 ASTAT = R7; // cc = 0, AV0 = 1 159 AV0 |= CC; // 160 R5 = ASTAT; // 161 162 imm32 R7, _CC; 163 ASTAT = R7; // cc = 1, AV0 = 0 164 AV0 |= CC; // 165 R6 = ASTAT; // 166 167 imm32 R7, (_CC|_AV0); 168 ASTAT = R7; // cc = 1, AV0 = 1 169 AV0 |= CC; // 170 R7 = ASTAT; // 171 172 CHECKREG r0, _UNSET; 173 CHECKREG r1, _UNSET; 174 CHECKREG r2, (_CC|_AV0); 175 CHECKREG r3, (_CC|_AV0); 176 CHECKREG r4, _UNSET; 177 CHECKREG r5, _AV0; 178 CHECKREG r6, (_CC|_AV0); 179 CHECKREG r7, (_CC|_AV0); 180 181// test AV0 &= CC (0-0, 0-1, 1-0, 1-1) 182 R7 = 0x00; 183 ASTAT = R7; // cc = 0, AV0 = 0 184 AV0 &= CC; // 185 R4 = ASTAT; // 186 187 imm32 R7, _AV0; 188 ASTAT = R7; // cc = 0, AV0 = 1 189 AV0 &= CC; // 190 R5 = ASTAT; // 191 192 imm32 R7, _CC; 193 ASTAT = R7; // cc = 1, AV0 = 0 194 AV0 &= CC; // 195 R6 = ASTAT; // 196 197 imm32 R7, (_CC|_AV0); 198 ASTAT = R7; // cc = 1, AV0 = 1 199 AV0 &= CC; // 200 R7 = ASTAT; // 201 202 CHECKREG r0, _UNSET; 203 CHECKREG r1, _UNSET; 204 CHECKREG r2, (_CC|_AV0); 205 CHECKREG r3, (_CC|_AV0); 206 CHECKREG r4, _UNSET; 207 CHECKREG r5, _UNSET; 208 CHECKREG r6, (_CC); 209 CHECKREG r7, (_CC|_AV0); 210 211// test AV0 ^= CC (0-0, 0-1, 1-0, 1-1) 212 R7 = 0x00; 213 ASTAT = R7; // cc = 0, AV0 = 0 214 AV0 ^= CC; // 215 R4 = ASTAT; // 216 217 imm32 R7, _AV0; 218 ASTAT = R7; // cc = 0, AV0 = 1 219 AV0 ^= CC; // 220 R5 = ASTAT; // 221 222 imm32 R7, _CC; 223 ASTAT = R7; // cc = 1, AV0 = 0 224 AV0 ^= CC; // 225 R6 = ASTAT; // 226 227 imm32 R7, (_CC|_AV0); 228 ASTAT = R7; // cc = 1, AV0 = 1 229 AV0 ^= CC; // 230 R7 = ASTAT; // 231 232 CHECKREG r0, _UNSET; 233 CHECKREG r1, _UNSET; 234 CHECKREG r2, (_CC|_AV0); 235 CHECKREG r3, (_CC|_AV0); 236 CHECKREG r4, _UNSET; 237 CHECKREG r5, _AV0; 238 CHECKREG r6, (_CC|_AV0); 239 CHECKREG r7, _CC; 240 241 pass 242