1//Original:/proj/frio/dv/testcases/core/c_cc_regmvlogi_mvbrsft_sn/c_cc_regmvlogi_mvbrsft_sn.dsp
2// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft)
3# mach: bfin
4
5#include "test.h"
6.include "testutils.inc"
7	start
8
9	INIT_I_REGS 0;
10	INIT_M_REGS 0;
11	INIT_L_REGS 0;
12	INIT_B_REGS 0;
13	INIT_R_REGS 0;
14	INIT_P_REGS 0;
15	ASTAT = R0;
16	A0 = A1 = 0;
17
18	imm32 r0, (_CC);	// cc=1
19	imm32 r1, 0x00000000;	// cc=0
20	imm32 r2, 0x62b61557;
21	imm32 r3, 0x07300007;
22	imm32 r4, 0x00740088;
23	imm32 r5, 0x609950aa;
24	imm32 r6, 0x20bb06cc;
25	imm32 r7, 0x00000002;
26
27	A0 = R4;
28	A1 = R6;
29
30	ASTAT = R0;	// cc=1  REGMV
31	P2 = R2;
32	R2 = R0 + R2;	// comp3op dr plus dr
33	M0 = P2;	// regmv
34	IF CC R1 = R3;	// ccmov
35	ASTAT = R1;	// cc=0  REGMV
36	R3 >>= R7;	// alu2op sft
37	R3 = R0 + R2;	// comp3op dr plus dr
38	I0 = R5;
39	IF CC R3 = R2;	// ccmv
40	CC = R0 < R1;	// ccflag
41	R3.H = R1.L + R3.H (S);	// dsp32alu
42	R5 = ( A1 = R7.L * R4.H ),  R4 = ( A0 = R7.H * R4.L );	// dsp32mac pair
43	IF CC R4 = R5;	// ccmv
44	CC = ! BITTST( R0 , 4 );	// cc = 0
45	R0 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR);	// dsp32alu sft
46	I0 += 2;	// dagmodim
47	IF CC R4 = R5;	// ccmv
48	CC = BITTST ( R1 , 4 );	// cc = 0
49	R7.L = R5.L << 1;	// dsp32shiftim
50	R1 = R0 +|- R1 , R5 = R0 -|+ R1 (ASR);	// dsp32alu sft
51	P1 = A0.w;
52	IF !CC JUMP LABEL1;	// branch
53	CC = ! CC;
54	R1 = ( A1 = R7.L * R4.L ),  R0 = ( A0 = R7.H * R4.H )  (S2RND);	// dsp32mac pair
55	I0 += M0;	// dagmodim
56	P2 = A1.w;
57	IF !CC JUMP LABEL2 (BP);	// branch
58LABEL1:
59	R2 = R0 + R2;
60	JUMP.S END;
61LABEL2:
62	R7 = R5 - R3;
63	CC = R0 < R1;	// ccflag
64	R6 = R0 + R2;	// comp3op dr plus dr
65	P4 = I0;
66	IF CC JUMP END (BP);	// branch on
67	R7 = R5 + R7;
68
69END:
70
71	CHECKREG r0, 0x0398000C;
72	CHECKREG r1, 0x05640002;
73	CHECKREG r2, 0x664E1583;
74	CHECKREG r3, 0x62BD1597;
75	CHECKREG r4, 0x000001D0;
76	CHECKREG r5, 0xFE340009;
77	CHECKREG r6, 0xFC680013;
78	CHECKREG r7, 0x000003A0;
79	CHECKREG p1, 0x00000000;
80	CHECKREG p2, 0x62B61557;
81	CHECKREG p4, 0x00000000;
82
83	imm32 r0, (_CC);
84	imm32 r1, 0x00000000;
85	imm32 r2, 0x62661557;
86	imm32 r3, 0x073b0007;
87	imm32 r4, 0x01f49088;
88	imm32 r5, 0x6e2959aa;
89	imm32 r6, 0xa0b506cc;
90	imm32 r7, 0xabd30002;
91
92	A1 = A0 = 0;
93	ASTAT = R0;	// cc=1  REGMV
94	R2.H = R3.L + R4.L (NS);	// dsp32alu
95	R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L;	// dsp32mac
96	R3 = ROT R2 BY 1;	// dsp32shiftim_rot
97	ASTAT = R1;	// cc=0  REGMV
98	A1 += R2.L * R3.L, A0 += R2.L * R3.H;	// dsp32mac
99	R2.L = R5.L << 1;	// dsp32shiftimm
100	R5 = ROT R3 BY 1;	// dsp32shiftim_rot
101	CC = ! BITTST( R0 , 4 );	// cc = 0
102	R4.L = R5.L << 1;	// dsp32shiftimm
103	R0 >>= R7;	// alu2op sft
104	A0 += A1;	// dsp32alu a0 + a1
105	R6 = ROT R4 BY 5;	// dsp32shiftim_rot
106	CC = BITTST ( R1 , 4 );	// cc = 0
107	R0 = R0 + R2;	// comp3op dr plus dr
108	R5 = R3.L * R4.H, R4 = R3.H * R4.L;	// dsp32mult
109	P1 = A0.w;
110	IF CC R4 = R5;	// ccmov
111	P1.L = 0x3000;	// ldimmhalf
112	P2 = A1.w;	// regmv
113	CC = BITTST ( R0 , 4 );	// cc = 1
114	R7 = ROT R6 BY R7.L;
115
116	CHECKREG r0, 0x0001B354;
117	CHECKREG r1, 0x00000000;
118	CHECKREG r2, 0x0001B354;
119	CHECKREG r3, 0x00022AAF;
120	CHECKREG r4, 0xFFFEAAF0;
121	CHECKREG r5, 0x00A6BB98;
122	CHECKREG r6, 0x3E955790;
123	CHECKREG r7, 0xFA555E42;
124	CHECKREG p1, 0x07193000;
125	CHECKREG p2, 0x071EE3B4;
126
127	pass
128