1//Original:/testcases/core/c_dsp32alu_r_negneg/c_dsp32alu_r_negneg.dsp 2// Spec Reference: dsp32alu dregs = neg / neg dregs 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10 11imm32 r0, 0xa5678911; 12imm32 r1, 0x2789ab1d; 13imm32 r2, 0x3b44b515; 14imm32 r3, 0x46667717; 15imm32 r4, 0x5567891b; 16imm32 r5, 0x6789ab1d; 17imm32 r6, 0x74445515; 18imm32 r7, 0x86667777; 19R0 = - R0 (V); 20R1 = - R1 (V); 21R2 = - R2 (V); 22R3 = - R3 (V); 23R4 = - R4 (V); 24R5 = - R5 (V); 25R6 = - R6 (V); 26R7 = - R7 (V); 27CHECKREG r0, 0x5A9976EF; 28CHECKREG r1, 0xD87754E3; 29CHECKREG r2, 0xC4BC4AEB; 30CHECKREG r3, 0xB99A88E9; 31CHECKREG r4, 0xAA9976E5; 32CHECKREG r5, 0x987754E3; 33CHECKREG r6, 0x8BBCAAEB; 34CHECKREG r7, 0x799A8889; 35 36imm32 r0, 0xa567892b; 37imm32 r1, 0x2789ab2d; 38imm32 r2, 0x344d5525; 39imm32 r3, 0xd6667727; 40imm32 r4, 0x58889929; 41imm32 r5, 0x6aaabb2b; 42imm32 r6, 0x7ccfdd2d; 43imm32 r7, 0x8eeeffff; 44R1 = - R0 (V); 45R2 = - R1 (V); 46R3 = - R2 (V); 47R4 = - R3 (V); 48R5 = - R4 (V); 49R6 = - R5 (V); 50R7 = - R6 (V); 51R0 = - R7 (V); 52CHECKREG r0, 0xA567892B; 53CHECKREG r1, 0x5A9976D5; 54CHECKREG r2, 0xA567892B; 55CHECKREG r3, 0x5A9976D5; 56CHECKREG r4, 0xA567892B; 57CHECKREG r5, 0x5A9976D5; 58CHECKREG r6, 0xA567892B; 59CHECKREG r7, 0x5A9976D5; 60 61imm32 r0, 0xb5678941; 62imm32 r1, 0x2789ab5d; 63imm32 r2, 0x34445565; 64imm32 r3, 0xe6667777; 65imm32 r4, 0x5567898b; 66imm32 r5, 0x6789ab9d; 67imm32 r6, 0xc4445505; 68imm32 r7, 0x8666b777; 69R2 = - R0 (V); 70R3 = - R1 (V); 71R4 = - R2 (V); 72R5 = - R3 (V); 73R6 = - R4 (V); 74R7 = - R5 (V); 75R0 = - R6 (V); 76R1 = - R7 (V); 77CHECKREG r0, 0xB5678941; 78CHECKREG r1, 0x2789AB5D; 79CHECKREG r2, 0x4A9976BF; 80CHECKREG r3, 0xD87754A3; 81CHECKREG r4, 0xB5678941; 82CHECKREG r5, 0x2789AB5D; 83CHECKREG r6, 0x4A9976BF; 84CHECKREG r7, 0xD87754A3; 85 86 87 88pass 89