1//Original:/testcases/core/c_dsp32mac_dr_a0_is/c_dsp32mac_dr_a0_is.dsp 2// Spec Reference: dsp32mac dr a0 is (scale by 2.0 signed fraction with round) 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10 11A1 = A0 = 0; 12 13// The result accumulated in A , and stored to a reg half 14imm32 r0, 0xf3545abd; 15imm32 r1, 0x7fbcfec7; 16imm32 r2, 0xc7fff679; 17imm32 r3, 0xd0799007; 18imm32 r4, 0xefb79f69; 19imm32 r5, 0xcd35700b; 20imm32 r6, 0xe00c87fd; 21imm32 r7, 0xf78e909f; 22A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (ISS2); 23R1 = A0.w; 24A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (ISS2); 25R3 = A0.w; 26A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (ISS2); 27R5 = A0.w; 28A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (ISS2); 29R7 = A0.w; 30CHECKREG r0, 0xF3548000; 31CHECKREG r1, 0xFF910EEB; 32CHECKREG r2, 0xC7FF8000; 33CHECKREG r3, 0xE71226F2; 34CHECKREG r4, 0xEFB78000; 35CHECKREG r5, 0xEA4D52D5; 36CHECKREG r6, 0xE00C8000; 37CHECKREG r7, 0xEE42DC2B; 38 39// The result accumulated in A , and stored to a reg half (MNOP) 40imm32 r0, 0xc5548abd; 41imm32 r1, 0x9b5cfec7; 42imm32 r2, 0xa9b55679; 43imm32 r3, 0xb09b5007; 44imm32 r4, 0xcfb9b5c9; 45imm32 r5, 0x52359b5c; 46imm32 r6, 0xe50c5098; 47imm32 r7, 0x675e7509; 48R0.L = ( A0 -= R1.L * R0.L ) (ISS2); 49R1 = A0.w; 50R2.L = ( A0 += R2.L * R3.H ) (ISS2); 51R3 = A0.w; 52R4.L = ( A0 = R4.H * R5.L ) (ISS2); 53R5 = A0.w; 54R6.L = ( A0 -= R6.H * R7.H ) (ISS2); 55R7 = A0.w; 56CHECKREG r0, 0xC5548000; 57CHECKREG r1, 0xEDB37D40; 58CHECKREG r2, 0xA9B58000; 59CHECKREG r3, 0xD2E20883; 60CHECKREG r4, 0xCFB97FFF; 61CHECKREG r5, 0x12FAA97C; 62CHECKREG r6, 0xE50C7FFF; 63CHECKREG r7, 0x1DDCBB14; 64 65// The result accumulated in A , and stored to a reg half (MNOP) 66imm32 r0, 0x4b54babd; 67imm32 r1, 0x12346ec7; 68imm32 r2, 0xa4bbe679; 69imm32 r3, 0x8abdb707; 70imm32 r4, 0x9f4b7b69; 71imm32 r5, 0xa234877b; 72imm32 r6, 0xb00c4887; 73imm32 r7, 0xc78ea4b8; 74R0.L = ( A0 = R1.L * R0.L ) (ISS2); 75R1 = A0.w; 76R2.L = ( A0 -= R2.H * R3.L ) (ISS2); 77R3 = A0.w; 78R4.L = ( A0 = R4.H * R5.H ) (ISS2); 79R5 = A0.w; 80R6.L = ( A0 += R6.L * R7.H ) (ISS2); 81R7 = A0.w; 82CHECKREG r0, 0x4B548000; 83CHECKREG r1, 0xE2075EEB; 84CHECKREG r2, 0xA4BB8000; 85CHECKREG r3, 0xC80330CE; 86CHECKREG r4, 0x9F4B7FFF; 87CHECKREG r5, 0x236ED13C; 88CHECKREG r6, 0xB00C7FFF; 89CHECKREG r7, 0x1370FD1E; 90 91// The result accumulated in A , and stored to a reg half 92imm32 r0, 0x1a545abd; 93imm32 r1, 0x42fcfec7; 94imm32 r2, 0xc53f5679; 95imm32 r3, 0x9c64f007; 96imm32 r4, 0xafc7ec69; 97imm32 r5, 0xd23c891b; 98imm32 r6, 0xc00cc602; 99imm32 r7, 0x678edc7e; 100A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (ISS2); 101R3 = A0.w; 102A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (ISS2); 103R7 = A0.w; 104A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (ISS2); 105R5 = A0.w; 106A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (ISS2); 107R1 = A0.w; 108CHECKREG r0, 0x1A548000; 109CHECKREG r1, 0xF0477293; 110CHECKREG r2, 0xC53F7FFF; 111CHECKREG r3, 0x13020C09; 112CHECKREG r4, 0xAFC78000; 113CHECKREG r5, 0xEEE57293; 114CHECKREG r6, 0xC00C8000; 115CHECKREG r7, 0xFD3CE337; 116 117 118 119pass 120