1//Original:/testcases/core/c_dsp32mac_dr_a0_m/c_dsp32mac_dr_a0_m.dsp 2// Spec Reference: dsp32mac dr_a0 m 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10 11imm32 r0, 0xab235675; 12imm32 r1, 0xcfba5127; 13imm32 r2, 0x13246705; 14imm32 r3, 0x00060007; 15imm32 r4, 0x90abcd09; 16imm32 r5, 0x10acefdb; 17imm32 r6, 0x000c000d; 18imm32 r7, 0x1246700f; 19 20A1 = A0 = 0; 21 22// The result accumulated in A1 , and stored to a reg half 23imm32 r0, 0x13545abd; 24imm32 r1, 0xadbcfec7; 25imm32 r2, 0xa1245679; 26imm32 r3, 0x00060007; 27imm32 r4, 0xefbc4569; 28imm32 r5, 0x1235000b; 29imm32 r6, 0x000c000d; 30imm32 r7, 0x678e000f; 31A1 -= R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ); 32R1 = A0.w; 33A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ); 34R3 = A0.w; 35A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ); 36R5 = A0.w; 37A1 = R6.H * R7.H, R6.L = ( A0 = R6.L * R7.H ); 38R7 = A0.w; 39CHECKREG r0, 0x1354FF22; 40CHECKREG r1, 0xFF221DD6; 41CHECKREG r2, 0xA124FF27; 42CHECKREG r3, 0xFF274DDE; 43CHECKREG r4, 0xEFBCFCD7; 44CHECKREG r5, 0xFCD701B6; 45CHECKREG r6, 0x000C000B; 46CHECKREG r7, 0x000A846C; 47 48// The result accumulated in A1, and stored to a reg half (MNOP) 49imm32 r0, 0x13545abd; 50imm32 r1, 0xadbcfec7; 51imm32 r2, 0xa1245679; 52imm32 r3, 0x00060007; 53imm32 r4, 0xefbc4569; 54imm32 r5, 0x1235000b; 55imm32 r6, 0x000c000d; 56imm32 r7, 0x678e000f; 57R0.L = ( A0 += R6.L * R7.L ); 58R1 = A0.w; 59R2.L = ( A0 -= R2.L * R3.H ); 60R3 = A0.w; 61R4.L = ( A0 += R4.H * R5.L ); 62R5 = A0.w; 63R6.L = ( A0 = R0.H * R1.H ); 64R7 = A0.w; 65CHECKREG r0, 0x1354000B; 66CHECKREG r1, 0x000A85F2; 67CHECKREG r2, 0xA1240006; 68CHECKREG r3, 0x00067846; 69CHECKREG r4, 0xEFBC0005; 70CHECKREG r5, 0x0005126E; 71CHECKREG r6, 0x000C0002; 72CHECKREG r7, 0x00018290; 73 74// The result accumulated in A1 , and stored to a reg half (MNOP) 75imm32 r0, 0x13545abd; 76imm32 r1, 0xadbcfec7; 77imm32 r2, 0xa1245679; 78imm32 r3, 0x00060007; 79imm32 r4, 0xefbc4569; 80imm32 r5, 0x1235000b; 81imm32 r6, 0x000c000d; 82imm32 r7, 0x678e000f; 83R0.L = ( A0 = R1.L * R0.L ); 84R1 = A0.w; 85R2.L = ( A0 += R2.H * R3.L ); 86R3 = A0.w; 87R4.L = ( A0 += R4.H * R5.H ); 88R5 = A0.w; 89R6.L = ( A0 += R6.L * R7.H ); 90R7 = A0.w; 91CHECKREG r0, 0x1354FF22; 92CHECKREG r1, 0xFF221DD6; 93CHECKREG r2, 0xA124FF1D; 94CHECKREG r3, 0xFF1CEDCE; 95CHECKREG r4, 0xEFBCFCCD; 96CHECKREG r5, 0xFCCCA1A6; 97CHECKREG r6, 0x000CFCD7; 98CHECKREG r7, 0xFCD72612; 99 100// The result accumulated in A1 , and stored to a reg half 101imm32 r0, 0x13545abd; 102imm32 r1, 0xadbcfec7; 103imm32 r2, 0xa1245679; 104imm32 r3, 0x00060007; 105imm32 r4, 0xefbc4569; 106imm32 r5, 0x1235000b; 107imm32 r6, 0x000c000d; 108imm32 r7, 0x678e000f; 109A1 = R1.L * R0.L (M), R6.L = ( A0 -= R1.L * R0.L ); 110R7 = A0.w; 111A1 -= R2.L * R3.H (M), R2.L = ( A0 += R2.H * R3.L ); 112R3 = A0.w; 113A1 = R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ); 114R5 = A0.w; 115A1 -= R6.H * R7.H (M), R0.L = ( A0 = R6.L * R7.H ); 116R1 = A0.w; 117CHECKREG r0, 0x1354000B; 118CHECKREG r1, 0x000A83F2; 119CHECKREG r2, 0xA124FDB0; 120CHECKREG r3, 0xFDAFD834; 121CHECKREG r4, 0xEFBCFDB0; 122CHECKREG r5, 0xFDAFB3D8; 123CHECKREG r6, 0x000CFDB5; 124CHECKREG r7, 0xFDB5083C; 125 126 127pass 128