1//Original:/testcases/core/c_dsp32mac_dr_a0_t/c_dsp32mac_dr_a0_t.dsp
2// Spec Reference: dsp32mac dr a0 t (truncation)
3# mach: bfin
4
5.include "testutils.inc"
6	start
7
8
9
10
11A1 = A0 = 0;
12
13// The result accumulated in A , and stored to a reg half
14imm32 r0, 0xa3545abd;
15imm32 r1, 0xbdbcfec7;
16imm32 r2, 0xc1248679;
17imm32 r3, 0xd0069007;
18imm32 r4, 0xefbc4569;
19imm32 r5, 0xcd35500b;
20imm32 r6, 0xe00c800d;
21imm32 r7, 0xf78e900f;
22A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (T);
23R1 = A0.w;
24A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (T);
25R3 = A0.w;
26A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (T);
27R5 = A0.w;
28A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (T);
29R7 = A0.w;
30CHECKREG r0, 0xA354FF22;
31CHECKREG r1, 0xFF221DD6;
32CHECKREG r2, 0xC12436FD;
33CHECKREG r3, 0x36FD0FF8;
34CHECKREG r4, 0xEFBC3D71;
35CHECKREG r5, 0x3D716BD0;
36CHECKREG r6, 0xE00C45E2;
37CHECKREG r7, 0x45E2903C;
38
39// The result accumulated in A , and stored to a reg half (MNOP)
40imm32 r0, 0x63548abd;
41imm32 r1, 0x7dbcfec7;
42imm32 r2, 0xa1245679;
43imm32 r3, 0xb0069007;
44imm32 r4, 0xcfbc4569;
45imm32 r5, 0xd235c00b;
46imm32 r6, 0xe00ca00d;
47imm32 r7, 0x678e700f;
48R0.L = ( A0 = R1.L * R0.L ) (T);
49R1 = A0.w;
50R2.L = ( A0 += R2.L * R3.H ) (T);
51R3 = A0.w;
52R4.L = ( A0 -= R4.H * R5.L ) (T);
53R5 = A0.w;
54R6.L = ( A0 = R6.H * R7.H ) (T);
55R7 = A0.w;
56CHECKREG r0, 0x6354011E;
57CHECKREG r1, 0x011EBDD6;
58CHECKREG r2, 0xA124CB17;
59CHECKREG r3, 0xCB172B82;
60CHECKREG r4, 0xCFBCB2F9;
61CHECKREG r5, 0xB2F9515A;
62CHECKREG r6, 0xE00CE626;
63CHECKREG r7, 0xE6263550;
64
65// The result accumulated in A , and stored to a reg half (MNOP)
66imm32 r0, 0x5354babd;
67imm32 r1, 0x6dbcdec7;
68imm32 r2, 0x7124e679;
69imm32 r3, 0x80067007;
70imm32 r4, 0x9fbc4569;
71imm32 r5, 0xa235900b;
72imm32 r6, 0xb00c300d;
73imm32 r7, 0xc78ea00f;
74R0.L = ( A0 -= R1.L * R0.L ) (T);
75R1 = A0.w;
76R2.L = ( A0 = R2.H * R3.L ) (T);
77R3 = A0.w;
78R4.L = ( A0 -= R4.H * R5.H ) (T);
79R5 = A0.w;
80R6.L = ( A0 += R6.L * R7.H ) (T);
81R7 = A0.w;
82CHECKREG r0, 0x5354D42C;
83CHECKREG r1, 0xD42C177A;
84CHECKREG r2, 0x71246305;
85CHECKREG r3, 0x6305AFF8;
86CHECKREG r4, 0x9FBC1C7B;
87CHECKREG r5, 0x1C7B9C20;
88CHECKREG r6, 0xB00C074B;
89CHECKREG r7, 0x074B208C;
90
91// The result accumulated in A , and stored to a reg half
92imm32 r0, 0x33545abd;
93imm32 r1, 0x5dbcfec7;
94imm32 r2, 0x71245679;
95imm32 r3, 0x90060007;
96imm32 r4, 0xafbc4569;
97imm32 r5, 0xd235900b;
98imm32 r6, 0xc00ca00d;
99imm32 r7, 0x678ed00f;
100A1 = R1.L * R0.L (M), R0.L = ( A0 += R1.L * R0.L ) (T);
101R1 = A0.w;
102A1 += R2.L * R3.H (M), R2.L = ( A0 -= R2.H * R3.L ) (T);
103R3 = A0.w;
104A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (T);
105R5 = A0.w;
106A1 -= R6.H * R7.H (M), R6.L = ( A0 += R6.L * R7.H ) (T);
107R7 = A0.w;
108CHECKREG r0, 0x3354066D;
109CHECKREG r1, 0x066D3E62;
110CHECKREG r2, 0x71240667;
111CHECKREG r3, 0x06670E6A;
112CHECKREG r4, 0xAFBC1CB7;
113CHECKREG r5, 0x1CB733D8;
114CHECKREG r6, 0xC00CCF17;
115CHECKREG r7, 0xCF173844;
116
117
118
119pass
120