1//Original:/testcases/core/c_dsp32mac_dr_a0_u/c_dsp32mac_dr_a0_u.dsp 2// Spec Reference: dsp32mac dr a0 u (unsigned fraction and unsigned int) 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10 11A1 = A0 = 0; 12 13// The result accumulated in A , and stored to a reg half 14imm32 r0, 0xa3545abd; 15imm32 r1, 0x9abcfec7; 16imm32 r2, 0xc9a48679; 17imm32 r3, 0xd09a9007; 18imm32 r4, 0xefb9a569; 19imm32 r5, 0xcd359a0b; 20imm32 r6, 0xe00c89ad; 21imm32 r7, 0xf78e909a; 22A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (FU); 23R1 = A0.w; 24A1 = R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (FU); 25R3 = A0.w; 26A1 -= R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (FU); 27R5 = A0.w; 28A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (FU); 29R7 = A0.w; 30CHECKREG r0, 0xA3545A4E; 31CHECKREG r1, 0x5A4E0EEB; 32CHECKREG r2, 0xC9A40000; 33CHECKREG r3, 0x00000000; 34CHECKREG r4, 0xEFB9C029; 35CHECKREG r5, 0xC028C64D; 36CHECKREG r6, 0xE00CFFFF; 37CHECKREG r7, 0x454B0F43; 38 39// The result accumulated in A , and stored to a reg half (MNOP) 40imm32 r0, 0xb8548abd; 41imm32 r1, 0x7b8cfec7; 42imm32 r2, 0xa1b85679; 43imm32 r3, 0xb00b8007; 44imm32 r4, 0xcfbcb869; 45imm32 r5, 0xd235cb8b; 46imm32 r6, 0xe00ca0b8; 47imm32 r7, 0x678e700b; 48R0.L = ( A0 = R1.L * R0.L ) (FU); 49R1 = A0.w; 50R2.L = ( A0 += R2.L * R3.H ) (FU); 51R3 = A0.w; 52R4.L = ( A0 -= R4.H * R5.L ) (FU); 53R5 = A0.w; 54R6.L = ( A0 = R6.H * R7.H ) (FU); 55R7 = A0.w; 56CHECKREG r0, 0xB8548A13; 57CHECKREG r1, 0x8A135EEB; 58CHECKREG r2, 0xA1B8C58A; 59CHECKREG r3, 0xC58A461E; 60CHECKREG r4, 0xCFBC205F; 61CHECKREG r5, 0x205F670A; 62CHECKREG r6, 0xE00C5AA1; 63CHECKREG r7, 0x5AA11AA8; 64 65// The result accumulated in A , and stored to a reg half (MNOP) 66imm32 r0, 0x7b54babd; 67imm32 r1, 0xb7bcdec7; 68imm32 r2, 0xab7be679; 69imm32 r3, 0x8ab7b007; 70imm32 r4, 0x9fab7b69; 71imm32 r5, 0xa23ab7bb; 72imm32 r6, 0xb00cab7b; 73imm32 r7, 0xc78eaab7; 74R0.L = ( A0 = R1.L * R0.L ) (FU); 75R1 = A0.w; 76R2.L = ( A0 -= R2.H * R3.L ) (FU); 77R3 = A0.w; 78R4.L = ( A0 = R4.H * R5.H ) (FU); 79R5 = A0.w; 80R6.L = ( A0 += R6.L * R7.H ) (FU); 81R7 = A0.w; 82CHECKREG r0, 0x7B54A281; 83CHECKREG r1, 0xA2810EEB; 84CHECKREG r2, 0xAB7B2C98; 85CHECKREG r3, 0x2C97CE8E; 86CHECKREG r4, 0x9FAB652E; 87CHECKREG r5, 0x652E62BE; 88CHECKREG r6, 0xB00CEADA; 89CHECKREG r7, 0xEADA1DF8; 90 91// The result accumulated in A , and stored to a reg half 92imm32 r0, 0xea545abd; 93imm32 r1, 0x5eacfec7; 94imm32 r2, 0xc1ea5679; 95imm32 r3, 0x9c0ea007; 96imm32 r4, 0xafccea69; 97imm32 r5, 0xd23c9eab; 98imm32 r6, 0xc00cc0ea; 99imm32 r7, 0x678edc0e; 100A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (FU); 101R3 = A0.w; 102A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (FU); 103R7 = A0.w; 104A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (FU); 105R5 = A0.w; 106A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (FU); 107R1 = A0.w; 108CHECKREG r0, 0xEA540484; 109CHECKREG r1, 0x04840000; 110CHECKREG r2, 0xC1EAFFFF; 111CHECKREG r3, 0x45282CE3; 112CHECKREG r4, 0xAFCC0000; 113CHECKREG r5, 0x00000000; 114CHECKREG r6, 0xC00C2200; 115CHECKREG r7, 0x22002A7E; 116 117 118 119pass 120