1//Original:/testcases/core/c_dsp32mac_dr_a1_tu/c_dsp32mac_dr_a1_tu.dsp
2// Spec Reference: dsp32mac dr_a1 tu (truncate signed fraction)
3# mach: bfin
4
5.include "testutils.inc"
6	start
7
8
9
10
11A1 = A0 = 0;
12
13// The result accumulated in A1 , and stored to a reg half
14imm32 r0, 0xa3545abd;
15imm32 r1, 0xbdbcfec7;
16imm32 r2, 0xc1248679;
17imm32 r3, 0xd0069007;
18imm32 r4, 0xefbc4569;
19imm32 r5, 0xcd35500b;
20imm32 r6, 0xe00c800d;
21imm32 r7, 0xf78e900f;
22R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (TFU);
23R1 = A1.w;
24R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (TFU);
25R3 = A1.w;
26R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (TFU);
27R5 = A1.w;
28R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (TFU);
29R7 = A1.w;
30CHECKREG r0, 0x5A4E5ABD;
31CHECKREG r1, 0x5A4E0EEB;
32CHECKREG r2, 0x00008679;
33CHECKREG r3, 0x00000000;
34CHECKREG r4, 0x4AF54569;
35CHECKREG r5, 0x4AF50D14;
36CHECKREG r6, 0xFFFF800D;
37CHECKREG r7, 0x239CE7BC;
38
39// The result accumulated in A1, and stored to a reg half (MNOP)
40imm32 r0, 0x63548abd;
41imm32 r1, 0x7dbcfec7;
42imm32 r2, 0xC5885679;
43imm32 r3, 0xC5880000;
44imm32 r4, 0xcfbc4569;
45imm32 r5, 0xd235c00b;
46imm32 r6, 0xe00ca00d;
47imm32 r7, 0x678e700f;
48R0.H = ( A1 = R1.L * R0.L ) (TFU);
49R1 = A1.w;
50R2.H = ( A1 += R2.L * R3.H ) (TFU);
51R3 = A1.w;
52R4.H = ( A1 -= R4.H * R5.L ) (TFU);
53R5 = A1.w;
54R6.H = ( A1 = R6.H * R7.H ) (TFU);
55R7 = A1.w;
56CHECKREG r0, 0x8A138ABD;
57CHECKREG r1, 0x8A135EEB;
58CHECKREG r2, 0xCCCC5679;
59CHECKREG r3, 0xCCCC6C33;
60CHECKREG r4, 0x30F64569;
61CHECKREG r5, 0x30F67F1F;
62CHECKREG r6, 0x5AA1A00D;
63CHECKREG r7, 0x5AA11AA8;
64
65// The result accumulated in A1 , and stored to a reg half (MNOP)
66imm32 r0, 0x5354babd;
67imm32 r1, 0x6dbcdec7;
68imm32 r2, 0x7124e679;
69imm32 r3, 0x80067007;
70imm32 r4, 0x9fbc4569;
71imm32 r5, 0xa235900b;
72imm32 r6, 0xb00c300d;
73imm32 r7, 0xc78ea00f;
74 R0.H = A1 , A0 -= R1.L * R0.L (TFU);
75R1 = A1.w;
76 R2.H = A1 , A0 += R2.H * R3.L (TFU);
77R3 = A1.w;
78 R4.H = A1 , A0 -= R4.H * R5.H (TFU);
79R5 = A1.w;
80 R6.H = A1 , A0 = R6.L * R7.H (TFU);
81R7 = A1.w;
82CHECKREG r0, 0x5AA1BABD;
83CHECKREG r1, 0x5AA11AA8;
84CHECKREG r2, 0x5AA1E679;
85CHECKREG r3, 0x5AA11AA8;
86CHECKREG r4, 0x5AA14569;
87CHECKREG r5, 0x5AA11AA8;
88CHECKREG r6, 0x5AA1300D;
89CHECKREG r7, 0x5AA11AA8;
90
91// The result accumulated in A1 , and stored to a reg half
92imm32 r0, 0x33545abd;
93imm32 r1, 0x5dbcfec7;
94imm32 r2, 0x71245679;
95imm32 r3, 0x90060007;
96imm32 r4, 0xafbc4569;
97imm32 r5, 0xd235900b;
98imm32 r6, 0xc00ca00d;
99imm32 r7, 0x678ed00f;
100R0.H = ( A1 = R1.L * R0.L ) (M), A0 -= R1.L * R0.L (TFU);
101R1 = A1.w;
102R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (TFU);
103R3 = A1.w;
104R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (TFU);
105R5 = A1.w;
106R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (TFU);
107R7 = A1.w;
108CHECKREG r0, 0xFF915ABD;
109CHECKREG r1, 0xFF910EEB;
110CHECKREG r2, 0x30375679;
111CHECKREG r3, 0x303725C1;
112CHECKREG r4, 0x5D604569;
113CHECKREG r5, 0x5D60D8AD;
114CHECKREG r6, 0x4382A00D;
115CHECKREG r7, 0x43823355;
116
117// The result accumulated in A1 MM=0, and stored to a reg half (MNOP)
118imm32 r0, 0x92005ABD;
119imm32 r1, 0x09300000;
120imm32 r2, 0x56749679;
121imm32 r3, 0x30A95000;
122imm32 r4, 0xa0009669;
123imm32 r5, 0x01000970;
124imm32 r6, 0xdf45609D;
125imm32 r7, 0x12345679;
126R0.H = ( A1 += R1.L * R0.L ) (M,TFU);
127R1 = A1.w;
128R2.H = ( A1 -= R2.L * R3.H ) (M,TFU);
129R3 = A1.w;
130R4.H = ( A1 = R4.H * R5.L ) (M,TFU);
131R5 = A1.w;
132R6.H = ( A1 -= R6.H * R7.H ) (M,TFU);
133R7 = A1.w;
134CHECKREG r0, 0x43825ABD;
135CHECKREG r1, 0x43823355;
136CHECKREG r2, 0x57919679;
137CHECKREG r3, 0x57912D74;
138CHECKREG r4, 0xFC769669;
139CHECKREG r5, 0xFC760000;
140CHECKREG r6, 0xFEC9609D;
141CHECKREG r7, 0xFEC9CBFC;
142
143
144
145pass
146