1//Original:/testcases/core/c_dsp32shift_fdepx/c_dsp32shift_fdepx.dsp 2// Spec Reference: dsp32shift fdep x 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8imm32 r0, 0x00000001; 9imm32 r1, 0x01000801; 10imm32 r2, 0x08200802; 11imm32 r3, 0x08030803; 12imm32 r4, 0x08004804; 13imm32 r5, 0x08000505; 14imm32 r6, 0x08000866; 15imm32 r7, 0x08000807; 16R1 = DEPOSIT( R1, R0 ); 17R2 = DEPOSIT( R2, R0 ); 18R3 = DEPOSIT( R3, R0 ); 19R4 = DEPOSIT( R4, R0 ) (X); 20R5 = DEPOSIT( R5, R0 ); 21R6 = DEPOSIT( R6, R0 ); 22R7 = DEPOSIT( R7, R0 ) (X); 23R0 = DEPOSIT( R0, R0 ); 24CHECKREG r0, 0x00000000; 25CHECKREG r1, 0x01000800; 26CHECKREG r2, 0x08200802; 27CHECKREG r3, 0x08030802; 28CHECKREG r4, 0x00000000; 29CHECKREG r5, 0x08000504; 30CHECKREG r6, 0x08000866; 31CHECKREG r7, 0x00000000; 32 33imm32 r0, 0x0900d001; 34imm32 r1, 0x09000002; 35imm32 r2, 0x09000002; 36imm32 r3, 0x09100003; 37imm32 r4, 0x09020004; 38imm32 r5, 0x09003005; 39imm32 r6, 0x09000406; 40imm32 r7, 0x09000057; 41R0 = DEPOSIT( R0, R1 ); 42R2 = DEPOSIT( R2, R1 ); 43R3 = DEPOSIT( R3, R1 ); 44R4 = DEPOSIT( R4, R1 ); 45R5 = DEPOSIT( R5, R1 ) (X); 46R6 = DEPOSIT( R6, R1 ); 47R7 = DEPOSIT( R7, R1 ) (X); 48R1 = DEPOSIT( R1, R1 ); 49CHECKREG r0, 0x0900D000; 50CHECKREG r1, 0x09000000; 51CHECKREG r2, 0x09000000; 52CHECKREG r3, 0x09100000; 53CHECKREG r4, 0x09020004; 54CHECKREG r5, 0x00000000; 55CHECKREG r6, 0x09000404; 56CHECKREG r7, 0x00000000; 57 58 59imm32 r0, 0x0a00e001; 60imm32 r1, 0x0a00e001; 61imm32 r2, 0x0a00000f; 62imm32 r3, 0x0a000010; 63imm32 r4, 0x0a00e004; 64imm32 r5, 0x0a00e005; 65imm32 r6, 0x0a00e006; 66imm32 r7, 0x0a00e007; 67R0 = DEPOSIT( R0, R2 ); 68R1 = DEPOSIT( R1, R2 ); 69R3 = DEPOSIT( R3, R2 ); 70R4 = DEPOSIT( R4, R2 ); 71R5 = DEPOSIT( R5, R2 ); 72R6 = DEPOSIT( R6, R2 ); 73R7 = DEPOSIT( R7, R2 ); 74R2 = DEPOSIT( R2, R2 ); 75CHECKREG r0, 0x0A008A00; 76CHECKREG r1, 0x0A008A00; 77CHECKREG r2, 0x0A000A00; 78CHECKREG r3, 0x0A000A00; 79CHECKREG r4, 0x0A008A00; 80CHECKREG r5, 0x0A008A00; 81CHECKREG r6, 0x0A008A00; 82CHECKREG r7, 0x0A008A00; 83 84imm32 r0, 0x4b00f001; 85imm32 r1, 0x5b00f001; 86imm32 r2, 0x6b00f002; 87imm32 r3, 0x9f000010; 88imm32 r4, 0x8b00f004; 89imm32 r5, 0x0900f005; 90imm32 r6, 0x0b00f006; 91imm32 r7, 0x0b0af007; 92R0 = DEPOSIT( R0, R3 ); 93R1 = DEPOSIT( R1, R3 ); 94R2 = DEPOSIT( R2, R3 ) (X); 95R4 = DEPOSIT( R4, R3 ); 96R5 = DEPOSIT( R5, R3 ); 97R6 = DEPOSIT( R6, R3 ) (X); 98R7 = DEPOSIT( R7, R3 ); 99R3 = DEPOSIT( R3, R3 ); 100CHECKREG r0, 0x4B009F00; 101CHECKREG r1, 0x5B009F00; 102CHECKREG r2, 0xFFFF9F00; 103CHECKREG r3, 0x9F009F00; 104CHECKREG r4, 0x8B009F00; 105CHECKREG r5, 0x09009F00; 106CHECKREG r6, 0xFFFF9F00; 107CHECKREG r7, 0x0B0A9F00; 108 109imm32 r0, 0x0c0000c0; 110imm32 r1, 0x0c0100c0; 111imm32 r2, 0x0c0200c0; 112imm32 r3, 0x0c0300c0; 113imm32 r4, 0x0c04000c; 114imm32 r5, 0x0c0500c0; 115imm32 r6, 0x0c0600c0; 116imm32 r7, 0x0c0700c0; 117R0 = DEPOSIT( R0, R4 ); 118R1 = DEPOSIT( R1, R4 ); 119R2 = DEPOSIT( R2, R4 ); 120R3 = DEPOSIT( R3, R4 ); 121R5 = DEPOSIT( R5, R4 ) (X); 122R6 = DEPOSIT( R6, R4 ); 123R7 = DEPOSIT( R7, R4 ); 124R4 = DEPOSIT( R4, R4 ); 125CHECKREG r0, 0x0C000C04; 126CHECKREG r1, 0x0C010C04; 127CHECKREG r2, 0x0C020C04; 128CHECKREG r3, 0x0C030C04; 129CHECKREG r4, 0x0C040C04; 130CHECKREG r5, 0xFFFFFC04; 131CHECKREG r6, 0x0C060C04; 132CHECKREG r7, 0x0C070C04; 133 134imm32 r0, 0xa00100d0; 135imm32 r1, 0xa00100d1; 136imm32 r2, 0xa00200d0; 137imm32 r3, 0xa00300d0; 138imm32 r4, 0xa00400d0; 139imm32 r5, 0xa0050007; 140imm32 r6, 0xa00600d0; 141imm32 r7, 0xa00700d0; 142R5 = DEPOSIT( R0, R5 ); 143R6 = DEPOSIT( R1, R5 ) (X); 144R7 = DEPOSIT( R2, R5 ); 145R0 = DEPOSIT( R3, R5 ); 146R1 = DEPOSIT( R4, R5 ) (X); 147R2 = DEPOSIT( R6, R5 ); 148R3 = DEPOSIT( R7, R5 ); 149R4 = DEPOSIT( R5, R5 ); 150CHECKREG r0, 0xA00300C1; 151CHECKREG r1, 0x00000001; 152CHECKREG r2, 0x00000001; 153CHECKREG r3, 0xA00200C1; 154CHECKREG r4, 0xA0010081; 155CHECKREG r5, 0xA0010085; 156CHECKREG r6, 0x00000001; 157CHECKREG r7, 0xA00200C1; 158 159imm32 r0, 0xb0010000; 160imm32 r1, 0xb0010000; 161imm32 r2, 0xb002000f; 162imm32 r3, 0xb0030000; 163imm32 r4, 0xb0040000; 164imm32 r5, 0xb0050000; 165imm32 r6, 0x00237809; 166imm32 r7, 0xb0070000; 167R0 = DEPOSIT( R0, R6 ); 168R1 = DEPOSIT( R1, R6 ); 169R2 = DEPOSIT( R2, R6 ); 170R3 = DEPOSIT( R3, R6 ) (X); 171R4 = DEPOSIT( R4, R6 ); 172R5 = DEPOSIT( R5, R6 ); 173R6 = DEPOSIT( R6, R6 ); 174R7 = DEPOSIT( R7, R6 ); 175CHECKREG r0, 0x23010000; 176CHECKREG r1, 0x23010000; 177CHECKREG r2, 0x2302000F; 178CHECKREG r3, 0x23030000; 179CHECKREG r4, 0x23040000; 180CHECKREG r5, 0x23050000; 181CHECKREG r6, 0x23237809; 182CHECKREG r7, 0x23070000; 183 184imm32 r0, 0xd00100e0; 185imm32 r1, 0xd00100e0; 186imm32 r2, 0xd00200e0; 187imm32 r3, 0xd00300e0; 188imm32 r4, 0xd00400e0; 189imm32 r5, 0xd00500e0; 190imm32 r6, 0xd00600e0; 191imm32 r7, 0x00012345; 192R1 = DEPOSIT( R0, R7 ); 193R2 = DEPOSIT( R1, R7 ); 194R3 = DEPOSIT( R2, R7 ); 195R4 = DEPOSIT( R3, R7 ); 196R5 = DEPOSIT( R4, R7 ) (X); 197R6 = DEPOSIT( R5, R7 ); 198R7 = DEPOSIT( R6, R7 ) (X); 199R0 = DEPOSIT( R7, R7 ); 200CHECKREG r0, 0x00000000; 201CHECKREG r1, 0xD0010008; 202CHECKREG r2, 0xD0010008; 203CHECKREG r3, 0xD0010008; 204CHECKREG r4, 0xD0010008; 205CHECKREG r5, 0x00000008; 206CHECKREG r6, 0x00000008; 207CHECKREG r7, 0x00000008; 208 209 210pass 211