1//Original:/testcases/core/c_dsp32shift_signbits_rl/c_dsp32shift_signbits_rl.dsp
2// Spec Reference: dsp32shift signbits dregs_lo
3# mach: bfin
4
5.include "testutils.inc"
6	start
7
8
9
10imm32 r0, 0x00000000;
11imm32 r1, 0x0000c001;
12imm32 r2, 0x0000c002;
13imm32 r3, 0x0000c003;
14imm32 r4, 0x0000c004;
15imm32 r5, 0x0000c005;
16imm32 r6, 0x0000c006;
17imm32 r7, 0x0000c007;
18R7.L = SIGNBITS R0.L;
19R1.L = SIGNBITS R0.L;
20R2.L = SIGNBITS R0.L;
21R3.L = SIGNBITS R0.L;
22R4.L = SIGNBITS R0.L;
23R5.L = SIGNBITS R0.L;
24R6.L = SIGNBITS R0.L;
25R0.L = SIGNBITS R0.L;
26CHECKREG r1, 0x0000000F;
27CHECKREG r0, 0x0000000F;
28CHECKREG r2, 0x0000000F;
29CHECKREG r3, 0x0000000F;
30CHECKREG r4, 0x0000000F;
31CHECKREG r5, 0x0000000F;
32CHECKREG r6, 0x0000000F;
33CHECKREG r7, 0x0000000F;
34
35imm32 r0, 0x00000001;
36imm32 r1, 0x00008001;
37imm32 r2, 0x0000d002;
38imm32 r3, 0x0000e003;
39imm32 r4, 0x0000f004;
40imm32 r5, 0x0000c005;
41imm32 r6, 0x0000d006;
42imm32 r7, 0x0000e007;
43R0.L = SIGNBITS R1.L;
44R7.L = SIGNBITS R1.L;
45R2.L = SIGNBITS R1.L;
46R3.L = SIGNBITS R1.L;
47R4.L = SIGNBITS R1.L;
48R5.L = SIGNBITS R1.L;
49R6.L = SIGNBITS R1.L;
50R1.L = SIGNBITS R1.L;
51CHECKREG r0, 0x00000000;
52CHECKREG r1, 0x00000000;
53CHECKREG r2, 0x00000000;
54CHECKREG r3, 0x00000000;
55CHECKREG r4, 0x00000000;
56CHECKREG r5, 0x00000000;
57CHECKREG r6, 0x00000000;
58CHECKREG r7, 0x00000000;
59
60
61imm32 r0, 0x0000c001;
62imm32 r1, 0x0000d001;
63imm32 r2, 0x0000c00f;
64imm32 r3, 0x0000e003;
65imm32 r4, 0x0000f004;
66imm32 r5, 0x0000f005;
67imm32 r6, 0x0000f006;
68imm32 r7, 0x0000f007;
69R0.L = SIGNBITS R2.L;
70R1.L = SIGNBITS R2.L;
71R7.L = SIGNBITS R2.L;
72R3.L = SIGNBITS R2.L;
73R4.L = SIGNBITS R2.L;
74R5.L = SIGNBITS R2.L;
75R6.L = SIGNBITS R2.L;
76R2.L = SIGNBITS R2.L;
77CHECKREG r0, 0x00000001;
78CHECKREG r1, 0x00000001;
79CHECKREG r2, 0x00000001;
80CHECKREG r3, 0x00000001;
81CHECKREG r4, 0x00000001;
82CHECKREG r5, 0x00000001;
83CHECKREG r6, 0x00000001;
84CHECKREG r7, 0x00000001;
85
86imm32 r0, 0x00009001;
87imm32 r1, 0x0000a001;
88imm32 r2, 0x0000b002;
89imm32 r3, 0x00000e10;
90imm32 r4, 0x0000c004;
91imm32 r5, 0x0000d005;
92imm32 r6, 0x0000e006;
93imm32 r7, 0x0000f007;
94R0.L = SIGNBITS R3.L;
95R1.L = SIGNBITS R3.L;
96R2.L = SIGNBITS R3.L;
97R7.L = SIGNBITS R3.L;
98R4.L = SIGNBITS R3.L;
99R5.L = SIGNBITS R3.L;
100R6.L = SIGNBITS R3.L;
101R3.L = SIGNBITS R3.L;
102CHECKREG r0, 0x00000003;
103CHECKREG r1, 0x00000003;
104CHECKREG r2, 0x00000003;
105CHECKREG r3, 0x00000003;
106CHECKREG r4, 0x00000003;
107CHECKREG r5, 0x00000003;
108CHECKREG r6, 0x00000003;
109CHECKREG r7, 0x00000003;
110
111imm32 r0, 0x00000000;
112imm32 r1, 0x00010000;
113imm32 r2, 0x00020000;
114imm32 r3, 0x00030000;
115imm32 r4, 0x0000f000;
116imm32 r5, 0x00050000;
117imm32 r6, 0x00060000;
118imm32 r7, 0x00070000;
119R0.L = SIGNBITS R4.L;
120R1.L = SIGNBITS R4.L;
121R2.L = SIGNBITS R4.L;
122R3.L = SIGNBITS R4.L;
123R7.L = SIGNBITS R4.L;
124R5.L = SIGNBITS R4.L;
125R6.L = SIGNBITS R4.L;
126R4.L = SIGNBITS R4.L;
127CHECKREG r0, 0x00000003;
128CHECKREG r1, 0x00010003;
129CHECKREG r2, 0x00020003;
130CHECKREG r3, 0x00030003;
131CHECKREG r4, 0x00000003;
132CHECKREG r5, 0x00050003;
133CHECKREG r6, 0x00060003;
134CHECKREG r7, 0x00070003;
135
136imm32 r0, 0x90010000;
137imm32 r1, 0x00010001;
138imm32 r2, 0x90020000;
139imm32 r3, 0x90030000;
140imm32 r4, 0x90040000;
141imm32 r5, 0x9008f000;
142imm32 r6, 0x90060000;
143imm32 r7, 0x90070000;
144R0.L = SIGNBITS R5.L;
145R1.L = SIGNBITS R5.L;
146R2.L = SIGNBITS R5.L;
147R3.L = SIGNBITS R5.L;
148R4.L = SIGNBITS R5.L;
149R7.L = SIGNBITS R5.L;
150R6.L = SIGNBITS R5.L;
151R5.L = SIGNBITS R5.L;
152CHECKREG r0, 0x90010003;
153CHECKREG r1, 0x00010003;
154CHECKREG r2, 0x90020003;
155CHECKREG r3, 0x90030003;
156CHECKREG r4, 0x90040003;
157CHECKREG r5, 0x90080003;
158CHECKREG r6, 0x90060003;
159CHECKREG r7, 0x90070003;
160
161imm32 r1, 0xa0010000;
162imm32 r2, 0xa002000f;
163imm32 r3, 0xa0030000;
164imm32 r4, 0xa0040000;
165imm32 r5, 0xa0050000;
166imm32 r6, 0xa000fc00;
167imm32 r7, 0xa0070000;
168R0.L = SIGNBITS R6.L;
169R1.L = SIGNBITS R6.L;
170R2.L = SIGNBITS R6.L;
171R3.L = SIGNBITS R6.L;
172R4.L = SIGNBITS R6.L;
173R5.L = SIGNBITS R6.L;
174R7.L = SIGNBITS R6.L;
175R6.L = SIGNBITS R6.L;
176CHECKREG r0, 0x90010005;
177CHECKREG r1, 0xA0010005;
178CHECKREG r2, 0xA0020005;
179CHECKREG r3, 0xA0030005;
180CHECKREG r4, 0xA0040005;
181CHECKREG r5, 0xA0050005;
182CHECKREG r6, 0xA0000005;
183CHECKREG r7, 0xA0070005;
184
185imm32 r0, 0xc0010001;
186imm32 r1, 0xc0010001;
187imm32 r2, 0xc0020002;
188imm32 r3, 0xc0030010;
189imm32 r4, 0xc0040004;
190imm32 r5, 0xc0050005;
191imm32 r6, 0xc0060006;
192imm32 r7, 0xc007e007;
193R0.L = SIGNBITS R7.L;
194R1.L = SIGNBITS R7.L;
195R2.L = SIGNBITS R7.L;
196R3.L = SIGNBITS R7.L;
197R4.L = SIGNBITS R7.L;
198R5.L = SIGNBITS R7.L;
199R6.L = SIGNBITS R7.L;
200R7.L = SIGNBITS R7.L;
201CHECKREG r0, 0xC0010002;
202CHECKREG r1, 0xC0010002;
203CHECKREG r2, 0xC0020002;
204CHECKREG r3, 0xC0030002;
205CHECKREG r4, 0xC0040002;
206CHECKREG r5, 0xC0050002;
207CHECKREG r6, 0xC0060002;
208CHECKREG r7, 0xC0070002;
209
210pass
211