1//Original:/proj/frio/dv/testcases/core/c_interr_disable_enable/c_interr_disable_enable.dsp
2// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10//
11// Include Files
12//
13
14include(std.inc)
15include(selfcheck.inc)
16
17// Defines
18
19#ifndef TCNTL
20#define TCNTL            0xFFE03000
21#endif
22#ifndef TPERIOD
23#define TPERIOD          0xFFE03004
24#endif
25#ifndef TSCALE
26#define TSCALE           0xFFE03008
27#endif
28#ifndef TCOUNT
29#define TCOUNT           0xFFE0300c
30#endif
31#ifndef EVT
32#define EVT              0xFFE02000
33#endif
34#ifndef EVT15
35#define EVT15            0xFFE0203c
36#endif
37#ifndef EVT_OVERRIDE
38#define EVT_OVERRIDE     0xFFE02100
39#endif
40#ifndef ITABLE
41#define ITABLE           0x000FF000
42#endif
43#ifndef PROGRAM_STACK
44#define PROGRAM_STACK    0x000FF100
45#endif
46#ifndef STACKSIZE
47#define STACKSIZE        0x00000300
48#endif
49
50// Boot code
51
52 BOOT :
53INIT_R_REGS(0);                             // Initialize Dregs
54INIT_P_REGS(0);                             // Initialize Pregs
55
56     // CHECK_INIT(p5,   0x00BFFFFC);
57     // CHECK_INIT(p5,   0xE0000000);
58include(symtable.inc)
59CHECK_INIT_DEF(p5);
60
61     // LD32(sp, 0x000FF200);
62LD32_LABEL(sp, KSTACK);   // setup the stack pointer
63FP = SP;                  // and frame pointer
64
65LD32(p0, EVT);              // Setup Event Vectors and Handlers
66LD32_LABEL(r0, EHANDLE);    // Emulation Handler (Int0)
67        [ P0 ++ ] = R0;
68
69LD32_LABEL(r0, RHANDLE);    // Reset Handler (Int1)
70        [ P0 ++ ] = R0;
71
72LD32_LABEL(r0, NHANDLE);    // NMI Handler (Int2)
73        [ P0 ++ ] = R0;
74
75LD32_LABEL(r0, XHANDLE);    // Exception Handler (Int3)
76        [ P0 ++ ] = R0;
77
78        [ P0 ++ ] = R0;                // IVT4 not used
79
80LD32_LABEL(r0, HWHANDLE);   // HW Error Handler (Int5)
81        [ P0 ++ ] = R0;
82
83LD32_LABEL(r0, THANDLE);    // Timer Handler (Int6)
84        [ P0 ++ ] = R0;
85
86LD32_LABEL(r0, I7HANDLE);   // IVG7 Handler
87        [ P0 ++ ] = R0;
88
89LD32_LABEL(r0, I8HANDLE);   // IVG8 Handler
90        [ P0 ++ ] = R0;
91
92LD32_LABEL(r0, I9HANDLE);   // IVG9 Handler
93        [ P0 ++ ] = R0;
94
95LD32_LABEL(r0, I10HANDLE);  // IVG10 Handler
96        [ P0 ++ ] = R0;
97
98LD32_LABEL(r0, I11HANDLE);  // IVG11 Handler
99        [ P0 ++ ] = R0;
100
101LD32_LABEL(r0, I12HANDLE);  // IVG12 Handler
102        [ P0 ++ ] = R0;
103
104LD32_LABEL(r0, I13HANDLE);  // IVG13 Handler
105        [ P0 ++ ] = R0;
106
107LD32_LABEL(r0, I14HANDLE);  // IVG14 Handler
108        [ P0 ++ ] = R0;
109
110LD32_LABEL(r0, I15HANDLE);  // IVG15 Handler
111        [ P0 ++ ] = R0;
112
113LD32(p0, EVT_OVERRIDE);
114        R0 = 0;
115        [ P0 ++ ] = R0;
116        R0 = -1;     // Change this to mask interrupts (*)
117        [ P0 ] = R0;   // IMASK
118
119LD32_LABEL(p1, START);
120
121LD32(p0, EVT15);
122        [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
123CSYNC;
124RAISE 15;    // after we RTI, INT 15 should be taken
125
126LD32_LABEL(r7, START);
127RETI = r7;
128NOP;        // Workaround for Bug 217
129RTI;
130NOP;
131NOP;
132NOP;
133NOP;
134NOP;
135NOP;
136NOP;
137NOP;
138DUMMY:
139	  NOP;
140NOP;
141NOP;
142NOP;
143NOP;
144NOP;
145NOP;
146NOP;
147NOP;
148NOP;
149
150//.code 0x200
151 START :
152        P1 = 0;
153        R7 = 0x0;
154        R6 = 0x1;
155        [ -- SP ] = RETI;        // Enable Nested Interrupts
156
157CLI R1;                                           // stop interrupt
158WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON TMPWR (active state)
159WR_MMR(TPERIOD, 0x00000050, p0, r0);
160WR_MMR(TCOUNT,  0x00000013, p0, r0);
161WR_MMR(TSCALE,  0x00000000, p0, r0);
162CSYNC;
163        // Read the contents of the Timer
164
165RD_MMR(TPERIOD, p0, r2);
166CHECKREG(r2,    0x00000050);
167
168//      RD_MMR(TCOUNT, p0, r3);
169//      CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910
170
171
172WR_MMR(TCNTL,   0x00000003, p0, r0);        // enable Timer (TMPWR, TMREN)
173CSYNC;
174
175RD_MMR(TPERIOD, p0, r4);
176CHECKREG(r4,    0x00000050);
177
178//      RD_MMR(TCNTL, p0, r5);
179//      CHECKREG(r5,    0x0000000B);                // INTERRUPT did happen
180
181WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
182CSYNC;
183NOP;
184WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON Timer Power
185WR_MMR(TPERIOD, 0x00000015, p0, r0);
186WR_MMR(TCOUNT,  0x00000013, p0, r0);
187WR_MMR(TSCALE,  0x00000002, p0, r0);
188WR_MMR(TCNTL,   0x00000007, p0, r0);        // Turn ON Timer (TAUTORLD=1)
189CSYNC;
190NOP;
191NOP;
192NOP;
193NOP;
194NOP;
195NOP;
196NOP;
197NOP;
198NOP;
199NOP;
200NOP;
201NOP;
202NOP;
203NOP;
204NOP;
205JUMP.S label4;
206        R4.L = 0x1111;                             // Will be killed
207        R4.H = 0x1111;                             // Will be killed
208NOP;
209NOP;
210NOP;
211label5: R5.H = 0x7777;
212        R5.L = 0x7888;
213JUMP.S label6;
214        R5.L = 0x1111;                             // Will be killed
215        R5.H = 0x1111;                             // Will be killed
216NOP;
217NOP;
218NOP;
219NOP;
220NOP;
221NOP;
222label4: R4.H = 0x5555;
223        R4.L = 0x6666;
224NOP;
225JUMP.S label5;
226        R5.L = 0x2222;     // Will be killed
227        R5.H = 0x2222;     // Will be killed
228NOP;
229NOP;
230NOP;
231NOP;
232label6: R3.H = 0x7999;
233        R3.L = 0x7aaa;
234NOP;
235NOP;
236NOP;
237NOP;
238NOP;
239NOP;
240NOP;
241                                                    // With auto reload
242        // Read the contents of the Timer
243
244RD_MMR(TPERIOD, p0, r2);
245CHECKREG(r2,    0x00000015);
246
247//      RD_MMR(TCNTL , p0, r3);
248//      CHECKREG(r3,    0x0000000F);
249CHECKREG(r7,    0x00000000);    // no interrupt being serviced
250WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
251CSYNC;
252STI R1;
253NOP;
254CHECKREG(r7,    0x00000001);    // interrupt being serviced
255WR_MMR(TCOUNT,  0x00000005, p0, r0);
256WR_MMR(TCNTL,   0x00000003, p0, r0);        // enable Timer (TMPWR, TMREN)
257CSYNC;
258NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
259NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
260NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
261NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
262NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
263NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
264NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
265NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
266NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
267NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
268NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
269NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
270NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
271CHECKREG(r7,    0x00000002);    // interrupt being serviced
272RAISE 7;
273NOP; NOP;
274CHECKREG(p1,    0x00000001);    // interrupt being serviced
275
276
277
278
279
280dbg_pass;        // Call Endtest Macro
281
282
283
284//*********************************************************************
285//
286// Handlers for Events
287//
288//.code ITABLE
289
290EHANDLE:            // Emulation Handler 0
291RTE;
292
293RHANDLE:            // Reset Handler 1
294RTI;
295
296NHANDLE:            // NMI Handler 2
297RTN;
298
299XHANDLE:            // Exception Handler 3
300RTX;
301
302HWHANDLE:           // HW Error Handler 5
303RTI;
304
305THANDLE:            // Timer Handler 6
306        R7 = R7 + R6;
307RTI;
308
309I7HANDLE:           // IVG 7 Handler
310        P1 += 1;
311RTI;
312
313I8HANDLE:           // IVG 8 Handler
314RTI;
315
316I9HANDLE:           // IVG 9 Handler
317RTI;
318
319I10HANDLE:          // IVG 10 Handler
320RTI;
321
322I11HANDLE:          // IVG 11 Handler
323RTI;
324
325I12HANDLE:          // IVG 12 Handler
326RTI;
327
328I13HANDLE:          // IVG 13 Handler
329RTI;
330
331I14HANDLE:          // IVG 14 Handler
332RTI;
333
334I15HANDLE:          // IVG 15 Handler
335        R5 = RETI;
336        P0 = R5;
337JUMP ( P0 );
338RTI;
339
340.data
341
342.space (STACKSIZE);
343KSTACK:
344NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
345