1//Original:/proj/frio/dv/testcases/core/c_interr_nested/c_interr_nested.dsp 2// Spec Reference: interrupt nested using raises 3# mach: bfin 4# sim: --environment operating 5 6#include "test.h" 7.include "testutils.inc" 8start 9 10include(std.inc) 11include(selfcheck.inc) 12include(gen_int.inc) 13INIT_R_REGS(0); 14INIT_P_REGS(0); 15INIT_I_REGS(0); // initialize the dsp address regs 16INIT_M_REGS(0); 17INIT_L_REGS(0); 18INIT_B_REGS(0); 19//CHECK_INIT(p5, 0xe0000000); 20include(symtable.inc) 21CHECK_INIT_DEF(p5); 22 23#ifndef STACKSIZE 24#define STACKSIZE 0x10 25#endif 26#ifndef EVT 27#define EVT 0xFFE02000 28#endif 29#ifndef EVT15 30#define EVT15 0xFFE0203C 31#endif 32#ifndef EVT_OVERRIDE 33#define EVT_OVERRIDE 0xFFE02100 34#endif 35#ifndef ITABLE 36#define ITABLE 0xF0000000 37#endif 38 39GEN_INT_INIT(ITABLE) // set location for interrupt table 40 41// 42// Reset/Bootstrap Code 43// (Here we should set the processor operating modes, initialize registers, 44// etc.) 45// 46 47BOOT: 48 49 50LD32_LABEL(sp, KSTACK); // setup the stack pointer 51FP = SP; // and frame pointer 52 53LD32(p0, EVT); // Setup Event Vectors and Handlers 54LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 55 [ P0 ++ ] = R0; 56 57LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 58 [ P0 ++ ] = R0; 59 60LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 61 [ P0 ++ ] = R0; 62 63LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 64 [ P0 ++ ] = R0; 65 66 [ P0 ++ ] = R0; // IVT4 not used 67 68LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 69 [ P0 ++ ] = R0; 70 71LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 72 [ P0 ++ ] = R0; 73 74LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 75 [ P0 ++ ] = R0; 76 77LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 78 [ P0 ++ ] = R0; 79 80LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 81 [ P0 ++ ] = R0; 82 83LD32_LABEL(r0, I10HANDLE);// IVG10 Handler 84 [ P0 ++ ] = R0; 85 86LD32_LABEL(r0, I11HANDLE);// IVG11 Handler 87 [ P0 ++ ] = R0; 88 89LD32_LABEL(r0, I12HANDLE);// IVG12 Handler 90 [ P0 ++ ] = R0; 91 92LD32_LABEL(r0, I13HANDLE);// IVG13 Handler 93 [ P0 ++ ] = R0; 94 95LD32_LABEL(r0, I14HANDLE);// IVG14 Handler 96 [ P0 ++ ] = R0; 97 98LD32_LABEL(r0, I15HANDLE);// IVG15 Handler 99 [ P0 ++ ] = R0; 100 101LD32(p0, EVT_OVERRIDE); 102 R0 = 0; 103 [ P0 ++ ] = R0; 104 R0 = -1; // Change this to mask interrupts (*) 105 [ P0 ] = R0; // IMASK 106 107DUMMY: 108 109 R0 = 0 (Z); 110 111LT0 = r0; // set loop counters to something deterministic 112LB0 = r0; 113LC0 = r0; 114LT1 = r0; 115LB1 = r0; 116LC1 = r0; 117 118ASTAT = r0; // reset other internal regs 119 120// The following code sets up the test for running in USER mode 121 122LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a 123 // ReturnFromInterrupt (RTI) 124RETI = r0; // We need to load the return address 125 126// Comment the following line for a USER Mode test 127 128JUMP STARTSUP; // jump to code start for SUPERVISOR mode 129 130RTI; 131 132STARTSUP: 133LD32_LABEL(p1, BEGIN); 134 135LD32(p0, EVT15); 136 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 137CSYNC; 138RAISE 15; // after we RTI, INT 15 should be taken 139 140RTI; 141 142// 143// The Main Program 144// 145STARTUSER: 146LD32_LABEL(sp, USTACK); // setup the stack pointer 147FP = SP; // set frame pointer 148JUMP BEGIN; 149 150//********************************************************************* 151 152BEGIN: 153 154 // COMMENT the following line for USER MODE tests 155 [ -- SP ] = RETI; // enable interrupts in supervisor mode 156 157 // **** YOUR CODE GOES HERE **** 158 159 160 161 // PUT YOUR TEST HERE! 162 // Can't Raise 0, 3, or 4 163 // Raise 1 requires some intelligence so the test 164 // doesn't loop forever - use SFTRESET bit in SEQSTAT (TBD) 165RAISE 2; // RTN 166// RAISE 5; // RTI 167RAISE 6; // RTI 168RAISE 7; // RTI 169// RAISE 8; // RTI 170RAISE 9; // RTI 171RAISE 10; // RTI 172RAISE 11; // RTI 173// RAISE 12; // RTI 174RAISE 13; // RTI 175RAISE 14; // RTI 176RAISE 15; // RTI 177 178CHECKREG(r0, 0x0000000B); 179CHECKREG(r1, 0x0000000C); 180CHECKREG(r2, 0x0000000D); 181CHECKREG(r3, 0x0000000E); 182CHECKREG(r4, 0x00000007); 183CHECKREG(r5, 0x00000008); 184CHECKREG(r6, 0x00000009); 185CHECKREG(r7, 0x0000000A); 186R0 = I0; 187R1 = I1; 188R2 = I2; 189R3 = I3; 190R4 = M0; 191CHECKREG(r0, 0x00000002); 192CHECKREG(r1, 0x00000000); 193CHECKREG(r2, 0x00000005); 194CHECKREG(r3, 0x00000006); 195CHECKREG(r4, 0x00000007); 196 197 198END: 199dbg_pass; // End the test 200 201//********************************************************************* 202 203// 204// Handlers for Events 205// 206 207EHANDLE: // Emulation Handler 0 208RTE; 209 210RHANDLE: // Reset Handler 1 211RTI; 212 213NHANDLE: // NMI Handler 2 214 R0 = 2; 215RTN; 216 217XHANDLE: // Exception Handler 3 218 R1 = 3; 219RTX; 220 221HWHANDLE: // HW Error Handler 5 222 R2 = 5; 223RTI; 224 225THANDLE: // Timer Handler 6 226 R3 = 6; 227RAISE 5; 228RTI; 229 230I7HANDLE: // IVG 7 Handler 231 R4 = 7; 232RTI; 233 234I8HANDLE: // IVG 8 Handler 235 R5 = 8; 236RTI; 237 238I9HANDLE: // IVG 9 Handler 239 R6 = 9; 240RAISE 8; 241RTI; 242 243I10HANDLE: // IVG 10 Handler 244 R7 = 10; 245RTI; 246 247I11HANDLE: // IVG 11 Handler 248 I0 = R0; 249 I1 = R1; 250 I2 = R2; 251 I3 = R3; 252 M0 = R4; 253 R0 = 11; 254RTI; 255 256I12HANDLE: // IVG 12 Handler 257 R1 = 12; 258RTI; 259 260I13HANDLE: // IVG 13 Handler 261 R2 = 13; 262RTI; 263 264I14HANDLE: // IVG 14 Handler 265 R3 = 14; 266RAISE 12; 267RTI; 268 269I15HANDLE: // IVG 15 Handler 270 R4 = 15; 271RTI; 272 273NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug 274 275// 276// Data Segment 277// 278 279.data 280DATA: 281 .space (0x10); 282 283// Stack Segments (Both Kernel and User) 284 285 .space (STACKSIZE); 286KSTACK: 287 288 .space (STACKSIZE); 289USTACK: 290