1//Original:/proj/frio/dv/testcases/core/c_interr_timer_tcount/c_interr_timer_tcount.dsp 2// Spec Reference: interrupt on HW TIMER tcount 3# mach: bfin 4# sim: --environment operating 5 6#include "test.h" 7.include "testutils.inc" 8start 9 10// 11// Include Files 12// 13 14include(std.inc) 15include(selfcheck.inc) 16 17// Defines 18 19#ifndef TCNTL 20#define TCNTL 0xFFE03000 21#endif 22#ifndef TPERIOD 23#define TPERIOD 0xFFE03004 24#endif 25#ifndef TSCALE 26#define TSCALE 0xFFE03008 27#endif 28#ifndef TCOUNT 29#define TCOUNT 0xFFE0300c 30#endif 31#ifndef EVT 32#define EVT 0xFFE02000 33#endif 34#ifndef EVT15 35#define EVT15 0xFFE0203c 36#endif 37#ifndef EVT_OVERRIDE 38#define EVT_OVERRIDE 0xFFE02100 39#endif 40#ifndef ITABLE 41#define ITABLE 0x000FF000 42#endif 43#ifndef PROGRAM_STACK 44#define PROGRAM_STACK 0x000FF100 45#endif 46#ifndef STACKSIZE 47#define STACKSIZE 0x00000300 48#endif 49 50// Boot code 51 52 BOOT : 53INIT_R_REGS(0); // Initialize Dregs 54INIT_P_REGS(0); // Initialize Pregs 55 56 // CHECK_INIT(p5, 0x00BFFFFC); 57 // CHECK_INIT(p5, 0xE0000000); 58include(symtable.inc) 59CHECK_INIT_DEF(p5); 60 61 62LD32(sp, 0x000FF200); 63LD32(p0, EVT); // Setup Event Vectors and Handlers 64 65LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 66 [ P0 ++ ] = R0; 67 68LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 69 [ P0 ++ ] = R0; 70 71LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 72 [ P0 ++ ] = R0; 73 74LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 75 [ P0 ++ ] = R0; 76 77 [ P0 ++ ] = R0; // IVT4 not used 78 79LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 80 [ P0 ++ ] = R0; 81 82LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 83 [ P0 ++ ] = R0; 84 85LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 86 [ P0 ++ ] = R0; 87 88LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 89 [ P0 ++ ] = R0; 90 91LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 92 [ P0 ++ ] = R0; 93 94LD32_LABEL(r0, I10HANDLE); // IVG10 Handler 95 [ P0 ++ ] = R0; 96 97LD32_LABEL(r0, I11HANDLE); // IVG11 Handler 98 [ P0 ++ ] = R0; 99 100LD32_LABEL(r0, I12HANDLE); // IVG12 Handler 101 [ P0 ++ ] = R0; 102 103LD32_LABEL(r0, I13HANDLE); // IVG13 Handler 104 [ P0 ++ ] = R0; 105 106LD32_LABEL(r0, I14HANDLE); // IVG14 Handler 107 [ P0 ++ ] = R0; 108 109LD32_LABEL(r0, I15HANDLE); // IVG15 Handler 110 [ P0 ++ ] = R0; 111 112LD32(p0, EVT_OVERRIDE); 113 R0 = 0; 114 [ P0 ++ ] = R0; 115 R0 = -1; // Change this to mask interrupts (*) 116 [ P0 ] = R0; // IMASK 117 118LD32_LABEL(p1, START); 119 120LD32(p0, EVT15); 121 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 122CSYNC; 123 124RAISE 15; // after we RTI, INT 15 should be taken 125 126LD32_LABEL(r7, START); 127RETI = r7; 128NOP; // Workaround for Bug 217 129RTI; 130NOP; 131NOP; 132 133//.code 0x200 134 START : 135 R7 = 0x0; 136 R6 = 0x1; 137 [ -- SP ] = RETI; // Enable Nested Interrupts 138 139WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state) 140WR_MMR(TPERIOD, 0x00000010, p0, r0); 141WR_MMR(TCOUNT, 0x00000002, p0, r0); 142WR_MMR(TSCALE, 0x00000001, p0, r0); 143WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN) 144CSYNC; 145 146 147RD_MMR(TCNTL, p0, r5); 148CHECKREG(r5, 0x0000000B); 149 150WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer 151CSYNC; 152CHECKREG(r7, 0x00000001); 153 R7 = 0; 154NOP; 155WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power 156WR_MMR(TPERIOD, 0x00000010, p0, r0); 157WR_MMR(TCOUNT, 0x00000002, p0, r0); 158WR_MMR(TSCALE, 0x00000003, p0, r0); 159WR_MMR(TCNTL, 0x00000003, p0, r0); // Turn ON Timer 160CSYNC; 161NOP; 162NOP; 163 // Read the contents of the Timer 164 165 166RD_MMR(TCNTL , p0, r3); 167CHECKREG(r3, 0x0000000B); 168 169CHECKREG(r7, 0x00000001); 170 171 172WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer 173CSYNC; 174NOP; NOP; NOP; 175 176 177 178 179 180dbg_pass; // Call Endtest Macro 181 182 183 184//********************************************************************* 185// 186// Handlers for Events 187// 188 189EHANDLE: // Emulation Handler 0 190RTE; 191 192RHANDLE: // Reset Handler 1 193RTI; 194 195NHANDLE: // NMI Handler 2 196RTN; 197 198XHANDLE: // Exception Handler 3 199RTX; 200 201HWHANDLE: // HW Error Handler 5 202RTI; 203 204THANDLE: // Timer Handler 6 205 R7 = R7 + R6; 206RTI; 207 208I7HANDLE: // IVG 7 Handler 209RTI; 210 211I8HANDLE: // IVG 8 Handler 212RTI; 213 214I9HANDLE: // IVG 9 Handler 215RTI; 216 217I10HANDLE: // IVG 10 Handler 218RTI; 219 220I11HANDLE: // IVG 11 Handler 221RTI; 222 223I12HANDLE: // IVG 12 Handler 224RTI; 225 226I13HANDLE: // IVG 13 Handler 227RTI; 228 229I14HANDLE: // IVG 14 Handler 230RTI; 231 232I15HANDLE: // IVG 15 Handler 233 R5 = RETI; 234 P0 = R5; 235JUMP ( P0 ); 236RTI; 237 238.section MEM_DATA_ADDR_1,"aw" 239 240.space (STACKSIZE); 241STACK: 242NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug 243