1//Original:/testcases/core/c_ldimmhalf_l_dr/c_ldimmhalf_l_dr.dsp
2// Spec Reference: ldimmhalf l dreg
3# mach: bfin
4
5.include "testutils.inc"
6	start
7
8
9
10INIT_R_REGS -1;
11
12
13// test Dreg
14R0.L = 0x0001;
15R1.L = 0x0003;
16R2.L = 0x0005;
17R3.L = 0x0007;
18R4.L = 0x0009;
19R5.L = 0x000b;
20R6.L = 0x000d;
21R7.L = 0x000f;
22CHECKREG r0, 0xffff0001;
23CHECKREG r1, 0xffff0003;
24CHECKREG r2, 0xffff0005;
25CHECKREG r3, 0xffff0007;
26CHECKREG r4, 0xffff0009;
27CHECKREG r5, 0xffff000b;
28CHECKREG r6, 0xffff000d;
29CHECKREG r7, 0xffff000f;
30
31R0.L = 0x0010;
32R1.L = 0x0030;
33R2.L = 0x0050;
34R3.L = 0x0070;
35R4.L = 0x0090;
36R5.L = 0x00b0;
37R6.L = 0x00d0;
38R7.L = 0x00f0;
39CHECKREG r0, 0xffff0010;
40CHECKREG r1, 0xffff0030;
41CHECKREG r2, 0xffff0050;
42CHECKREG r3, 0xffff0070;
43CHECKREG r4, 0xffff0090;
44CHECKREG r5, 0xffff00b0;
45CHECKREG r6, 0xffff00d0;
46CHECKREG r7, 0xffff00f0;
47
48R0.L = 0x0100;
49R1.L = 0x0300;
50R2.L = 0x0500;
51R3.L = 0x0700;
52R4.L = 0x0900;
53R5.L = 0x0b00;
54R6.L = 0x0d00;
55R7.L = 0x0f00;
56CHECKREG r0, 0xffff0100;
57CHECKREG r1, 0xffff0300;
58CHECKREG r2, 0xffff0500;
59CHECKREG r3, 0xffff0700;
60CHECKREG r4, 0xffff0900;
61CHECKREG r5, 0xffff0b00;
62CHECKREG r6, 0xffff0d00;
63CHECKREG r7, 0xffff0f00;
64
65R0.L = 0x1000;
66R1.L = 0x3000;
67R2.L = 0x5000;
68R3.L = 0x7000;
69R4.L = 0x9000;
70R5.L = 0xb000;
71R6.L = 0xd000;
72R7.L = 0xf000;
73CHECKREG r0, 0xffff1000;
74CHECKREG r1, 0xffff3000;
75CHECKREG r2, 0xffff5000;
76CHECKREG r3, 0xffff7000;
77CHECKREG r4, 0xffff9000;
78CHECKREG r5, 0xffffb000;
79CHECKREG r6, 0xffffd000;
80CHECKREG r7, 0xfffff000;
81
82pass
83