1//Original:/testcases/core/c_loopsetup_nested_prelc/c_loopsetup_nested_prelc.dsp
2// Spec Reference: loopsetup nested preload lc0 lc1
3# mach: bfin
4
5.include "testutils.inc"
6	start
7
8
9INIT_R_REGS 0;
10
11ASTAT = r0;
12
13//p0 = 2;
14P1 = 3;
15P2 = 4;
16P3 = 5;
17P4 = 6;
18P5 = 7;
19SP = 8;
20FP = 9;
21
22R0 = 0x05;
23R1 = 0x10;
24R2 = 0x12;
25R3 = 0x14;
26R4 = 0x18;
27R5 = 0x16;
28R6 = 0x16;
29R7 = 0x18;
30
31LC0 = R0;
32LC1 = R1;
33LSETUP ( start1 , end1 ) LC0;
34start1: R0 += 1;
35 R1 += -2;
36LSETUP ( start2 , end2 ) LC1;
37start2: R4 += 4;
38end2: R5 += -5;
39 R3 += 1;
40end1: R2 += 3;
41 R3 += 4;
42LC0 = R7;
43LC1 = R6;
44LSETUP ( start3 , end3 ) LC0;
45start3: R6 += 6;
46LSETUP ( start4 , end4 ) LC1;
47start4: R0 += 1;
48 R1 += -2;
49end4: R2 += 3;
50 R3 += 4;
51end3: R7 += -7;
52 R3 += 1;
53CHECKREG r0, 0x00000037;
54CHECKREG r1, 0xFFFFFFAC;
55CHECKREG r2, 0x000000A8;
56CHECKREG r3, 0x0000007E;
57CHECKREG r4, 0x00000068;
58CHECKREG r5, 0xFFFFFFB2;
59CHECKREG r6, 0x000000A6;
60CHECKREG r7, 0xFFFFFF70;
61
62R0 = 0x05;
63R1 = 0x10;
64R2 = 0x08;
65R3 = 0x0C;
66R4 = 0x40 (X);
67R5 = 0x50 (X);
68R6 = 0x60 (X);
69R7 = 0x70 (X);
70
71LC0 = R2;
72LC1 = R3;
73LSETUP ( start5 , end5 ) LC0;
74start5: R4 += 1;
75LSETUP ( start6 , end6 ) LC1;
76start6: R6 += 4;
77end6: R7 += -5;
78 R3 += 6;
79end5: R5 += -2;
80 R3 += 3;
81CHECKREG r0, 0x00000005;
82CHECKREG r1, 0x00000010;
83CHECKREG r2, 0x00000008;
84CHECKREG r3, 0x0000003F;
85CHECKREG r4, 0x00000048;
86CHECKREG r5, 0x00000040;
87CHECKREG r6, 0x000000AC;
88CHECKREG r7, 0x00000011;
89LSETUP ( start7 , end7 ) LC0;
90start7: R4 += 4;
91end7: R5 += -5;
92 R3 += 6;
93CHECKREG r0, 0x00000005;
94CHECKREG r1, 0x00000010;
95CHECKREG r2, 0x00000008;
96CHECKREG r3, 0x00000045;
97CHECKREG r4, 0x0000004C;
98CHECKREG r5, 0x0000003B;
99CHECKREG r6, 0x000000AC;
100CHECKREG r7, 0x00000011;
101
102P1 = 12;
103P2 = 14;
104P3 = 16;
105P4 = 18;
106P5 = 12;
107SP = 14;
108FP = 16;
109
110R0 = 0x05;
111R1 = 0x10;
112R2 = 0x14;
113R3 = 0x18;
114R4 = 0x16;
115R5 = 0x04;
116R6 = 0x30;
117R7 = 0x30;
118
119LC0 = R5;
120LC1 = R4;
121LSETUP ( start11 , end11 ) LC0;
122start11: R0 += 1;
123 R1 += -1;
124LSETUP ( start15 , end15 ) LC1;
125start15: R4 += 1;
126end15: R5 += -1;
127 R3 += 1;
128end11: R2 += 1;
129 R3 += 1;
130
131
132LSETUP ( start13 , end13 ) LC0 = P5;
133start13: R6 += 1;
134LSETUP ( start12 , end12 ) LC1 = P2;
135start12: R4 += 1;
136end12: R5 += -1;
137 R3 += 1;
138end13: R7 += -1;
139 R3 += 1;
140CHECKREG r0, 0x00000009;
141CHECKREG r1, 0x0000000C;
142CHECKREG r2, 0x00000018;
143CHECKREG r3, 0x0000002A;
144CHECKREG r4, 0x000000D7;
145CHECKREG r5, 0xFFFFFF43;
146CHECKREG r6, 0x0000003C;
147CHECKREG r7, 0x00000024;
148
149R0 = 0x05;
150R1 = 0x10;
151R2 = 0x20;
152R3 = 0x30;
153R4 = 0x40 (X);
154R5 = 0x50 (X);
155R6 = 0x14;
156R7 = 0x08;
157P4 = 6;
158FP = 8;
159
160LC0 = R6;
161LC1 = R7;
162LSETUP ( start14 , end14 ) LC0 = P4;
163start14: R0 += 1;
164 R1 += -1;
165LSETUP ( start16 , end16 ) LC1;
166start16: R6 += 1;
167end16: R7 += -1;
168 R3 += 1;
169LSETUP ( start17 , end17 ) LC1 = FP >> 1;
170start17: R4 += 1;
171end17: R5 += -1;
172 R3 += 1;
173end14: R2 += 1;
174 R3 += 1;
175CHECKREG r0, 0x0000000B;
176CHECKREG r1, 0x0000000A;
177CHECKREG r2, 0x00000026;
178CHECKREG r3, 0x0000003D;
179CHECKREG r4, 0x00000058;
180CHECKREG r5, 0x00000038;
181CHECKREG r6, 0x00000021;
182CHECKREG r7, 0xFFFFFFFB;
183
184pass
185