1//Original:/testcases/core/c_loopsetup_overlap/c_loopsetup_overlap.dsp 2// Spec Reference: loopsetup overlap 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9INIT_R_REGS 0; 10 11ASTAT = r0; 12 13//p0 = 2; 14P1 = 3; 15P2 = 4; 16P3 = 5; 17P4 = 6; 18P5 = 7; 19SP = 8; 20FP = 9; 21 22R0 = 0x05; 23R1 = 0x10; 24R2 = 0x20; 25R3 = 0x30; 26R4 = 0x40 (X); 27R5 = 0x50 (X); 28R6 = 0x60 (X); 29R7 = 0x70 (X); 30LSETUP ( start1 , end1 ) LC0 = P1; 31start1: R0 += 1; 32 R1 += -2; 33LSETUP ( start2 , end2 ) LC1 = P2; 34start2: R4 += 4; 35end2: R5 += -5; 36 R3 += 1; 37end1: R2 += 3; 38 R3 += 4; 39 40LSETUP ( start3 , end3 ) LC1 = P3; 41start3: R6 += 6; 42LSETUP ( start4 , end4 ) LC0 = P4 >> 1; 43start4: R0 += 1; 44 R1 += -2; 45end3: R2 += 3; 46 R3 += 4; 47end4: R7 += -7; 48 R3 += 1; 49CHECKREG r0, 0x0000000F; 50CHECKREG r1, 0xFFFFFFFC; 51CHECKREG r2, 0x0000003E; 52CHECKREG r3, 0x00000044; 53CHECKREG r4, 0x00000070; 54CHECKREG r5, 0x00000014; 55CHECKREG r6, 0x0000007E; 56CHECKREG r7, 0x0000005B; 57 58R0 = 0x05; 59R1 = 0x10; 60R2 = 0x20; 61R3 = 0x30; 62R4 = 0x40 (X); 63R5 = 0x50 (X); 64R6 = 0x60 (X); 65R7 = 0x70 (X); 66LSETUP ( start5 , end5 ) LC0 = P5; 67start5: R4 += 1; 68LSETUP ( start6 , end6 ) LC1 = SP >> 1; 69start6: R6 += 4; 70end5: R7 += -5; 71 R3 += 6; 72end6: R5 += -2; 73 R3 += 3; 74CHECKREG r0, 0x00000005; 75CHECKREG r1, 0x00000010; 76CHECKREG r2, 0x00000020; 77CHECKREG r3, 0x0000004B; 78CHECKREG r4, 0x00000047; 79CHECKREG r5, 0x00000048; 80CHECKREG r6, 0x00000088; 81CHECKREG r7, 0x0000003E; 82LSETUP ( start7 , end7 ) LC0 = FP; 83start7: R4 += 4; 84end7: R5 += -5; 85 R3 += 6; 86CHECKREG r0, 0x00000005; 87CHECKREG r1, 0x00000010; 88CHECKREG r2, 0x00000020; 89CHECKREG r3, 0x00000051; 90CHECKREG r4, 0x0000006B; 91CHECKREG r5, 0x0000001B; 92CHECKREG r6, 0x00000088; 93CHECKREG r7, 0x0000003E; 94 95P1 = 8; 96P2 = 10; 97P3 = 12; 98P4 = 14; 99P5 = 16; 100SP = 18; 101FP = 20; 102 103R0 = 0x05; 104R1 = 0x10; 105R2 = 0x20; 106R3 = 0x30; 107R4 = 0x40 (X); 108R5 = 0x50 (X); 109R6 = 0x60 (X); 110R7 = 0x70 (X); 111LSETUP ( start11 , end11 ) LC1 = P1; 112start11: R0 += 1; 113 R1 += -1; 114LSETUP ( start15 , end15 ) LC0 = P5; 115start15: R4 += 5; 116end11: R5 += -14; 117 R3 += 1; 118end15: R2 += 17; 119 R3 += 12; 120LSETUP ( start13 , end13 ) LC1 = P3; 121start13: R6 += 1; 122LSETUP ( start12 , end12 ) LC0 = P2; 123start12: R4 += 22; 124end13: R5 += -11; 125 R3 += 13; 126end12: R7 += -1; 127 R3 += 14; 128CHECKREG r0, 0x0000000D; 129CHECKREG r1, 0x00000008; 130CHECKREG r2, 0x00000130; 131CHECKREG r3, 0x000000DC; 132CHECKREG r4, 0x00000281; 133CHECKREG r5, 0xFFFFFE27; 134CHECKREG r6, 0x0000006C; 135CHECKREG r7, 0x00000066; 136 137R0 = 0x05; 138R1 = 0x10; 139R2 = 0x20; 140R3 = 0x30; 141R4 = 0x40 (X); 142R5 = 0x50 (X); 143R6 = 0x60 (X); 144R7 = 0x70 (X); 145LSETUP ( start14 , end14 ) LC0 = P4; 146start14: R0 += 21; 147 R1 += -11; 148LSETUP ( start16 , end16 ) LC1 = SP; 149start16: R6 += 10; 150end16: R7 += -12; 151 R3 += 1; 152LSETUP ( start17 , end17 ) LC1 = FP >> 1; 153start17: R4 += 31; 154end14: R5 += -1; 155 R3 += 11; 156end17: R2 += 41; 157 R3 += 1; 158CHECKREG r0, 0x0000012B; 159CHECKREG r1, 0xFFFFFF76; 160CHECKREG r2, 0x000001BA; 161CHECKREG r3, 0x000000AD; 162CHECKREG r4, 0x00000309; 163CHECKREG r5, 0x00000039; 164CHECKREG r6, 0x00000A38; 165CHECKREG r7, 0xFFFFF4A0; 166 167pass 168