1//Original:/proj/frio/dv/testcases/core/c_mode_user/c_mode_user.dsp
2// Spec Reference: mode_user
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10include(std.inc)
11include(selfcheck.inc)
12include(gen_int.inc)
13INIT_R_REGS(0);
14INIT_P_REGS(0);
15INIT_I_REGS(0);     // initialize the dsp address regs
16INIT_M_REGS(0);
17INIT_L_REGS(0);
18INIT_B_REGS(0);
19//CHECK_INIT(p5, 0xe0000000);
20include(symtable.inc)
21CHECK_INIT_DEF(p5);
22
23#ifndef STACKSIZE
24#define STACKSIZE 0x10
25#endif
26#ifndef EVT
27#define EVT  0xFFE02000
28#endif
29#ifndef EVT15
30#define EVT15  0xFFE0203C
31#endif
32#ifndef EVT_OVERRIDE
33#define EVT_OVERRIDE 0xFFE02100
34#endif
35//
36
37////MY_GEN_INT_INIT(0xF0000000) // set location for interrupt table
38
39//
40// Reset/Bootstrap Code
41//   (Here we should set the processor operating modes, initialize registers,
42//    etc.)
43//
44
45BOOT:
46
47                              // in reset mode now
48LD32_LABEL(sp, KSTACK);   // setup the stack pointer
49FP = SP;        // and frame pointer
50
51LD32(p0, EVT);      // Setup Event Vectors and Handlers
52LD32_LABEL(r0, EHANDLE);  // Emulation Handler (Int0)
53    [ P0 ++ ] = R0;
54
55LD32_LABEL(r0, RHANDLE);  // Reset Handler (Int1)
56    [ P0 ++ ] = R0;
57
58LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
59    [ P0 ++ ] = R0;
60
61LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
62    [ P0 ++ ] = R0;
63
64    [ P0 ++ ] = R0;        // IVT4 not used
65
66LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
67    [ P0 ++ ] = R0;
68
69LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
70    [ P0 ++ ] = R0;
71
72LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
73    [ P0 ++ ] = R0;
74
75LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
76    [ P0 ++ ] = R0;
77
78LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
79    [ P0 ++ ] = R0;
80
81LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
82    [ P0 ++ ] = R0;
83
84LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
85    [ P0 ++ ] = R0;
86
87LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
88    [ P0 ++ ] = R0;
89
90LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
91    [ P0 ++ ] = R0;
92
93LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
94    [ P0 ++ ] = R0;
95
96LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
97    [ P0 ++ ] = R0;
98
99LD32(p0, EVT_OVERRIDE);
100    R0 = 0;
101    [ P0 ++ ] = R0;
102    R0 = -1;     // Change this to mask interrupts (*)
103    [ P0 ] = R0;   // IMASK
104
105DUMMY:
106
107    A0 = 0;         // reset accumulators
108    A1 = 0;
109
110    R0 = 0 (Z);
111
112LT0 = r0;       // set loop counters to something deterministic
113LB0 = r0;
114LC0 = r0;
115LT1 = r0;
116LB1 = r0;
117LC1 = r0;
118
119ASTAT = r0;     // reset other internal regs
120
121// The following code sets up the test for running in USER mode
122
123LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
124                        // ReturnFromInterrupt (RTI)
125RETI = r0;      // We need to load the return address
126
127// Comment the following line for a USER Mode test
128
129//  JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
130
131RTI;            // execute this instr put us in USER mode
132
133STARTSUP:
134LD32_LABEL(p1, BEGIN);
135
136LD32(p0, EVT15);
137    [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
138
139RAISE 15;   // after we RTI, INT 15 should be taken,& return to BEGIN in
140                // USER MODE & go to different RAISE in USER mode
141                // until the end of the test.
142
143NOP;    // Workaround for Bug 217
144RTI;
145
146//
147// The Main Program
148//
149STARTUSER:
150LD32_LABEL(sp, USTACK);   // setup the stack pointer
151FP = SP;            // set frame pointer
152JUMP BEGIN;
153
154//*********************************************************************
155
156BEGIN:
157
158                // COMMENT the following line for USER MODE tests
159    [ -- SP ] = RETI;  // enable interrupts in supervisor mode
160
161                // **** YOUR CODE GOES HERE ****
162
163
164
165    // PUT YOUR TEST HERE!
166A1 = A0 = 0;
167ASTAT = R0;
168
169
170// R-reg to P-reg to R reg: stall
171LD32(r0, 0x1357bdad);
172LD32(r1, 0x02dfe804);
173LD32(r2, 0x12345679);
174LD32(r3, 0x34751975);
175LD32(r4, 0x08810990);
176LD32(r5, 0x01a1b0b0);
177LD32(r6, 0x01c1dd00);
178LD32(r7, 0x01e1fff0);
179R5 = R3.L * R1.L, R4 = R3.L * R1.L;            // dsp32mult_pair
180P4 = R5;
181R6 = P4;
182R1 = ( A1 += R5.L * R6.H ), A0 = R5.H * R6.L;   // dsp32mac_pair
183P3 = A0.w;
184P4 = A1.w;
185A1 = A1 (S), A0 = A0 (S);                               // dsp32alu_sat_aa
186R6 = A0.w;
187R7 = A1.w;
188R0 = R7;
189R2 = R0;                          // regmv
190R2 >>>= R3;                         // c_alu2op_arith_r_sft.dsp
191R4 = R2 - R1;
192R5.L = ASHIFT R4.L BY R3.L;
193R6 += -3;                                  //c_compi2opd_dr_add_i7_n.dsp
194I2 = R6;
195I2 += 2;
196I2 += M1;
197R7 = I2;
198
199
200CHECKREG(r0, 0x015AF820);
201CHECKREG(r2, 0x00000000);
202CHECKREG(r3, 0x34751975);
203CHECKREG(r4, 0xFEA507E0);
204CHECKREG(r5, 0xFB3A0000);
205CHECKREG(r6, 0x015AF81D);
206CHECKREG(r7, 0x015AF81F);
207R0 = I0;
208R1 = I1;
209R2 = I2;
210R3 = I3;
211CHECKREG(r0, 0x00000000);
212CHECKREG(r1, 0x00000000);
213CHECKREG(r2, 0x015AF81F);
214CHECKREG(r3, 0x00000000);
215CHECKREG(r4, 0xFEA507E0);
216
217
218END:
219dbg_pass;            // End the test
220
221//*********************************************************************
222
223//
224// Handlers for Events
225//
226
227EHANDLE:            // Emulation Handler 0
228RTE;
229
230RHANDLE:            // Reset Handler 1
231RTI;
232
233NHANDLE:            // NMI Handler 2
234    R0 = RETN;
235    R0 += 2;
236RETN = r0;
237RTN;
238
239XHANDLE:            // Exception Handler 3
240    R1 = RETX;
241    R0 += 1;
242    R1 += 2;
243    R2 += 1;
244    R3 += 1;
245    R4 += 1;
246    R5 += 1;
247    R6 += 1;
248    R7 += 1;
249RETX = r1;
250RTX;
251
252HWHANDLE:           // HW Error Handler 5
253    R2 = RETI;
254    R2 += 2;
255RETI = r2;
256RTI;
257
258THANDLE:            // Timer Handler 6
259    R3 = RETI;
260    R3 += 2;
261RETI = r3;
262RTI;
263
264I7HANDLE:           // IVG 7 Handler
265    R4 = RETI;
266    R4 += 2;
267RETI = r4;
268RTI;
269
270I8HANDLE:           // IVG 8 Handler
271    R5 = RETI;
272    R5 += 2;
273RETI = r5;
274RTI;
275
276I9HANDLE:           // IVG 9 Handler
277    R6 = RETI;
278    R6 += 2;
279RETI = r6;
280RTI;
281
282I10HANDLE:          // IVG 10 Handler
283    R7 = RETI;
284    R7 += 2;
285RETI = r7;
286RTI;
287
288I11HANDLE:          // IVG 11 Handler
289    I0 = R0;
290    I1 = R1;
291    I2 = R2;
292    I3 = R3;
293    M0 = R4;
294    R0 = RETI;
295    R0 += 2;
296RETI = r0;
297RTI;
298
299I12HANDLE:          // IVG 12 Handler
300    R1 = RETI;
301    R1 += 2;
302RETI = r1;
303RTI;
304
305I13HANDLE:          // IVG 13 Handler
306    R2 = RETI;
307    R2 += 2;
308RETI = r2;
309RTI;
310
311I14HANDLE:          // IVG 14 Handler
312    R3 = RETI;
313    R3 += 2;
314RETI = r3;
315RTI;
316
317I15HANDLE:          // IVG 15 Handler
318    R4 = 15;
319RTI;
320
321NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
322
323//
324// Data Segment
325//
326
327.data
328DATA:
329    .space (0x10);
330
331// Stack Segments (Both Kernel and User)
332
333    .space (STACKSIZE);
334KSTACK:
335
336    .space (STACKSIZE);
337USTACK:
338//  .space (STACKSIZE);  // adding this may solve the problem
339