1//Original:/proj/frio/dv/testcases/core/c_seq_ac_regmv_pushpop/c_seq_ac_regmv_pushpop.dsp 2// Spec Reference: sequencer stage AC (regmv + pushpopmultiple) 3# mach: bfin 4# sim: --environment operating 5 6#include "test.h" 7.include "testutils.inc" 8start 9 10include(std.inc) 11include(selfcheck.inc) 12include(gen_int.inc) 13INIT_R_REGS(0); 14INIT_P_REGS(0); 15INIT_I_REGS(0); // initialize the dsp address regs 16INIT_M_REGS(0); 17INIT_L_REGS(0); 18INIT_B_REGS(0); 19//CHECK_INIT(p5, 0xe0000000); 20include(symtable.inc) 21CHECK_INIT_DEF(p5); 22 23#ifndef STACKSIZE 24#define STACKSIZE 0x10 25#endif 26#ifndef EVT 27#define EVT 0xFFE02000 28#endif 29#ifndef EVT15 30#define EVT15 0xFFE0203C 31#endif 32#ifndef EVT_OVERRIDE 33#define EVT_OVERRIDE 0xFFE02100 34#endif 35#ifndef ITABLE 36#define ITABLE DATA_ADDR_1 37#endif 38 39GEN_INT_INIT(ITABLE) // set location for interrupt table 40 41// 42// Reset/Bootstrap Code 43// (Here we should set the processor operating modes, initialize registers, 44// 45 46BOOT: 47 48 // in reset mode now 49LD32_LABEL(sp, KSTACK); // setup the stack pointer 50FP = SP; // and frame pointer 51 52LD32(p0, EVT); // Setup Event Vectors and Handlers 53LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 54 [ P0 ++ ] = R0; 55 56LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 57 [ P0 ++ ] = R0; 58 59LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 60 [ P0 ++ ] = R0; 61 62LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 63 [ P0 ++ ] = R0; 64 65 [ P0 ++ ] = R0; // IVT4 not used 66 67LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 68 [ P0 ++ ] = R0; 69 70LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 71 [ P0 ++ ] = R0; 72 73LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 74 [ P0 ++ ] = R0; 75 76LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 77 [ P0 ++ ] = R0; 78 79LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 80 [ P0 ++ ] = R0; 81 82LD32_LABEL(r0, I10HANDLE);// IVG10 Handler 83 [ P0 ++ ] = R0; 84 85LD32_LABEL(r0, I11HANDLE);// IVG11 Handler 86 [ P0 ++ ] = R0; 87 88LD32_LABEL(r0, I12HANDLE);// IVG12 Handler 89 [ P0 ++ ] = R0; 90 91LD32_LABEL(r0, I13HANDLE);// IVG13 Handler 92 [ P0 ++ ] = R0; 93 94LD32_LABEL(r0, I14HANDLE);// IVG14 Handler 95 [ P0 ++ ] = R0; 96 97LD32_LABEL(r0, I15HANDLE);// IVG15 Handler 98 [ P0 ++ ] = R0; 99 100LD32(p0, EVT_OVERRIDE); 101 R0 = 0; 102 [ P0 ++ ] = R0; 103 R0 = -1; // Change this to mask interrupts (*) 104 [ P0 ] = R0; // IMASK 105CSYNC; 106 107DUMMY: 108 109 R0 = 0 (Z); 110 111LT0 = r0; // set loop counters to something deterministic 112LB0 = r0; 113LC0 = r0; 114LT1 = r0; 115LB1 = r0; 116LC1 = r0; 117 118ASTAT = r0; // reset other internal regs 119 120// The following code sets up the test for running in USER mode 121 122LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a 123 // ReturnFromInterrupt (RTI) 124RETI = r0; // We need to load the return address 125 126// Comment the following line for a USER Mode test 127 128JUMP STARTSUP; // jump to code start for SUPERVISOR mode 129 130RTI; 131 132STARTSUP: 133LD32_LABEL(p1, BEGIN); 134 135LD32(p0, EVT15); 136 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 137 138RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in 139 // SUPERVISOR MODE & go to different RAISE in supervisor mode 140 // until the end of the test. 141 142NOP; // Workaround for Bug 217 143RTI; 144 145// 146// The Main Program 147// 148STARTUSER: 149LD32_LABEL(sp, USTACK); // setup the stack pointer 150FP = SP; // set frame pointer 151JUMP BEGIN; 152 153//********************************************************************* 154 155BEGIN: 156 157 // COMMENT the following line for USER MODE tests 158 [ -- SP ] = RETI; // enable interrupts in supervisor mode 159 160 // **** YOUR CODE GOES HERE **** 161 162 163 164 // PUT YOUR TEST HERE! 165// PUSH 166 R0 = 0x01; 167 R1 = 0x02; 168 R2 = 0x03; 169 R3 = 0x04; 170 R4 = 0x05; 171 R5 = 0x06; 172 R6 = 0x07; 173 R7 = 0x08; 174LD32(p1, 0x12345678); 175LD32(p2, 0x05612496); 176LD32(p3, 0xab5fd490); 177LD32(p4, 0xa581bd94); 178 179 180 //RAISE 2; // RTN 181 P1 = R1; 182 R2 = P1; 183 [ -- SP ] = ( R7:0 ); 184 R1 = 0x12; 185 R2 = 0x13; 186 R3 = 0x14; 187 R4 = 0x15; 188 R5 = 0x16; 189 R6 = 0x17; 190 R7 = 0x18; 191 192 //RAISE 5; // RTI 193 P2 = R2; 194 R3 = P2; 195 196 [ -- SP ] = ( R7:1 ); 197 198 R2 = 0x23; 199 R3 = 0x24; 200 R4 = 0x25; 201 R5 = 0x26; 202 R6 = 0x27; 203 R7 = 0x28; 204 205 //RAISE 6; // RTI 206 P3 = R3; 207 R4 = P3; 208 [ -- SP ] = ( R7:2 ); 209// POP 210 R0 = 0x00; 211 R1 = 0x00; 212 R2 = 0x00; 213 R3 = 0x00; 214 R4 = 0x00; 215 R5 = 0x00; 216 R6 = 0x00; 217 R7 = 0x00; 218 219 //RAISE 7; // RTI 220 P4 = R4; 221 R5 = P4; 222 ( R7:2 ) = [ SP ++ ]; 223 224 225 226CHECKREG(r0, 0x00000000); 227CHECKREG(r1, 0x00000000); 228CHECKREG(r2, 0x00000023); 229CHECKREG(r3, 0x00000024); 230CHECKREG(r4, 0x00000024); 231CHECKREG(r5, 0x00000026); 232CHECKREG(r6, 0x00000027); 233CHECKREG(r7, 0x00000028); 234 235 //RAISE 8; // RTI 236 P1 = R1; 237 R5 = P1; 238 ( R7:1 ) = [ SP ++ ]; 239CHECKREG(r0, 0x00000000); 240CHECKREG(r1, 0x00000012); 241CHECKREG(r2, 0x00000013); 242CHECKREG(r3, 0x00000013); 243CHECKREG(r4, 0x00000015); 244CHECKREG(r5, 0x00000016); 245CHECKREG(r6, 0x00000017); 246CHECKREG(r7, 0x00000018); 247 248 //RAISE 9; // RTI 249 P2 = R2; 250 R5 = P2; 251 ( R7:0 ) = [ SP ++ ]; 252 253CHECKREG(r0, 0x00000001); 254CHECKREG(r1, 0x00000002); 255CHECKREG(r2, 0x00000002); 256CHECKREG(r3, 0x00000004); 257CHECKREG(r4, 0x00000005); 258CHECKREG(r5, 0x00000006); 259CHECKREG(r6, 0x00000007); 260CHECKREG(r7, 0x00000008); 261R0 = I0; 262R1 = I1; 263R2 = I2; 264R3 = I3; 265CHECKREG(r0, 0x00000000); 266CHECKREG(r1, 0x00000000); 267CHECKREG(r2, 0x00000000); 268CHECKREG(r3, 0x00000000); 269 270 271END: 272dbg_pass; // End the test 273 274//********************************************************************* 275 276// 277// Handlers for Events 278// 279 280EHANDLE: // Emulation Handler 0 281RTE; 282 283RHANDLE: // Reset Handler 1 284RTI; 285 286NHANDLE: // NMI Handler 2 287 I0 += 2; 288RTN; 289 290XHANDLE: // Exception Handler 3 291 R1 = 3; 292RTX; 293 294HWHANDLE: // HW Error Handler 5 295 I1 += 2; 296RTI; 297 298THANDLE: // Timer Handler 6 299 I2 += 2; 300RTI; 301 302I7HANDLE: // IVG 7 Handler 303 I3 += 2; 304RTI; 305 306I8HANDLE: // IVG 8 Handler 307 I0 += 2; 308RTI; 309 310I9HANDLE: // IVG 9 Handler 311 I0 += 2; 312RTI; 313 314I10HANDLE: // IVG 10 Handler 315 R7 = 10; 316RTI; 317 318I11HANDLE: // IVG 11 Handler 319 I0 = R0; 320 I1 = R1; 321 I2 = R2; 322 I3 = R3; 323 M0 = R4; 324 R0 = 11; 325RTI; 326 327I12HANDLE: // IVG 12 Handler 328 R1 = 12; 329RTI; 330 331I13HANDLE: // IVG 13 Handler 332 R2 = 13; 333RTI; 334 335I14HANDLE: // IVG 14 Handler 336 R3 = 14; 337RTI; 338 339I15HANDLE: // IVG 15 Handler 340 R4 = 15; 341RTI; 342 343NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug 344 345// 346// Data Segment 347// 348 349.data 350DATA: 351 .space (0x10); 352 353// Stack Segments (Both Kernel and User) 354 355 .space (STACKSIZE); 356KSTACK: 357 358 .space (STACKSIZE); 359USTACK: 360